U.S. patent application number 14/995956 was filed with the patent office on 2016-05-12 for alternative gate dielectric films for silicon germanium and germanium channel materials.
This patent application is currently assigned to GLOBALFOUNDRIES INC.. The applicant listed for this patent is GLOBALFOUNDRIES INC.. Invention is credited to Rohit Galatage, Hoon Kim, Bhagawan Sahu, Shariq Siddiqui.
Application Number | 20160133716 14/995956 |
Document ID | / |
Family ID | 54335537 |
Filed Date | 2016-05-12 |
United States Patent
Application |
20160133716 |
Kind Code |
A1 |
Siddiqui; Shariq ; et
al. |
May 12, 2016 |
ALTERNATIVE GATE DIELECTRIC FILMS FOR SILICON GERMANIUM AND
GERMANIUM CHANNEL MATERIALS
Abstract
Embodiments of the present invention provide a high-K dielectric
film for use with silicon germanium (SiGe) or germanium channel
materials, and methods of fabrication. As a first step of this
process, an interfacial layer (IL) is formed on the semiconductor
substrate providing reduced interface trap density. However, an
ultra-thin layer is used as a barrier film to avoid germanium
diffusion in high-k film and oxygen diffusion from the high-k film
to the interfacial layer (IL), therefore, dielectric films such as
aluminum oxide (Al.sub.2O.sub.3), zirconium oxide, or lanthanum
oxide (La.sub.2O.sub.3) may be used. In addition, these films can
provide high thermal budget. A second dielectric layer is then
deposited on the first dielectric layer. The second dielectric
layer is a high-k dielectric layer, providing a reduced effective
oxide thickness (EOT), resulting in improved device
performance.
Inventors: |
Siddiqui; Shariq; (Albany,
NY) ; Sahu; Bhagawan; (Watervliet, NY) ;
Galatage; Rohit; (Clifton Park, NY) ; Kim; Hoon;
(Clifton Park, NY) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
GLOBALFOUNDRIES INC. |
Grand Cayman |
|
KY |
|
|
Assignee: |
GLOBALFOUNDRIES INC.
Grand Cayman
KY
|
Family ID: |
54335537 |
Appl. No.: |
14/995956 |
Filed: |
January 14, 2016 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
14261559 |
Apr 25, 2014 |
9263541 |
|
|
14995956 |
|
|
|
|
Current U.S.
Class: |
257/411 ;
257/637 |
Current CPC
Class: |
H01L 21/28255 20130101;
H01L 29/513 20130101; H01L 29/517 20130101 |
International
Class: |
H01L 29/51 20060101
H01L029/51 |
Claims
1.-12. (canceled)
13. A semiconductor structure comprising: a silicon germanium
substrate comprising an oxidized top surface; a first dielectric
layer disposed on the oxidized top surface of the silicon germanium
substrate; and a second dielectric layer disposed on the first
dielectric layer.
14. The semiconductor structure of claim 13, wherein the first
dielectric layer comprises aluminum oxide and lanthanum oxide.
15. The semiconductor structure of claim 14, wherein the second
dielectric layer comprises titanium oxide.
16. The semiconductor structure of claim 14, wherein the second
dielectric layer comprises lanthanum oxide.
17. The semiconductor structure of claim 14, wherein the second
dielectric layer comprises zirconium oxide.
18. A semiconductor structure comprising: a semiconductor
substrate; a transistor gate disposed on the semiconductor
substrate; a gate dielectric disposed between the semiconductor
substrate and the transistor gate, wherein the gate dielectric
comprises an oxidized surface region of the semiconductor
substrate, an aluminum oxide layer disposed on the oxidized surface
region, and a high-K dielectric layer disposed on the aluminum
oxide layer.
19. The semiconductor structure of claim 18, wherein the high-K
dielectric layer comprises a titanium oxide layer.
20. The semiconductor structure of claim 18, wherein the high-K
dielectric layer comprises zirconium oxide.
21. A semiconductor structure comprising: a semiconductor substrate
comprising an oxidized top surface; a first dielectric layer
disposed on the oxidized top surface of the semiconductor
substrate; and a second dielectric layer disposed on the first
dielectric layer.
22. The semiconductor structure of claim 21, wherein the first
dielectric layer comprises aluminum oxide and lanthanum oxide.
23. The semiconductor structure of claim 22, wherein the second
dielectric layer comprises titanium oxide.
24. The semiconductor structure of claim 22, wherein the second
dielectric layer comprises lanthanum oxide.
25. The semiconductor structure of claim 22, wherein the second
dielectric layer comprises zirconium oxide.
26. The semiconductor structure of claim 13, wherein the oxidized
top surface has a thickness ranging from about 2 angstroms to about
5 angstroms.
27. The semiconductor structure of claim 18, wherein the oxidized
surface region has a thickness ranging from about 2 angstroms to
about 5 angstroms.
28. The semiconductor structure of claim 21, wherein the oxidized
top surface has a thickness ranging from about 2 angstroms to about
5 angstroms.
Description
FIELD OF THE INVENTION
[0001] The present invention relates generally to semiconductor
fabrication, and more particularly, to gate dielectric films for
silicon germanium and germanium channel materials.
BACKGROUND
[0002] As technology dimensions scale for semiconductor integrated
circuits (ICs), new challenges are being created with regards to
metal-oxide semiconductor field-effect transistors (MOSFETs).
Silicon germanium and germanium channel materials are being
introduced due to higher mobility (electrons and holes) when
compared to conventional Si devices. In order to continuously scale
devices, maintaining equivalent oxide thickness (EOT) and gate
leakage are needed to meet stringent requirements. In addition to
channel materials, scaling further requires gate dielectric
materials with higher k values. It is therefore desirable to have
improvements in dielectric films and methods of fabrication.
SUMMARY
[0003] Embodiments of the present invention provide a high-K
dielectric film for use with silicon germanium (SiGe) or germanium
channel materials and methods of fabrication. As a first step of
this process, an interfacial layer (IL) is formed on the
semiconductor substrate providing reduced interface trap density.
However, an ultra-thin layer is used as a barrier film to avoid
germanium diffusion in high-k film and oxygen diffusion from the
high-k film to the interfacial layer (IL). Therefore, dielectric
films such as aluminum oxide (Al.sub.2O.sub.3), zirconium oxide, or
lanthanum oxide (La.sub.2O.sub.3) may be used. In addition, these
films can provide high thermal budget. A second dielectric layer is
then deposited on the first dielectric layer. The second dielectric
layer is a high-k dielectric layer providing a reduced effective
oxide thickness (EOT), resulting in improved device
performance.
[0004] In a first aspect, embodiments of the present invention
provide a method of forming a semiconductor structure, comprising:
performing a surface oxidation of a semiconductor substrate to form
an interfacial oxide layer; depositing a first dielectric layer on
the interfacial oxide layer; and depositing a second dielectric
layer on the first dielectric layer.
[0005] In a second aspect, embodiments of the present invention
provide a semiconductor structure comprising: a silicon germanium
substrate comprising an oxidized top surface; a first dielectric
layer disposed on the oxidized top surface of the silicon germanium
substrate; and a second dielectric layer disposed on the first
dielectric layer.
[0006] In a third aspect, embodiments of the present invention
provide a semiconductor structure comprising: a semiconductor
substrate; a transistor gate disposed on the semiconductor
substrate; a gate dielectric disposed between the semiconductor
substrate and the transistor gate, wherein the gate dielectric
comprises an oxidized surface region of the semiconductor
substrate, an aluminum oxide layer disposed on the oxidized surface
region, and a high-K dielectric layer disposed on the aluminum
oxide layer.
BRIEF DESCRIPTION OF THE DRAWINGS
[0007] The accompanying drawings, which are incorporated in and
constitute a part of this specification, illustrate several
embodiments of the present teachings and, together with the
description, serve to explain the principles of the present
teachings.
[0008] Certain elements in some of the figures may be omitted, or
illustrated not-to-scale, for illustrative clarity. The
cross-sectional views may be in the form of "slices", or
"near-sighted" cross-sectional views, omitting certain background
lines which would otherwise be visible in a "true" cross-sectional
view, for illustrative clarity.
[0009] Often, similar elements may be referred to by similar
numbers in various figures (FIGs) of the drawing, in which case
typically the last two significant digits may be the same, the most
significant digit being the number of the drawing figure (FIG).
Furthermore, for clarity, some reference numbers may be omitted in
certain drawings.
[0010] FIG. 1A shows a semiconductor structure at a starting point
for embodiments of the present invention.
[0011] FIG. 1B shows a semiconductor structure after a subsequent
process step of performing a surface oxidation in accordance with
illustrative embodiments.
[0012] FIG. 1C shows a semiconductor structure after a subsequent
process step of depositing a first dielectric layer in accordance
with illustrative embodiments.
[0013] FIG. 1D shows a semiconductor structure after a subsequent
process step of depositing a second dielectric layer in accordance
with illustrative embodiments.
[0014] FIG. 2 shows a transistor gate structure in accordance with
illustrative embodiments.
[0015] FIG. 3 is a flowchart indicating process steps for
illustrative embodiments.
DETAILED DESCRIPTION
[0016] It will be appreciated that this disclosure may be embodied
in many different forms and should not be construed as limited to
the exemplary embodiments set forth herein. Rather, these exemplary
embodiments are provided so that this disclosure will be thorough
and complete and will fully convey the scope of this disclosure to
those skilled in the art. The terminology used herein is for the
purpose of describing particular embodiments only and is not
intended to be limiting of this disclosure. For example, as used
herein, the singular forms "a", "an", and "the" are intended to
include the plural forms as well, unless the context clearly
indicates otherwise. Furthermore, the use of the terms "a", "an",
etc., do not denote a limitation of quantity, but rather denote the
presence of at least one of the referenced items. It will be
further understood that the terms "comprises" and/or "comprising",
or "includes" and/or "including", when used in this specification,
specify the presence of stated features, regions, integers, steps,
operations, elements, and/or components, but do not preclude the
presence or addition of one or more other features, regions,
integers, steps, operations, elements, components, and/or groups
thereof.
[0017] Reference throughout this specification to one "embodiment,"
"an embodiment," "embodiments," "exemplary embodiments," or similar
language means that a particular feature, structure, or
characteristic described in connection with the embodiment is
included in at least one embodiment of the present invention. Thus,
appearances of the phrases "in one embodiment," "in an embodiment,"
"in embodiments" and similar language throughout this specification
may, but do not necessarily, all refer to the same embodiment.
[0018] The terms "overlying" or "atop", "positioned on" or
"positioned atop", "underlying", "beneath" or "below" mean that a
first element, such as a first structure (e.g., a first layer), is
present on a second element, such as a second structure (e.g., a
second layer), wherein intervening elements, such as an interface
structure (e.g., interface layer), may be present between the first
element and the second element.
[0019] FIG. 1A shows a semiconductor structure 100 at a starting
point for embodiments of the present invention. Semiconductor
structure 100 comprises semiconductor substrate 102. In
embodiments, semiconductor substrate 102 is a silicon germanium or
germanium substrate. In embodiments, the silicon germanium
substrate may be of the form Si(1-x)Ge(x), where x ranges from
about 0.25 to about 1.0. Substrate 102 may be used to form fins
and/or source/drain regions of a transistor in subsequent
processing.
[0020] FIG. 1B shows semiconductor structure 100 after a subsequent
process step of performing a surface oxidation in accordance with
illustrative embodiments. As a result of the surface oxidation, an
oxidized top surface region 104 is formed on the top surface of
semiconductor substrate 102. The oxidized surface region 104 serves
as an interfacial oxide layer and has a thickness D1. In
embodiments, thickness D1 ranges from about 2 angstroms to about 5
angstroms. In embodiments, the oxidized surface region 104 is
formed by a remote plasma oxidation process. In such a process, a
plasma is formed in a remote plasma region of a processing tool,
and then the plasma is flowed to a processing region of a process
chamber of a tool where the semiconductor substrate 102 is
disposed, creating a very thin oxidized surface region 104. This
method provides a precise control over an interfacial layer (IL)
and control over Ge oxide species.
[0021] FIG. 1C shows semiconductor structure 100 after a subsequent
process step of depositing a first dielectric layer 106 in
accordance with illustrative embodiments. In embodiments, the first
dielectric layer comprises aluminum oxide (Al.sub.2O.sub.3). In
other embodiments, the first dielectric layer comprises silicon
nitride (Si.sub.3N.sub.4) or lanthanum oxide (La.sub.2O.sub.3). The
first dielectric layer 106 serves as a diffusion barrier for
oxygen, which serves to preserve the oxidized surface region 104.
Additionally, first dielectric layer 106 serves to provide higher
thermal stability for a strained SiGe channel. In embodiments, the
first dielectric layer 106 is deposited via an atomic layer
deposition (ALD) process. The first dielectric layer 106 has a
thickness D2. In embodiments, thickness D2 ranges from about 5
angstroms to about 10 angstroms. Following the deposition of the
first dielectric layer 106, an additional process step of a
densifying plasma ozone oxidation process may be performed. This
serves to further densify the oxidized surface region and to
further reduce the interface trap density 104.
[0022] FIG. 1D shows semiconductor structure 100 after a subsequent
process step of depositing a second dielectric layer 108 in
accordance with illustrative embodiments. In embodiments, the
second dielectric layer comprises titanium oxide (TiO.sub.2). In
other embodiments, the second dielectric layer comprises hafnium
oxide (HfO.sub.2). In other embodiments, the second dielectric
layer comprises lanthanum oxide (La.sub.2O.sub.3). In embodiments,
the second dielectric layer 108 is deposited via an atomic layer
deposition (ALD) process. The second dielectric layer 108 has a
thickness D3. In some embodiments, thickness D3 ranges from about
13 angstroms to about 17 angstroms. In some embodiments, thickness
D3 ranges from about 25 angstroms to about 35 angstroms. In
particular, when the second dielectric layer 108 is comprised of
hafnium oxide, the thickness D3 may range from about 8 angstroms to
about 17 angstroms. However, when the second dielectric layer 108
is comprised of titanium oxide, the thickness D3 may range from
about 25 angstroms to about 35 angstroms. This is because the
dielectric constant of titanium (40 to 85) is higher than that of
hafnium oxide (.about.19-21). This is advantageous in a variety of
aspects. The use of titanium oxide allows a thicker physical film
to be formed while preserving a reduced EOT. Furthermore, the
increased physical thickness serves to reduce undesirable device
leakage when the film is used as a gate dielectric. The first
dielectric layer 106 acts as a barrier between the interfacial
layer (IL) or oxidized surface region 104 and the second dielectric
layer 108, and serves to prevent Ge diffusion into high-k and
oxygen diffusion from high-k to SiGe substrate, which would
adversely affect device performance. Embodiments of the present
invention also utilize titanium oxide as the second dielectric
layer due to higher dielectric constant. In addition, due to higher
dielectric constant, a thicker film can be used without increasing
EOT, while improving device leakage characteristics.
[0023] FIG. 2 shows a transistor gate structure 200 in accordance
with illustrative embodiments. Gate structure 200 comprises
semiconductor substrate 202. In embodiments, semiconductor
substrate 202 is a silicon germanium substrate. In embodiments, the
silicon germanium substrate may be of the form Si(1-x)Ge(x), where
x ranges from about 0.25 to about 1.0. Gate structure 200 comprises
gate electrode 210, which is disposed on gate dielectric 203, which
is in turn disposed on semiconductor substrate 202. The gate
dielectric 203 is comprised of an oxidized surface region 204, a
first dielectric layer 206 disposed on the oxidized surface region
204, and a second dielectric layer 208 disposed on the first
dielectric layer 206. In embodiments, gate dielectric 203 is
fabricated as described and shown in FIGS. 1A-1D. In embodiments,
the gate electrode 210 may be comprised of tungsten. Additional
metal layers, such as work function layers (not shown), may also be
present within the gate electrode 210. Second dielectric layer 208
is a high-K dielectric layer (k>5) and may be comprised of
hafnium oxide, titanium oxide, zirconium oxide, or lanthanum oxide.
Other high-K materials may also be possible, and embodiments of the
present invention are not limited to these materials. In
embodiments, the first dielectric layer 206 may be comprised of
aluminum oxide or silicon nitride. The oxidized surface region 204
may be formed using a remote plasma oxidation process. A recess
process may be performed to remove the portion of the oxidized
surface region that is not directly underneath the gate electrode
210. From this point forward, industry-standard process steps such
as spacer formation, source/drain formation, implantation, back end
of line (BEOL) wiring, and packaging, may be performed to complete
a functional integrated circuit.
[0024] FIG. 3 is a flowchart 300 indicating process steps for
illustrative embodiments. In process step 350, a surface oxidation
is performed. This may include a remote plasma oxidation process.
When performed on a silicon germanium substrate, the resulting
surface oxide is a combination of silicon oxide and germanium
oxide. In process step 352, a first dielectric layer is deposited.
This may be performed using atomic layer deposition (ALD). In
embodiments, the first dielectric layer may include aluminum oxide,
silicon nitride or lanthanum oxide. In process step 354, a plasma
ozone oxidation process is performed. This serves to further
densify the surface oxidation layer. In process step 356, a second
dielectric is deposited. In embodiments, the second dielectric may
include, but is not limited to, titanium oxide, hafnium oxide, and
lanthanum oxide. The second dielectric preferably has a very high
dielectric constant value (e.g., k>20) such that it enables the
deposition of a thicker film (e.g. 25 to 35 angstroms) while still
maintaining an acceptable EOT. Thus, embodiments of the present
invention enable a dielectric film with improved manufacturability,
reduced EOT and Dit, and improved device leakage
characteristics.
[0025] While the invention has been particularly shown and
described in conjunction with exemplary embodiments, it will be
appreciated that variations and modifications will occur to those
skilled in the art. For example, although the illustrative
embodiments are described herein as a series of acts or events, it
will be appreciated that the present invention is not limited by
the illustrated ordering of such acts or events unless specifically
stated. Some acts may occur in different orders and/or concurrently
with other acts or events apart from those illustrated and/or
described herein, in accordance with the invention. In addition,
not all illustrated steps may be required to implement a
methodology in accordance with the present invention. Furthermore,
the methods according to the present invention may be implemented
in association with the formation and/or processing of structures
illustrated and described herein as well as in association with
other structures not illustrated. Therefore, it is to be understood
that the appended claims are intended to cover all such
modifications and changes that fall within the true spirit of the
invention.
* * * * *