U.S. patent application number 14/996232 was filed with the patent office on 2016-05-12 for mask set having feature patterns and dummy patterns.
The applicant listed for this patent is UNITED MICROELECTRONICS CORP.. Invention is credited to Yu-Cheng Tung.
Application Number | 20160131969 14/996232 |
Document ID | / |
Family ID | 52626019 |
Filed Date | 2016-05-12 |
United States Patent
Application |
20160131969 |
Kind Code |
A1 |
Tung; Yu-Cheng |
May 12, 2016 |
MASK SET HAVING FEATURE PATTERNS AND DUMMY PATTERNS
Abstract
A mask set includes a first mask, a second mask, and a third
mask respectively include a first layout pattern, a second layout
pattern, and a third layout pattern. The first layout pattern
includes mandrel patterns and dummy mandrel patterns. The second
layout pattern includes geometric patterns covering portions of the
mandrel patterns and portions of the dummy mandrel patterns. The
third layout pattern includes dummy pad patterns which are
laterally spaced apart from the mandrel patterns and the dummy
mandrel patterns.
Inventors: |
Tung; Yu-Cheng; (Kaohsiung
City, TW) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
UNITED MICROELECTRONICS CORP. |
Hsin-Chu City |
|
TW |
|
|
Family ID: |
52626019 |
Appl. No.: |
14/996232 |
Filed: |
January 15, 2016 |
Related U.S. Patent Documents
|
|
|
|
|
|
Application
Number |
Filing Date |
Patent Number |
|
|
14023472 |
Sep 11, 2013 |
9274413 |
|
|
14996232 |
|
|
|
|
Current U.S.
Class: |
430/5 |
Current CPC
Class: |
G03F 1/70 20130101; H01L
21/845 20130101; H01L 21/823431 20130101; H01L 21/3086 20130101;
G03F 1/38 20130101 |
International
Class: |
G03F 1/38 20060101
G03F001/38 |
Claims
1. A mask set for defining a layout pattern of a semiconductor
device, comprising: a first mask comprising a first layout pattern,
wherein the first layout pattern comprises a plurality of mandrel
patterns belonging to the layout pattern and a plurality of dummy
mandrel patterns not belonging to the layout pattern; a second mask
comprising a second layout pattern, wherein the second layout
pattern comprises a plurality of geometric patterns, and the
geometric patterns cover portions of the mandrel patterns and
portions of the dummy mandrel patterns; and a third mask comprising
a third layout pattern, wherein the third layout pattern comprises
a plurality of dummy pad patterns not belonging to the layout
pattern, and the dummy pad patterns are laterally spaced apart from
the mandrel patterns and the dummy mandrel patterns.
2. The mask set of claim 1, wherein the mandrel patterns and the
dummy mandrel patterns have same dimensions.
3. The mask set of claim 1, wherein at least one of the dummy
mandrel patterns is non-printable.
4. The mask set of claim 1, wherein the second layout pattern
further comprises a plurality of dummy geometric patterns, and at
least one of the dummy geometric patterns is non-printable.
5. The mask set of claim 4, wherein dimensions of the dummy pad
patterns are greater than dimensions of the dummy mandrel patterns
and the dummy geometric patterns.
6. The mask set of claim 1, wherein dimensions of the dummy pad
patterns are larger than dimensions of the mandrel patterns and the
dummy mandrel patterns.
7. The mask set of claim 1, wherein all of the dummy pad patterns
are printable.
8. The mask set of claim 1, wherein the third layout pattern
further comprising a plurality of pad patterns belonging to the
layout pattern.
9. The mask set of claim 8, wherein at least one of the pad
patterns overlaps at least one of the mandrel patterns.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application is a division of U.S. application Ser. No.
14/023,472, filed Sep. 11, 2013, the disclosure of which is hereby
incorporated herein by reference in its entirety.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention generally relates to the field of
layout patterns of semiconductor devices, and more particularly to
a mask set having feature patterns and dummy patterns, which is
configured to fabricate a layout pattern in non-planar
semiconductor devices.
[0004] 2. Description of the Prior Art
[0005] Integrated circuits (IC) are made of devices and
interconnections, which are formed through patterned features in
different layers. During the fabrication process of ICs, the
photolithography is an essential technique. The photolithography is
used to form designed patterns, such as implantation patterns or
layout patterns, on at least a photomask, and then to precisely
transfer such patterns to a photoresist layer through exposure and
development steps. Finally, by performing several semiconductor
processes such as etching processes, ion implantations, depositions
and so forth, complicated and sophisticated IC structures can be
obtained.
[0006] With the continuous miniaturization of semiconductor devices
and the remarkable advance in fabrication techniques of
semiconductor devices, the conventional lithography process meets
its limitation due to printability and manufacturability problems.
To meet the requirements of device design rules which continue to
push the resolution limits of existing processes and tooling, a
double patterning technique (DPT) has been developed and taken as
one of the most promising lithography technologies for 32 nanometer
(nm) node and 22 nm node patterning, since it can increase the
half-pitch resolution up to twice higher by using current
infrastructures. Besides, three-dimensional or non-planar
transistor technology, such as the fin field effect transistor
(FinFET) technology, has also been developed to replace planar MOS
transistors. Generally, patterned structures in a FinFET, such as
fin structures, can be obtained by sidewall image transfer
(SIT).
[0007] Although the above-mentioned technologies, i.e. DPT and 3-D
transistor technology, have been widely adopted by semiconductor
manufacturers and successively overcome major drawbacks in the
fabricating process, there are still some problems needed to be
solved. For example, in order to prevent or overcome optical
problems, such as optical proximity effect, in photolithography
processes and polishing problems, such as dishing phenomenon, in
planarization processes, dummy patterns are often added to layout
patterns of semiconductor devices through proper computer
simulation at the beginning of the fabrication process. However,
how to effectively distribute different dummy patterns over
individual photomasks is still a major topic for study in the
semiconductor field.
SUMMARY OF THE INVENTION
[0008] In accordance with the present invention, the disadvantage
and problems associated with a mask set configured to fabricate a
layout pattern in non-planar semiconductor devices have been
substantially reduced or eliminated. In particular, a mask set
having feature patterns and dummy patterns is provided during the
process of fabricating non-planar semiconductor devices.
[0009] In accordance with one embodiment of the present invention,
a mask set for defining a layout pattern is provided. The mask set
includes a first mask, a second mask, and a third mask respectively
include a first layout pattern, a second layout pattern, and a
third layout pattern. The first layout pattern includes mandrel
patterns and dummy mandrel patterns. The second layout pattern
includes geometric patterns covering portions of the mandrel
patterns and portions of the dummy mandrel patterns. The third
layout pattern includes dummy pad patterns which are laterally
spaced apart from the mandrel patterns and the dummy mandrel
patterns.
[0010] These and other objectives of the present invention will no
doubt become obvious to those of ordinary skill in the art after
reading the following detailed description of the preferred
embodiment that is illustrated in the various figures and
drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0011] For a more complete understanding of the present invention
and its advantages, references is now made to the following
description, taken in conjunction with the accompanying drawings,
in which:
[0012] FIG. 1 illustrates an exemplary layout pattern in accordance
with one embodiment of the present invention;
[0013] FIG. 2 illustrates an exemplary first mask with a first
layout pattern in accordance with one embodiment of the present
invention;
[0014] FIG. 3 illustrates a semiconductor structure including at
least a first layout pattern surrounded by spacers in accordance
with one embodiment of the present invention;
[0015] FIG. 4 is a schematic cross-sectional diagram taken along a
line A-A' in FIG. 4;
[0016] FIG. 5 illustrates an exemplary second mask with a second
layout pattern in accordance with one embodiment of the present
invention;
[0017] FIG. 6 illustrates a semiconductor structure after the step
of transferring a second layout pattern to a layer over a substrate
in accordance with one embodiment of the present invention;
[0018] FIG. 7 illustrates an exemplary third mask with a third
layout pattern in accordance with one embodiment of the present
invention;
[0019] FIG. 8 illustrates a layout pattern fabricated on a
substrate after the step of transferring a third layout pattern in
accordance with one embodiment of the present invention;
[0020] FIG. 9 is a schematic cross-sectional diagram taken along a
line B-B' in FIG. 8;
[0021] FIG. 10 illustrates a layout pattern fabricated on a
substrate after an etching process in accordance with one
embodiment of the present invention;
[0022] FIG. 11 is a flowchart detailing an exemplary method for
forming a layout pattern on a substrate in accordance with one
embodiment of the present invention.
DETAILED DESCRIPTION
[0023] In the following description, numerous specific details are
given to provide a thorough understanding of the invention. It
will, however, be apparent to one skilled in the art that the
invention may be practiced without these specific details.
Furthermore, some well-known system configurations and process
steps are not disclosed in detail, as these should be well-known to
those skilled in the art.
[0024] Likewise, the drawings showing embodiments of the structures
or apparatus are not to scale and some dimensions are exaggerated
for clarity of presentation. Also, where multiple embodiments are
disclosed and described as having some features in common, like or
similar features will usually be described with same reference
numerals for ease of illustration and description thereof.
[0025] FIG. 1 to FIG. 10 are schematic diagrams showing a method
for forming a layout pattern on a substrate by sidewall image
transfer (SIT) technology according to one embodiment of the
present invention. FIG. 11 is a simplified flowchart showing a
method for forming a layout pattern on a substrate according to one
embodiment of the present invention. Please refer to FIG. 1 and
FIG. 11; in step S110, an original layout pattern 10 is first
provided to a database of a computer system. The original layout
pattern 10, which is an ideal designed pattern supposed to be
formed in final products, may include feature patterns used to
construct integrated circuits (IC) such as device patterns, contact
pad patterns, or layout of circuits, but not limited thereto.
According to this embodiment, the original layout pattern 10 is
classified into at least a first feature pattern 12 and a second
feature pattern 14. The first feature pattern 12 may consist of
straight line patterns 16 and bent line patterns 18 with the same
widths, while the second feature pattern 14 may consist of
rectangular pad patterns (not shown) connecting to the
corresponding straight line patterns 16 or bent line patterns 18.
As depicted in FIG. 1, since the first feature pattern 12 is
preferably used to construct active regions in semiconductor
devices and the second feature pattern 14 is preferably used to
construct interconnection pads, the dimensions of the straight line
patterns 16 and the bent line patterns 18 are smaller than those of
the pad patterns, but not limited thereto.
[0026] After the classification of the original layout pattern 10,
step S120 and step S130 are carried out sequentially. More
precisely, in step S120, at least a first layout pattern, a second
layout pattern, and a third layout pattern are generated and stored
in a computer database according to the original layout pattern. In
step S130, the first layout pattern, the second layout pattern, and
the third layout pattern are respectively defined on a first mask,
a second mask, and a third mask. The first mask, a second mask, and
a third mask may be used to constitute a mask set according to the
present embodiment. After step S120 and step S130, the first layout
pattern, the second layout pattern, and the third layout pattern
may be further respectively transferred to layers on or over a
substrate in the subsequent fabrication process. It should be noted
that, since the contour of the layout patterns formed in the layers
on or over the substrate usually deviates from what was intended to
be formed, a suitable correction method, such as optical proximity
correction (OPC), is often carried out to correct them. For
example, the usual way of correcting the layout patterns includes
an adjustment of the line width of the line segment, and the
disposition of printable or non-printable assist patterns, such as
serif or hammerhead patterns at the line end or the corner.
Alternatively, some of the assist patterns on the individual masks
may be disposed apart from adjacent feature patterns. In this way,
both the line width adjustment and the use of assist patterns may
be successfully used to avoid the deviation of the transferred
patterns, such as rounded right-angle corners, shortened line-ends,
or increased/decreased line widths when the layout patterns on the
corresponding photomasks are later transferred onto the layers on
the substrate. Through the OPC process and photomask-making
process, the corrected layout patterns are generated and
respectively defined on the corresponding photomasks.
[0027] For the sake of clarity, the actual layout of the first
layout pattern, the second layout pattern and the third layout
pattern, and the process for transferring the layout patterns from
the masks to the layers on the substrate are described in detail in
the following paragraphs.
[0028] Please refer to FIG. 2. FIG. 2 is a schematic diagram
showing a first mask with a first layout pattern. As depicted in
FIG. 2, the first layout pattern 100 includes mandrel patterns 22
and dummy mandrel patterns 24. The mandrel patterns 22 may consist
of straight line patterns 26 and L-shaped patterns 28. In contrast,
the dummy mandrel patterns 24 may only consist of straight line
patterns (not shown), but not limited thereto. Preferably, the
dimensions of the mandrel patterns 22 are the same as those of the
dummy mandrel patterns 24. According to this embodiment, all the
dummy mandrel patterns 24 shown in FIG. 2 are printable and have
dimensions the same as those of the mandrel patterns 22 according
to this embodiment. However, in another case, some of the dummy
mandrel patterns may be non-printable so that they would not be
transferred to a layer on or over a substrate in the following
process. It should be noted that, since the first pattern layout
100 is corrected by the OPC process in advance, the straight line
patterns 24 and 26 and L-shaped patterns 28 formed on the first
mask 20 would never be perfect straight line patterns and perfect
L-shaped patterns, they may have slightly widened line ends and
slightly inwards and/or outwards corners instead.
[0029] Then, please refer to FIG. 3 and FIG. 4. FIG. 3 is a
schematic diagram showing a first layout pattern transferred to a
layer over a substrate and surrounded by spacers. FIG. 4 is
schematic cross-sectional diagram taken along a line A-A' in FIG.
4. Referring to FIG. 3 and FIG. 4, in step S140, the first layout
pattern 100 formed on the first mask 20 is transferred to the layer
over the substrate 30. For example, in a case that the substrate 30
is covered by layers including a target layer 31, a hard mask layer
32, and a sacrificial layer (not shown), the first layout pattern
100 may be transferred from the first mask 20 to the sacrificial
layer through a suitable photolithographic process and an etching
process so as to form a first patterned layer 33. It should be
noted that there may be another layer, such as a pad layer or
another hard mask layer, disposed on or under the hard mask layer
32, but not limited thereto.
[0030] The above-mentioned substrate 30 may be a semiconductor
substrate (such as a silicon substrate), a silicon containing
substrate (such as a silicon carbide substrate), a III-V
group-on-silicon (such as GaN-on-silicon) substrate, a
graphene-on-silicon substrate, a silicon-on-insulator (SOI)
substrate or an epitaxial layer containing substrate. The target
layer 31 may be a semiconductor layer made of materials the same as
or different from that of the underlying substrate 30. The hard
mask layer 32 are made of a dielectric layer, such as silicon oxide
layer or a silicon nitride layer, but not limited thereto. The
sacrificial layer may be made of silicon material, III-V group
semiconductors or other suitable semiconductor materials, and
preferably be made of polysilicon material.
[0031] It should be note that the layout of the first patterned
layer 33 depicted in FIG. 3 is similar to that depicted in FIG. 2
That is to say, a mandrel patterns 22' consisting of straight line
patterns 26' and L-shaped patterns 28' and dummy mandrel patterns
24' are formed in the first patterned layer 33. Additionally, since
the mandrel patterns 22 and the dummy mandrel patterns 24 are
corrected in the corresponding OPC process, the straight line
patterns 24' and 26' and the L-shaped patterns 28' formed in the
first patterned layer 33 would be more close to perfect straight
line patterns and perfect L-shaped patterns that is originally
stored in the computer database.
[0032] After step S140 is completed, step S150 is then carried out.
In step S150, spacers 34 and 34' are formed on the sidewalls of the
first patterned layer 33 through deposition and etching process.
Through step S150, loop-shaped patterns (not shown) consisting of
loop-shaped feature patterns 36 and loop-shaped dummy patterns 38
are formed on the sidewalls of the first patterned layer 33. More
precisely, the loop-shaped feature patterns 36 and loop-shaped
dummy patterns 38 may respectively surround the mandrel patterns
22' and the dummy mandrel patterns 24'. Furthermore, each of the
loop-shaped feature patterns 36 and the loop-shaped dummy patterns
38 may be further divided into two portions, such as major portions
34a and 34'a and redundancy portions 34b and 34'b. The layout of
the major portions 34a may be used to define active regions of the
corresponding semiconductor devices and the redundancy portions 34b
and 34'b may be removed in the following etching process.
[0033] Still referring to FIG. 3, patterns within the first
patterned layer 33 may be distributed with suitable spacings in
order to meet the requirements of the minimum rule according to
corresponding photolithographic process. Preferably, the spacings
S1 among the mandrel patterns 22' are smaller than or equal to the
minimum design rule. Besides, the critical dimension of the mandrel
patterns 22' and the dummy mandrel patterns 24' are preferably
larger than that of the spacers 34 and 34'. In other words, the
widths W1 of the mandrel patterns 22' and the dummy mandrel
patterns 24' are preferably wider than the widths W2 of the spacers
34 and 34'.
[0034] After the formation of the spacers 34, all or portions of
the first patterned layer 33 may be optionally removed through
suitable etching processes. Then, please refer to FIG. 5 and FIG.
6. FIG. 5 is a schematic diagram showing a second mask with a
second layout pattern. FIG. 6 is a schematic diagram showing a
layout pattern on a substrate after transferring the second layout
pattern. In step S160, portions of the spacers 34 and 34' are
removed by transferring geometric patterns 42 shown in FIG. 5. For
example, after the structure shown in FIG. 3 and FIG. 4 is
fabricated, a patterned photoresist layer (not shown) may be formed
on the spacers 34 through at least a photolithographic process.
More precisely, the patterned photoresist layer may have a layout
pattern almost identical to the second layout pattern 200 formed on
the second mask, but not limited thereto. Besides, the second
layout pattern 200 may further include printable dummy geometric
patterns (not shown) or non-printable dummy geometric patterns (not
shown) which are separately disposed apart from the geometric
patterns 42. These dummy geometric patterns may be used to remove
portions of the mandrel patterns 22' or dummy mandrel patterns 24',
but not limited thereto. Preferably, the positions of the geometric
patterns 42 or the dummy geometric patterns may correspond to those
of the spacers 34 and 34'. In one case, the geometric patterns 42
in the patterned photoresist layer may expose the redundancy
portion 34b and 34'b of the spacers 34 and 34'. In another case,
the edges of the geometric patterns 42 in the patterned photoresist
layer may partially align with the edges of the mandrel patterns
22' and the dummy mandrel patterns 24'. In the subsequent etching
process, mere the redundancy portions 34b and 34'b of the spacers
34 and 34' are removed and the structure shown in FIG. 6 is
therefore obtained.
[0035] Please refer to FIG. 7. FIG. 7 is a schematic diagram
showing a third mask with a third layout pattern. As depicted in
FIG. 7, the third layout pattern 300 includes geometric patterns 62
consisting of pad patterns 64 and dummy pad patterns 66. In
addition, the shapes of the pad patterns 64 and the dummy pad
patterns 66 are rectangles, but not limited thereto; their shapes
may also be squares, circles or ellipses. Preferably, the
dimensions of the pad patterns 64 are larger than those of the
dummy pad patterns 66. More preferably, the dimensions of the dummy
pad patterns 66 are larger than those of the mandrel patterns 22,
the dummy mandrel patterns 24, and/or dummy geometric patterns.
According to this embodiment, all the dummy pad patterns 66 shown
in FIG. 7 are printable according to this embodiment. However, in
another case, some of the dummy pad patterns may be non-printable
so that they would not be transferred to a layer on or over the
substrate in the following process. Besides, the dummy pad patterns
66 are preferably designed without overlaying any pattern in the
previous masks, such as mandrel patterns and dummy mandrel
patterns. It should be noted that, since the third pattern layout
300 is also corrected by the OPC process, the pad patterns 64 and
the dummy pad patterns 66 formed on the third mask 60 cannot be
exactly the same as those later formed on the substrate and they
may have slightly widened line ends and slightly inwards and/or
outwards corners instead.
[0036] Please refer to FIG. 8 and FIG. 9. FIG. 8 is schematic
diagram showing a layout pattern on a substrate after transferring
a third layout pattern. FIG. 9 is schematic cross-sectional diagram
taken along a line B-B' in FIG. 8. As depicted in FIG. 8 and FIG.
9, in step S170, the third layout pattern 300 formed on the third
mask layer 60 is transferred to a layer, such as a photoresist
layer, over the substrate 30 so as to form a second patterned layer
68. Similarly, the layout of the second patterned layer 68 depicted
in FIG. 8 is similar to that depicted in FIG. 7. That is to say,
the geometric patterns 62' consisting of pad patterns 64' and dummy
pad patterns 66' are formed in the second patterned layer 68.
Besides, since the pad patterns 64 and dummy pad patterns 66 are
corrected in the corresponding OPC process, the pad patterns 64'
and dummy pad patterns 66' defined in the second patterned layer 68
would be more close to perfect pad patterns and dummy patterns
originally stored in the computer database. Still referring to FIG.
8 and FIG. 9, when the second patterned layer 68 is made of
photoresist, the pad patterns 64' may cover portions of the
loop-shaped patterns and especially cover portions of the major
portion 34a. According to this embodiment, the dummy pad patterns
66' may be uniformly distributed around a periphery of major
portion 34a of the loop-shaped feature patterns and the major
portion 34'a of the loop-shaped dummy patterns. That is to say, the
dummy pad patterns 66' do not cover or overlay any major portion
34a and 34'a.
[0037] It should be noted that patterns within the second patterned
layer 68 may be distributed with suitable spacings in order to meet
the requirements of the minimum rule according to corresponding
photolithographic process. Preferably, the spacings S2 among the
geometric patterns 62' are at least 5 times greater than the
minimum design rule. In addition, the second patterned layer 68
preferably has a critical dimension greater than that of the first
patterned layer 33 and the spacers 34 and more preferably larger
than 1 micrometer. That is to say, the widths W3 and W4 of the
second patterned layer 68 are wider than the widths W1 and W2 of
the first patterned layer 33 and the spacers 34. Furthermore, the
lengths L3 of the pad patterns 64' may be longer than the lengths
L4 of the dummy pad patterns 66'.
[0038] Please refer to FIG. 10. Finally, in step S180, at least a
suitable etching process, such as an anisotropic etching process,
may be carried out by using the major portions 34a and 34'a of the
spacers 34 and 34' and the second patterned layer 68 as etch mask.
In this way, the layout pattern consisting of the major portions
34a and 34'a and the second patterned layer 68 may be further
transferred to the target layer 31' and therefore form a patterned
layer 31' on the substrate 30. According to this embodiment, the
layout of the patterned layer 31' may correspond to a layout of
semiconductor devices, such as FinFET devices, but not limited
thereto.
[0039] In summary, the embodiments of the present invention provide
a method for forming a layout pattern. According to these
embodiments, the dummy patterns with different dimensions are
distributed over different individual photomasks and these dummy
patterns with different dimensions may be transferred to the target
layer concurrently. In this way, the fabrication process can be
therefore more effective and the corresponding process window is
therefore enhanced.
[0040] Those skilled in the art will readily observe that numerous
modifications and alterations of the device and method may be made
while retaining the teachings of the invention. Accordingly, the
above disclosure should be construed as limited only by the metes
and bounds of the appended claims.
* * * * *