U.S. patent application number 14/994166 was filed with the patent office on 2016-05-05 for magnetic memory devices.
This patent application is currently assigned to Shanghai Ciyu Information Technologies Co., Ltd.. The applicant listed for this patent is Shanghai Ciyu Information Technologies Co., Ltd.. Invention is credited to Yimin Guo.
Application Number | 20160126288 14/994166 |
Document ID | / |
Family ID | 51841357 |
Filed Date | 2016-05-05 |
United States Patent
Application |
20160126288 |
Kind Code |
A1 |
Guo; Yimin |
May 5, 2016 |
Magnetic Memory Devices
Abstract
A STT-MRAM comprises apparatus and a method of manufacturing a
plurality of magnetoresistive memory element having a dielectric
thermal buffer layer between a thin top electrode of the MTJ
element and a bit line, and a bit-line VIA electrically connecting
the top electrode and the bit line having a vertical distance away
from the location of the MTJ stack. In a laser thermal annealing, a
short wavelength of a laser has a shallow thermal penetration depth
and a high thermal resistance from the bit line to the MTJ stack
only causes a temperature rise of the MTJ stack being much smaller
than that of the bit line. As the temperature of the MTJ element
during the laser thermal annealing of bit line copper layer is
controlled under 300-degree C., possible damages on MTJ and
magnetic property can be avoided.
Inventors: |
Guo; Yimin; (San Jose,
CA) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Shanghai Ciyu Information Technologies Co., Ltd. |
Fremont |
CA |
US |
|
|
Assignee: |
Shanghai Ciyu Information
Technologies Co., Ltd.
Fremont
CA
|
Family ID: |
51841357 |
Appl. No.: |
14/994166 |
Filed: |
January 13, 2016 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
14269066 |
May 2, 2014 |
|
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14994166 |
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Current U.S.
Class: |
257/421 |
Current CPC
Class: |
H01L 43/12 20130101;
H01L 43/08 20130101; H01L 43/10 20130101; H01L 43/02 20130101; G11C
11/161 20130101; H01L 27/228 20130101; H01L 27/222 20130101 |
International
Class: |
H01L 27/22 20060101
H01L027/22; G11C 11/16 20060101 G11C011/16; H01L 43/10 20060101
H01L043/10; H01L 43/02 20060101 H01L043/02; H01L 43/08 20060101
H01L043/08 |
Claims
1. A spin-transfer torque magnetoresistive memory comprising a
control circuitry and at least one memory cell comprising: a bottom
electrode provided on a surface of a substrate connecting to a VIA
of a select transistor; a patterned MTJ stack consisting of a seed
layer provided on the top surface of the bottom electrode, an MTJ
multilayer provided on the top surface of the seed layer and a cap
layer provided on the top surface of the MTJ multilayer; a top
electrode provided on the surface of the MTJ stack; a dielectric
thermal barrier layer provided on the top surface of the top
electrode; a bit-line VIA provided on the surface of the top
electrode and surrounded by the dielectric thermal barrier layer
and having a vertical distance away from the MTJ stack; a bit line
provided on the top surface of the dielectric thermal barrier layer
and electrically connecting to the bit-line VIA.
2. The element of claim 1, wherein said insulating thermal barrier
layer is made of an oxide, or nitride, or oxynitride having a low
thermal conductivity.
3. The element of claim 1, wherein said insulating thermal barrier
layer is preferred to be made of an oxide, or nitride, selected
from the stoichiometric composition group of Al2O3, SiO2, Si3N4,
MgO.
4. The element of claim 1, wherein said insulating thermal barrier
layer has a thickness in a range from 50 nm to 500 nm.
5. The element of claim 1, wherein said bit line layer is made of a
copper or CuAl line having a seed layer such as TiN, TaN, etc. and
is encapsulated by a SiNx layer.
6. The element of claim 1, wherein said bit line layer is thermal
annealed by a pulsed short wavelength laser.
7. The element of claim 1, wherein said bit line layer has a
thickness in a range from 50 nm to 500 nm.
8. The element of claim 1, wherein said top electrode layer is made
by a multilayer of Ta/Ru/Ta.
9. The element of claim 1, wherein said top electrode layer has a
thickness in a range from 20 nm to 200 nm.
10. The element of claim 1, wherein said vertical distance between
said bit-line VIA and said MTJ stack is least 20 nm, preferred to
be more than 100 nm.
11. The element of claim 1, wherein said MTJ multilayer further
consisting of a recording layer, a tunneling barrier and a
reference layer
12. The element of claim 11, wherein said tunnel barrier layer is
made of a metal oxide or a metal nitride, a metal oxynitride,
preferred to be MgO, ZnO, MgZnO, MgN, MgON.
13. The element of claim 1, wherein said recording layer and said
reference layer are ferromagnetic layers.
Description
RELATED APPLICATIONS
[0001] This application claims the priority benefit of U.S.
Provisional Application No. 61,820,101 filed on May 6, 2013, which
is incorporated herein by reference. This application is a
divisional divisional application due to a restriction requirement
on application Ser. No. 14/269,066.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] This invention relates generally to a spin-transfer-torque
magnetic-random-access memory (MRAM) cell having a heat buffer
(barrier) layer for reducing undesirable heating of the magnetic
tunneling junction during pulsed laser heating annealing of upper
copper bit lines.
[0004] 2. Description of the Related Art
[0005] In recent years, magnetic random access memories
(hereinafter referred to as MRAMs) using the magnetoresistive
effect of ferromagnetic tunnel junctions (also called MTJs) have
been drawing increasing attention as the next-generation
solid-state nonvolatile memories that can also cope with high-speed
reading and writing. A ferromagnetic tunnel junction has a
three-layer stack structure formed by stacking a recording layer
having a changeable magnetization direction, an insulating tunnel
barrier layer, and a fixed layer that is located on the opposite
side from the recording layer and maintains a predetermined
magnetization direction. Corresponding to the parallel and
anti-parallel magnetic states between the recording layer
magnetization and the reference layer magnetization, the magnetic
memory element has low and high electrical resistance states,
respectively. Accordingly, a detection of the resistance allows a
magnetoresistive element to provide information stored in the
magnetic memory device.
[0006] There has been a known technique for achieving a high MR
ratio by forming a crystallization acceleration film that
accelerates crystallization and is in contact with an interfacial
magnetic film having an amorphous structure. As the crystallization
acceleration film is formed through a thermal annealing process or
a rapid thermal annealing process, crystallization is accelerated
from the tunnel barrier layer side, and the interfaces with the
tunnel barrier layer and the interfacial magnetic film are matched
to each other. Typically, the annealing temperature is preferred to
be between 250-degree C. and 350-degree C. By using this technique,
a high MR ratio can be achieved.
[0007] Typically, MRAM devices are classified by different write
methods. A traditional MRAM is a magnetic field-switched MRAM
utilizing electric line currents to generate magnetic fields and
switch the magnetization direction of the recording layer in a
magnetoresistive element at their cross-point location during the
programming write. A spin-transfer torque (or STT)-MRAM has a
different write method utilizing electrons' spin momentum transfer.
Specifically, the angular momentum of the spin-polarized electrons
is transmitted to the electrons in the magnetic material serving as
the magnetic recording layer. According to this method, the
magnetization direction of a recording layer is reversed by
applying a spin-polarized current to the magnetoresistive element.
As the volume of the magnetic layer forming the recording layer is
smaller, the injected spin-polarized current to write or switch can
be also smaller. In a so-called perpendicular STT-MRAM, both two
magnetization films in an MTJ stack have easy axis of magnetization
in a direction perpendicular to the film plane due to their strong
magnetic crystalline anisotropy and interface interaction induced
anisotropy, shape anisotropies are not used, and accordingly, the
device shape can be made smaller than that of an in-plane
magnetization type. Also, variance in the easy axis of
magnetization can be made smaller. Accordingly, both
miniaturization and lower currents can be expected to be achieved
while a thermal disturbance resistance is maintained. In another
word, perpendicular STT-MRAM having high speed, large capacities
and low-power-consumption operations can potentially replace the
conventional semiconductor memory used in electronic chips,
especially mobile chips for power saving and non-volatility.
[0008] Reading STT MRAM involves applying a voltage to the MTJ
stack to discover whether the MTJ element states at high resistance
or low. However, a relatively high voltage needs to be applied to
the MTJ to correctly determine whether its resistance is high or
low, and the current passed at this voltage leaves little
difference between the read-voltage and the write-voltage. Any
fluctuation in the electrical characteristics of individual MTJs at
advanced technology nodes could cause what was intended as a
read-current, to have the effect of a write-current, thus reversing
the direction of magnetization of the recording layer in MTJ.
[0009] The thermal stability of the magnetic orientation in a MRAM
cell is a critical parameter which has to be kept high enough for a
good data retention, and is typically characterized by the
so-called thermal factor which is proportional to the perpendicular
anisotropy as well as the volume of the recording layer cell
size.
[0010] Combining writing, reading and thermal stability factors, an
MRAM has to be well designed and manufactured with tight processing
variations. However, there are still thermal incompatibilities
between magnetic and semiconductor materials. The bottom CMOS
material annealing can be conducted before MTJ deposition, but the
upper bit line which is preferred to made of copper or CuAl is
fabricated after MTJ deposition and typically requires a high
temperature (400-degree C. or higher) annealing to achieve
enlargement of grain size, remove tension from the material and
reduce electromigration. This high temperature annealing process
would degrade MTJ magnetic properties.
[0011] A pulsed laser thermal annealing has much faster heating and
cooling rates and shallow thermal penetration depth which should
reduce direct heating to the lower magnetic materials. Since a bit
line still needs a much higher annealing temperature well above
400-degree C., a direct metal thermal conduction between the bit
line and the MTJ would lead a higher temperature of the MTJ element
above its thermal margin, yielding a damage of tunneling barrier or
magnetic materials.
[0012] Thus, it is desirable to provide STT-MRAM structures having
a heat barrier for reducing undesirable heating of the magnetic
tunneling junction during pulsed laser heating annealing of upper
copper bit lines.
BRIEF SUMMARY OF THE PRESENT INVENTION
[0013] The present invention comprises a magnetoresistive memory
cell having a heat barrier for reducing undesirable heating of the
magnetic tunneling junction during pulsed laser heating annealing
of upper copper bit lines.
[0014] An exemplary embodiment includes a spin-transfer-torque
magnetoresistive memory cell consisting of a bottom electrode
connecting to a VIA of a select transistor, an MTJ stack, a top
electrode, a bit line, an insulating thermal barrier layer between
the top electrode and the bit line, a connection VIA connecting the
top electrode and the bit line.
[0015] The bit line is typically made of a copper or CuAl line
having a seed layer such as TiN, TaN, etc. and is encapsulated by a
SiNx layer. The growth of an electro-plated copper layer is
polycrystalline. The size of the grains depends on the substrate
surface, the growth conditions as well as on the size of the graves
and vias. Electroplated Cu films demonstrate an intriguing
phenomenon known as "self-annealing"; the as-plated films are not
stable and their microstructure evolves even at room temperature.
However re-crystallization is not under control and not uniform in
this case and depends also on the width of the Cu lines. And more,
large different thermal expansion coefficients of dielectric and
copper can promote detachments between copper and dielectric
material. A narrow bit line electromigration is another major
concern for integrated circuitry whereby the moving electrons that
constitute electrical current collide with stationary atoms of the
interconnect and push these atoms in the direction of the electron
flow. In order to improve the properties of the copper layer, a Cu
thermal anneal is required. Microstructural, mechanical and
contamination results show that rapid thermal anneals at
400.degree. C. offer performances that are similar to longer
furnace anneals at the same temperature, whereas 250.degree. C.
anneals are insufficient and 300.degree. C. anneals are marginal. A
typical MTJ would be damaged or partially damaged by a conventional
uniform high temperature annealing of copper lines by long batch
furnace thermal treatments.
[0016] In a laser thermal annealing, a short wavelength of a laser
has a shallow thermal penetration depth which reduces direct
heating to the lower magnetic materials. In this invention, a
dielectric thermal buffer or barrier layer having a low thermal
conductivity is deposited between a thin top electrode of the MTJ
element and a bit line, while the VIA electrically connecting the
top electrode and the bit line has a vertical distance away from
the location of the MTJ element. Thus, a high thermal resistance
from the bit line to the MTJ element is achieved, and the
temperature rise of the MTJ element is much smaller than that of
the bit line during a pulsed laser thermal annealing. As the
temperature of the MTJ element during the laser thermal annealing
of bit line copper layer is controlled under 300-degree C., there
is no damage on MTJ and magnetic property.
[0017] Various embodiments will be described hereinafter with
reference to the companying drawings. The drawings are schematic or
conceptual, and the relationships between the thickness and width
of portions, the proportional coefficients of sizes among portions,
etc., are not necessarily the same as the actual values
thereof.
BRIEF DESCRIPTION OF THE DRAWINGS
[0018] FIG. 1 is a cross-section of one memory cell in a STT-MRAM
array having an insulating thermal barrier vertically separating an
MTJ element and a bit line in the first embodiment;
[0019] FIG. 2 is a cross-section of one memory cell in a STT-MRAM
array having an insulating thermal barrier vertically separating an
MTJ element and a bit line in the second embodiment.
DETAILED DESCRIPTION OF THE INVENTION
[0020] In general, according to each embodiment, there is provided
a magnetoresistive memory cell comprising: [0021] a bottom
electrode provided on a surface of a substrate connecting to a VIA
of a select transistor; [0022] a patterned MTJ stack consisting of
a seed layer provided on the top surface of the bottom electrode,
an MTJ multilayer provided on the top surface of the seed layer and
a cap layer provided on the top surface of the MTJ multilayer;
[0023] a top electrode provided on the surface of the MTJ stack;
[0024] a dielectric thermal barrier layer provided on the top
surface of the top electrode; [0025] a bit-line VIA provided on the
surface of the top electrode and surrounded by the dielectric
thermal barrier layer and having a vertical distance away from the
MTJ stack; [0026] a bit line provided on the top surface of the
dielectric thermal barrier layer and electrically connecting to the
bit-line VIA.
[0027] An exemplary embodiment includes a spin-transfer-torque
magnetoresistive memory cell including a bottom electrode
connecting to a VIA of a select transistor, a patterned MTJ stack
vertically overlaid on top of the VIA of the select transistor and
consisting of a seed layer, an MTJ multilayer and a cap layer, a
top electrode on the top surface of the MTJ stack having a thin
multilayer, an insulating thermal barrier layer deposited on the
top electrode, a bit line deposited on the insulating thermal
barrier layer and a bit-line VIA having vertical distance away from
the MTJ stack and connecting the bit line and the top
electrode.
[0028] Another exemplary embodiment includes a spin-transfer-torque
magnetoresistive memory cell including a bottom electrode
connecting to a VIA of a select transistor, a patterned MTJ stack
having a vertical distance away from the VIA of the select
transistor and consisting of a seed layer, an MTJ multilayer and a
cap layer, a top electrode on the top surface of the MTJ stack
having a thin multilayer, an insulating thermal barrier layer
deposited on the top electrode, a bit line deposited on the
insulating thermal barrier layer and a bit-line VIA having vertical
distance away from the MTJ stack and connecting the bit line and
the top electrode.
[0029] The following detailed descriptions are merely illustrative
in nature and are not intended to limit the embodiments of the
subject matter or the application and uses of such embodiments. Any
implementation described herein as exemplary is not necessarily to
be construed as preferred or advantageous over other
implementations. Furthermore, there is no intention to be bound by
any expressed or implied theory presented in the preceding
technical field, background, brief summary, or the following
detailed description.
[0030] FIG. 1 is a cross-sectional view of a magnetoresistive
memory cell in a perpendicular STT-MRAM array. The magnetoresistive
memory cell 10 is configured by a bit line 16, a bit-line VIA 15, a
top electrode 14, an insulating dielectric thermal barrier layer
20, an MTJ stack 19, a bottom electrode 18, a VIA of a select
transistor 17, a ILD layer 13, and a select transistor comprising
an interconnect layer 12, a source contact 11, drain contact 21,
source region 22, a gate insulating film 23, a gate electrode 24
and a drain region 25.
[0031] The bit line 16 typically made of a copper or CuAl line
having a seed layer such as TiN, TaN, etc. and is encapsulated by a
SiNx layer. In a laser thermal annealing, a short wavelength of a
laser has a shallow thermal penetration depth which should reduce
direct heating to the lower magnetic materials. And further, a
dielectric thermal barrier layer 20 having a low thermal
conductivity is deposited between a thin top electrode 14 of the
MTJ element and a bit line 16, while a bit-line VIA electrically
connecting the top electrode 14 and the bit line 16 has a vertical
distance away from the location of the MTJ stack 19. The top
electrode 14 is typically made of a thin multilayer Ta/Ru/Ta. Thus,
a high thermal resistance from the bit line 16 to the MTJ stack 19
is achieved, and a low thermal resistance from the MTJ stack to the
VIA of the select transistor. During a pulsed laser thermal
annealing on the bit line, the temperature rise of the MTJ element
is much smaller than that of the bit line. As the temperature of
the MTJ element during the laser thermal annealing of bit line
copper layer is readily controlled under 300-degree C. while the
thermal annealing temperature of the bit line reaches more than
400-degree C., there is no damage on MTJ and magnetic property.
[0032] The insulating thermal barrier layer 20 is preferred to be
made of an oxide, or nitride, or oxynitride selected from the
stoichiometric composition group of Al2O3, SiO2, Si3N4, MgO, which
is made from a balanced chemical reaction.
[0033] FIG. 2 is a cross-sectional view of a magnetoresistive
memory cell in a perpendicular STT-MRAM array in another
embodiment. The magnetoresistive memory cell 10 is configured by a
bit line 17, a bit-line VIA 20, a top electrode 15, an insulating
dielectric thermal barrier layer 16, an MTJ stack 14, a bottom
electrode 19, a VIA of a select transistor 18, a ILD layer 13, and
a select transistor comprising an interconnect layer 12, a source
contact 11, drain contact 21, source region 22, a gate insulating
film 23, a gate electrode 24 and a drain region 25.
[0034] The bit line 17 typically made of a copper or CuAl line
having a seed layer such as TiN, TaN, etc. and is encapsulated by a
SiNx layer. In a laser thermal annealing, a short wavelength of a
laser has a shallow thermal penetration depth which should reduce
direct heating to the lower magnetic materials. And further, a
dielectric thermal barrier layer 16 having a low thermal
conductivity is deposited between a thin top electrode 19 of the
MTJ element and a bit line 17, while a bit-line VIA 20 electrically
connecting the top electrode 19 and the bit line 17 has a vertical
distance away from the location of the MTJ stack 14. The top
electrode 19 is typically made of a thin multilayer Ta/Ru/Ta. Thus,
a high thermal resistance from the bit line 17 to the MTJ stack 14
is achieved. During a pulsed laser thermal annealing on the bit
line, the temperature rise of the MTJ element is much smaller than
that of the bit line. As the temperature of the MTJ element during
the laser thermal annealing of bit line copper layer is readily
controlled under 300-degree C. while the thermal annealing
temperature of the bit line reaches more than 400-degree C., there
is no damage on MTJ and magnetic property.
[0035] While certain embodiments have been described above, these
embodiments have been presented by way of example only, and are not
intended to limit the scope of the inventions. Indeed, the novel
embodiments described herein may be embodied in a variety of other
forms; furthermore, various omissions, substitutions and changes in
the form of the embodiments described herein may be made without
departing from the spirit of the inventions. The accompanying
claims and their equivalents are intended to cover such forms or
modifications as would fall within the scope and spirit of the
inventions.
* * * * *