U.S. patent application number 14/985189 was filed with the patent office on 2016-04-21 for method for reading a third-dimensional embedded re-writeable non-volatile memory and registers.
This patent application is currently assigned to III Holdings 1, LLC. The applicant listed for this patent is III Holdings 1, LLC. Invention is credited to Robert Norman.
Application Number | 20160111157 14/985189 |
Document ID | / |
Family ID | 40931544 |
Filed Date | 2016-04-21 |
United States Patent
Application |
20160111157 |
Kind Code |
A1 |
Norman; Robert |
April 21, 2016 |
METHOD FOR READING A THIRD-DIMENSIONAL EMBEDDED RE-WRITEABLE
NON-VOLATILE MEMORY AND REGISTERS
Abstract
A non-volatile register includes register logic connected with
first and second ends of a memory element. The register logic is
positioned below the memory element. The memory element may be a
two-terminal memory element configured to store data as a plurality
of conductivity profiles that can be non-destructively determined
by applying a read voltage across the two terminals. New data can
be written to the two-terminal memory element by applying a write
voltage of a predetermined magnitude and/or polarity across the two
terminals. The two-terminal memory element retains stored data in
the absence of power. A reference element including a structure
that is identical or substantially identical to the two-terminal
memory element may be used to generate a reference signal for
comparisons during read operations.
Inventors: |
Norman; Robert; (Pendleton,
OR) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
III Holdings 1, LLC |
Wilmington |
DE |
US |
|
|
Assignee: |
III Holdings 1, LLC
Wilmington
DE
|
Family ID: |
40931544 |
Appl. No.: |
14/985189 |
Filed: |
December 30, 2015 |
Related U.S. Patent Documents
|
|
|
|
|
|
Application
Number |
Filing Date |
Patent Number |
|
|
14730173 |
Jun 3, 2015 |
|
|
|
14985189 |
|
|
|
|
13134713 |
Jun 14, 2011 |
9064548 |
|
|
14730173 |
|
|
|
|
12927795 |
Nov 23, 2010 |
7961529 |
|
|
13134713 |
|
|
|
|
12800289 |
May 11, 2010 |
7839702 |
|
|
12927795 |
|
|
|
|
12012641 |
Feb 5, 2008 |
7715244 |
|
|
12800289 |
|
|
|
|
Current U.S.
Class: |
365/148 |
Current CPC
Class: |
G11C 13/004 20130101;
G11C 2207/063 20130101; G11C 5/04 20130101; G11C 2213/13 20130101;
G11C 13/0069 20130101; G11C 7/062 20130101; G11C 2213/71 20130101;
G11C 13/02 20130101; G11C 2013/009 20130101; G11C 2013/0054
20130101 |
International
Class: |
G11C 13/00 20060101
G11C013/00 |
Claims
1. A method, comprising: receiving a datum; and applying a voltage
across a memory element to write the datum to the memory element;
wherein the memory element is configured to store the datum as one
of a plurality of conductivity profiles and to retain the datum in
an absence of electrical power; wherein the applying the voltage is
operative to change a resistive state of the memory element from
one of the plurality of conductivity profiles to another one of the
plurality of conductivity profiles; and wherein the voltage has a
polarity operative to change the resistive state of the memory
element.
2. The method of claim 1, further comprising: switching the
polarity of the voltage based on the datum.
3. The method of claim 1, wherein the memory element includes: a
conductive oxide including mobile oxygen ions; and an electrolytic
tunnel barrier in contact with the conductive oxide; wherein the
conductive oxide and the electrolytic tunnel barrier are
electrically serially coupled with memory element.
4. The method of claim 1, wherein the memory element is integrally
fabricated directly above a silicon substrate; wherein the silicon
substrate includes circuitry fabricated on the silicon substrate;
and wherein the circuitry includes register logic electrically
coupled with the memory element.
5. The method of claim 4, wherein the memory element is embedded in
a memory plane that is integrally fabricated directly above and is
in direct contact with the silicon substrate.
6. The method of claim 5, wherein the memory plane includes a
two-terminal cross-point array having a plurality of conductive
array lines, the memory element being positioned between a
cross-point of a unique pair of the conductive array lines; wherein
first and second terminals of the memory element are electrically
coupled with the unique pair of the conductive array lines; wherein
the memory element is directly electrically in series with the
unique pair of conductive array lines; and wherein the unique pair
of conductive array lines electrically couples the memory element
with the register logic.
7. A system, comprising: a receiver circuit to receive a datum; and
a voltage circuit configured to write the datum to a memory element
configured to store the datum as one of a plurality of conductivity
profiles and to retain the datum in the absence of electrical
power; wherein the memory element comprises: a conductive oxide
including mobile oxygen ions; and an electrolytic tunnel barrier
electrically in series with the conductive oxide.
8. The system of claim 7, wherein the electrolytic tunnel barrier
comprises a thickness that is less than approximately 50
angstroms.
9. The system of claim 7, wherein: the memory element is integrally
fabricated directly above a silicon substrate; the silicon
substrate comprises circuitry fabricated on the silicon substrate;
and the circuitry comprises a register logic electrically coupled
with the memory element.
10. The system of claim 7, wherein the voltage circuit is further
configured to write the datum to the memory element by applying a
voltage.
11. The system of claim 10, wherein the voltage circuit is further
configured to switch a polarity of the voltage based on the
datum.
12. A method, comprising: receiving a datum; and applying a voltage
across a memory element to write the datum to the memory element;
wherein the memory element is configured to store the datum as one
of a plurality of conductivity profiles and to retain the datum in
an absence of electrical power; and wherein the memory element
comprises: a conductive oxide including mobile oxygen ions; and an
electrolytic tunnel barrier electrically in series with the
conductive oxide.
13. The method of claim 12, further comprising: switching a
polarity of the voltage based on the datum.
14. The method of claim 12, further comprising: serially coupling
the conductive oxide and the electrolytic tunnel barrier to the
memory element.
15. The method of claim 12, further comprising: fabricating the
memory element directly above a silicon substrate; and fabricating
circuitry register logic electrically coupled with the memory
element on the silicon substrate.
16. The method of claim 15, further comprising: embedding the
memory element in a memory plane that is integrally fabricated
directly above and is in direct contact with the silicon
substrate.
17. The method of claim 16, wherein the memory plane includes a
two-terminal cross-point array having a plurality of conductive
array lines, the memory element being positioned between a
cross-point of a unique pair of the conductive array lines; wherein
first and second terminals of the memory element are electrically
coupled with the unique pair of the conductive array lines; wherein
the memory element is directly electrically in series with the
unique pair of conductive array lines; and wherein the unique pair
of conductive array lines electrically couples the memory element
with the register logic.
Description
RELATED APPLICATIONS
[0001] This application is a division of and claims priority to
pending U.S. patent application Ser. No. 14/730,173, which is a
division of and claims priority to U.S. patent application Ser. No.
13/134,713, filed Jun. 14, 2011, now issued as U.S. Pat. No.
9,064,548, which is a continuation of and claims priority to U.S.
patent application Ser. No. 12/927,795 filed, Nov. 23, 2010, now
issued as U.S. Pat. No. 7,961,529, which is a continuation of and
claims priority to U.S. patent application Ser. No. 12/800,289,
filed May 11, 2010, now issued as U.S. Pat. No. 7,839,702, which is
a continuation of and claims priority to U.S. patent application
Ser. No. 12/012,641, filed Feb. 5, 2008, now issued as U.S. Pat.
No. 7,715,244, all of which are incorporated by reference herein in
their entirety.
FIELD OF THE INVENTION
[0002] The present invention relates to semiconductors and, more
particularly, to a non-volatile register.
BACKGROUND
[0003] A register can be a portion of a hardware used as a storage
location. An example of a register can include a portion of a
central processor unit used for storage of information. Another
example of a register can include a portion of a video memory used
for storage by video graphic cards. Information stored in a
register can include configuration information, information
associated with the initialization of the hardware, and other
information.
[0004] Flash memory may be configured as a register. However, flash
memory requires high voltage charge pumps that require specialized
designs. Furthermore, flash memory requires complex programming
algorithms that result in a large amount of logic. Electronically
Erasable Programmable Read-Only Memory (EEPROM) also may be
configured as a register. Still, the EEPROM requires a charge pump
and the process of configuring the EEPROM as a register is
complicated and is subject to a high failure rate. As a result,
there is a need for continuing efforts to improve non-volatile
registers.
BRIEF DESCRIPTION OF THE DRAWINGS
[0005] The present invention will be readily understood by the
following detailed description in conjunction with the accompanying
drawings, and like reference numerals designate like structural
elements. Although the Drawings depict various examples of the
invention, the invention is not limited by the depicted examples.
Furthermore, the depictions are not necessarily to scale:
[0006] FIG. 1 is a simplified block diagram of a non-volatile
register, in accordance with an embodiment;
[0007] FIG. 2 is a diagram of a cross-section of a non-volatile
register that is vertically configured, in accordance with an
embodiment;
[0008] FIG. 3 is a flowchart diagram of a high level logic overview
for writing data to a non-volatile register, in accordance with an
embodiment;
[0009] FIG. 4 is a flowchart diagram of a high level logic overview
for reading data from a non-volatile register, in accordance with
an embodiment;
[0010] FIG. 5 is a circuit diagram of a non-volatile register, in
accordance with an embodiment; and
[0011] FIG. 6 is a circuit diagram of a non-volatile register, in
accordance with another embodiment.
DETAILED DESCRIPTION
[0012] A detailed description of one or more embodiments is
provided below along with accompanying figures. The detailed
description is provided in connection with such embodiments, but is
not limited to any particular embodiment. The scope is limited only
by the claims and numerous alternatives, modifications, and
equivalents are encompassed. Numerous specific details are set
forth in the following description in order to provide a thorough
understanding. These details are provided for the purpose of
example and the described embodiments may be implemented according
to the claims without some or all of these specific details. For
the purpose of clarity, technical material that is known in the
technical fields related to the embodiments has not been described
in detail to avoid unnecessarily obscuring the description.
[0013] The embodiments described herein non-volatile registers and
methods for accessing the non-volatile registers. The non-volatile
register includes one or more memory elements and a register logic.
In an embodiment, the memory element is disposed above the register
logic. As will be explained in more detail below, register logic
may include circuitries, such as comparator and switches, to access
the memory element.
[0014] FIG. 1 is a simplified block diagram of a non-volatile
register 106, in accordance with an embodiment. Non-volatile
register 106 may be a third dimension memory. A third dimension
memory, which is connected with the register logic 102 and may be
disposed above the register logic 102, may include one or more
memory elements that are vertically configured along multiple
memory planes 150. Register logic 102 may include a variety of
logic and/or circuitry that is associated with the access of the
third dimension memory. For example, as explained in more detail
below, register logic 102 may include a comparator for reading data
from the third dimension memory and further include switches for
switching the polarity of voltages in a write operation. Memory
planes 150 can be implemented to emulate various types of memory
technologies that permit different physical and logical
arrangements (e.g., vertically stacked). A memory is "third
dimension memory" when the memory is fabricated above other
circuitry components, the components usually including a silicon
substrate, polysilicon layers, and metallization layers. By using
non-volatile third dimension memory, non-volatile memory registers
(and latches) may be vertically-configured to reduce die size and
not sacrifice overall chip functionality.
[0015] A third dimension memory can include one or more
two-terminal memory elements where, as shown in the embodiment of
FIG. 1, the memory elements in the form of memory planes 150 may be
stacked on top of or disposed above register logic 102. U.S. patent
application Ser. No. 11/095,026, filed Mar. 30, 2005, U.S.
Published Application No. 2006/0171200, and titled "Memory Using
Mixed Valence Conductive Oxides," hereby incorporated by reference
in its entirety and for all purposes, describes two-terminal memory
elements that can be arranged in a cross-point array. The
application describes a two-terminal memory element that changes
conductivity when exposed to an appropriate voltage drop across the
two terminals. The memory element includes an electrolytic tunnel
barrier and a mixed valence conductive oxide. The voltage drop
across the electrolytic tunnel barrier causes an electrical field
within the mixed valence conductive oxide that is strong enough to
move oxygen ions out of the mixed valence conductive oxides and
into the electrolytic tunnel barrier. Oxygen depletion causes the
mixed valence conductive oxide to change its valence, which causes
a change in conductivity. Both the electrolytic tunnel barrier and
the mixed valence conductive oxide do not need to operate in a
silicon substrate, and, therefore, can be fabricated above
circuitry being used for other purposes (such as selection
circuitry).
[0016] Both the electrolytic tunnel barrier and the mixed valence
conductive oxide do not need to operate in a silicon substrate,
and, therefore, can be fabricated above circuitry being used for
other purposes (such as register logic 102). The two-terminal
memory elements can be arranged in a cross-point array such that
one terminal is electrically coupled with an x-direction line and
the other terminal is electrically coupled with a y-direction line.
A stacked cross-point array consists of multiple cross-point arrays
vertically stacked upon one another, sometimes sharing x-direction
and y-direction lines between layers, and sometimes having isolated
lines. When a first write voltage V.sub.W1 is applied across the
memory element, (typically by applying 1/2V.sub.W1 to the
x-direction line and 1/2-V.sub.W1 to the y-direction line) it
switches to a low resistive state. When a second write voltage
V.sub.W2 is applied across the memory element, (typically by
applying 1/2V.sub.W2 to the x-direction line and 1/2-V.sub.W2 to
the y-direction line) it switches to a high resistive state.
Typically, memory elements using electrolytic tunnel barriers and
mixed valence conductive oxides require V.sub.W1 to be opposite in
polarity from V.sub.W2.
[0017] FIG. 2 is a diagram of a cross-section of a non-volatile
register that is vertically configured, in accordance with an
embodiment. As shown in FIG. 2, memory plane 150 is disposed above
register logic 102. In turn, register logic 102 is disposed above
substrate 252. Memory plane 150 includes one more memory elements,
such as memory element 412. Memory element 412 is electrically
connected with register logic 102 by way of an interconnect
structure, such as one or more vertically configured vias 410, for
example. As explained in more detail below, register logic 102 may
include a variety of logic and/or circuitry that is associated with
the access of memory element 412.
[0018] FIG. 3 is a flowchart diagram 300 depicting a high level
logic overview for writing data to a non-volatile register, in
accordance with an embodiment. At a stage 302, a register logic
receives a datum or a plurality of data to be written to the
non-volatile register. The non-volatile register is comprised of
one or more memory elements. As discussed above, the memory element
may be configured to store the datum based on the resistive state
of the memory element. To write the datum in the memory element, a
write voltage is applied across the memory element at a stage 304
to change or switch the memory element to a high or low resistive
state. The high or low resistive state may correspond to a value of
one or zero, which can correspond to the value of the datum.
[0019] The resistive state of the memory element can be changed
with the application of one or more write voltages with a voltage
potential. In an embodiment, the resistive state of the memory
element can depend on the polarity of the applied write voltages.
In other words, write voltages with different polarities can be
applied across a memory element to create the voltage potential.
For example, a positive polarity may switch the memory to a high
resistive state. Vice versa, a negative polarity may switch the
memory to a low resistive state. The polarity of the write voltage
therefore may depend on or is based on the value of the datum.
Accordingly, the polarity of the applied write voltage can be
switched based on the received datum. For example, if the datum is
a value of one, then the polarity of the write voltage may be
switched to a positive polarity. On the other hand, for example, if
the datum is a value of zero, then the polarity of the write
voltage may be switched to a negative voltage. In another
embodiment, the applied write voltages can have a single polarity.
Here, the applied write voltages can be either positive or
negative. As will be explained in more detail below, the voltage
potential associated with the write voltages is created by the
difference between the single polarity write voltages.
[0020] FIG. 4 is a flowchart diagram 400 depicting a high level
logic overview for reading data from a non-volatile register, in
accordance with an embodiment. During a read operation, to read a
datum or data stored in one or more memory elements, a read voltage
is applied across the memory element at a stage 402. With the read
voltage applied, the voltage associated with the resistance of the
memory element is read at a stage 404. The voltage associated with
the resistance of the memory element is then compared with a
reference voltage at a stage 406. The comparison defines a
comparison output that defines or corresponds to the value of the
datum stored in the memory element. As explained in more detail
below, in an embodiment, the comparison may include sensing a
difference between the voltage associated with the resistance of
the memory element and the reference voltage.
[0021] It should be appreciated that, in another embodiment, the
comparison may be based on the current instead of the voltage.
Here, during a read operation, a read voltage is applied across the
memory element. With the read voltage applied, the current
associated with the resistance of the memory element is read and
compared to a reference current. As explained in more detail below,
in an embodiment, the comparison may include sensing a difference
between the current associated with the resistance of the memory
element and a reference current.
[0022] FIG. 5 is a circuit diagram of a non-volatile register, in
accordance with an embodiment. Non-volatile register 502 includes
memory element 412 and register logic 536. In an embodiment,
register logic 536 is configured to be disposed below memory
element 412. Register logic 536 includes switches 504 and 506,
resistor 508, comparator 514, latch 526, and operational amplifier
532. In an embodiment, comparator 514 may be an operational
amplifier. As shown in FIG. 5, memory element 412 has two ends that
are connected with register logic 536. One end of memory element
412 is connected with switch 504 by way of via 410. The other end
of memory element 412 is connected with switch 506, an end of
resistor 508, and an input of comparator 514 by way of via 410.
Switch 504 is connected with switch 506, and switch 506 also is
connected with a ground 541. Another end of resistor 508 also is
connected with the ground 541. The other input of comparator 514 is
connected with a biased reference, such as voltage reference 534.
The output of comparator 514 is connected with latch 526 and the
latch is connected with operational amplifier 532.
[0023] In a write operation, switches 504 and 506 are enabled by
write enable signal 516 such as to receive datum 518. To write data
in memory element 412, write voltages 522 and 524 are applied
across memory element 412. Examples of write voltages 522 and 524
that may be applied across memory element 412 include .+-.3 volts,
.+-.7 volts, and other write voltages. In an embodiment, to create
a voltage potential, a positive write voltage and a negative write
voltage may be applied across memory element 412. For example, a
positive voltage may be applied to switch 504 and a negative
voltage may be applied to switch 506. Write voltages 522 and 524
have polarities (positive or negative) that are based on datum 518.
Switches 504 and 506 are configured to switch the polarities of the
write voltages based on datum 518. For example, if the datum 518 is
a value of zero, then switch 504 may switch the polarity of write
voltage 522 to a negative polarity. At the same time, switch 506
may switch the polarity of write voltage 524 to a positive
polarity. On the other hand, for example, if the datum 518 is a
value of one, then switch 504 may switch the polarity of write
voltage 522 to a positive polarity. At the same time, switch 506
may switch the polarity of write voltage 524 to a negative
polarity.
[0024] In another embodiment, the applied write voltages 522 and
524 can have a single polarity. Here, to create a voltage
potential, the polarities of write voltages 522 and 524 may be all
positive or negative. The voltage potential associated with the
write voltages 522 and 524 is created by the difference between the
single polarity write voltages. For example, a potential voltage
difference of +6 volts can be created by applying a +1 write
voltage and a +7 write voltage across memory element 412 by way of
switches 504 and 506, respectively. In another example, a potential
voltage difference of -6 volts can be created by applying a write
voltage potential of -1 volts and a write voltage potential of -7
volts across memory element 412 by way of switches 504 and 506,
respectively. After the write operation is complete, write voltages
522 and 524 or the write voltage difference can be reduced to zero
to minimize the current flow.
[0025] In a read operation, switches 504 and 506 are enabled by
read enable signal 520 and, to apply read voltage 538 across memory
element 412, the read voltage 538 is supplied to switch 504.
Comparator 514 includes two inputs that are connected with an end
of memory element 412 and switch 406. One input of comparator 514
receives a voltage associated with a resistance of memory element
412. Such voltage is generated by the application of the read
voltage 538. The other input of comparator 514 receives reference
voltage 534 from, for example, a reference element configured to
provide a specific voltage (e.g., a reference voltage).
[0026] Comparator 514 (e.g., operational amplifier) is configured
to amplify and sense a voltage difference between the voltage
associated with a resistance of memory element 412 and reference
voltage 534. Depending on the relationship between voltage
associated with resistance of memory element 412 and reference
voltage 534, comparator 514 outputs a high or low voltage. For
example, voltage associated with resistance of memory element 412
that is higher than reference voltage 534 can drive the voltage
output (i.e., a comparison output) to a high. On the other hand,
voltage associated with resistance of memory element 412 that is
lower than reference voltage 534 can drive the voltage output to a
low. Conversely, voltage associated with the resistance of memory
element 412 that is higher than reference voltage 534 can drive the
voltage output to a low, while the voltage associated with the
resistance of memory element 412 that is lower than the reference
voltage 534 can drive the voltage output to a high. The high or low
voltage output corresponds to the value of the datum stored in
memory element 412.
[0027] Still referring to FIG. 5, the comparison output from
comparator 514 may be sampled or stored in latch 526. The
comparison output from comparator 514 may be synchronized with
enable signal 528 or a clock signal. With output enable signal 530
supplied to operational amplifier 532, the operational amplifier
532 provides a three state output.
[0028] FIG. 6 is a circuit diagram of a non-volatile register, in
accordance with another embodiment. It should be appreciated that
in another embodiment, the register logic of FIG. 5 may be based on
a current mirror that is connected with a register. As shown in
FIG. 6, non-volatile register 602 includes memory element 412 and
register logic 610. Register logic 610 includes switches 604 and
606, current mirror 611, register 608, and operational amplifier
632. Memory element 412 has two ends that are connected with
register logic 610. One end of memory element 412 is connected with
switch 604 by way of via 410. The other end of memory element 412
is connected with switch 606 and an input of current mirror 611 by
way of via 410. Switch 604 is connected with switch 606, and switch
606 also is connected with a ground 641. The other input of current
mirror 611 is connected with a biased reference, such as reference
current 615. The output of current mirror 611 is connected with
register 608 and the register 608 is connected with operational
amplifier 632.
[0029] In a read operation, switches 604 and 606 are enabled by
read enable signal 620 and, to apply read voltage 638 across memory
element 412, the read voltage 638 is supplied to switch 604.
Current mirror 611 includes two inputs that are connected with an
end of memory element 412 and switch 606. One input of current
mirror 611 receives a current associated with a resistance of
memory element 412. The current is generated by the application of
read voltage 638. The other input of current mirror 611 receives
reference current 615 from, for example, a reference element (not
shown) configured to generate a specified signal (e.g., a reference
current or reference voltage). The reference element may have a
structure that is identical to or substantially identical to that
of the memory element 412. Moreover, the reference element may be a
two-terminal memory element like the memory element 412. The
reference element may have a resistance that is between the high
and low resistance values of the memory element 412 that represent
the datum stored in the memory element 412. For example, in the
memory element 412, a high resistance of 1 M.OMEGA. may represent a
logic "1" and a low resistance of 10 k.OMEGA. may represent a logic
"0", or vice-versa. Therefore, the reference element may have
resistance value that is somewhere between 1 M.OMEGA. and 10
k.OMEGA., such as approximately 500 k.OMEGA., for example. The
reference element may be fabricated in the memory plane 150 of FIG.
2 and positioned above the register logic 102. The reference
element may be used to generate the reference voltage 534 described
above in FIG. 5. Voltages that are identical to or approximately
equal to the voltages applied across the memory element 412 may be
applied across the reference element to generate the reference
signal, that is, the reference current in FIG. 6 or the reference
voltage in FIG. 5.
[0030] Current mirror 611 is configured to amplify and sense a
current difference between current associated with a resistance of
memory element 412 and reference current 615. Depending on the
relationship between reference current 615 and current associated
with a resistance of memory element 412 (e.g., a read current),
current mirror 611 outputs a high current or a low current. For
example, current associated with a resistance of memory element 412
that is higher than reference current 615 can drive the current
output to a high. However, if current associated with a resistance
of memory element 412 is lower than reference current 615, then
current mirror 611 can drive the current output to a low.
Conversely, current associated with a resistance of memory element
412 that is higher than reference current 615 can drive the current
output to a low, while the current associated with the resistance
of the memory element 412 that is lower than the reference current
615 can drive the current output to a high.
[0031] The comparison output from current mirror 611 may be stored
in a second register 698. The comparison output could be
synchronized with enable signal 628 or a clock signal. With output
enable signal 630 supplied to operational amplifier 632, the
operational amplifier 632 provides a three state output. As was
described above, the reference current 615 may be generated by the
reference element.
[0032] Although the foregoing embodiments have been described in
some detail for purposes of clarity of understanding, the
embodiments are not limited to the details provided. There are many
alternative ways of implementing the embodiments. Accordingly, the
disclosed embodiments are to be considered as illustrative and not
restrictive, and the embodiments are not to be limited to the
details given herein, but may be modified within the scope and
equivalents of the appended claims. In the claims, elements and/or
operations do not imply any particular order of operation, unless
explicitly stated in the claims.
* * * * *