U.S. patent application number 14/922512 was filed with the patent office on 2016-03-31 for integrated circuit inductors.
The applicant listed for this patent is NXP B.V.. Invention is credited to Alexe Nazarian.
Application Number | 20160092625 14/922512 |
Document ID | / |
Family ID | 44630389 |
Filed Date | 2016-03-31 |
United States Patent
Application |
20160092625 |
Kind Code |
A1 |
Nazarian; Alexe |
March 31, 2016 |
INTEGRATED CIRCUIT INDUCTORS
Abstract
An integrated circuit inductor design is provided in which the
path crossings are designed such that the voltage differences
between the adjacent paths in the loops are (in total)
minimised.
Inventors: |
Nazarian; Alexe; (Eindhoven,
NL) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
NXP B.V. |
Eindhoven |
|
NL |
|
|
Family ID: |
44630389 |
Appl. No.: |
14/922512 |
Filed: |
October 26, 2015 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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13991616 |
Jun 4, 2013 |
9196409 |
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PCT/IB2011/054389 |
Oct 5, 2011 |
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14922512 |
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Current U.S.
Class: |
716/119 |
Current CPC
Class: |
H01F 2017/0073 20130101;
G06F 30/392 20200101; Y10T 29/49004 20150115; H01F 17/0013
20130101; H01F 27/2804 20130101; H01F 27/34 20130101; H01F 41/041
20130101; H01F 5/003 20130101; H01F 17/0006 20130101 |
International
Class: |
G06F 17/50 20060101
G06F017/50 |
Foreign Application Data
Date |
Code |
Application Number |
Dec 6, 2010 |
EP |
10193825.6 |
Claims
1-12. (canceled)
13. A method of designing the layout of an inductor comprising a
conducting track arranged in loops, each loop comprising at least
two concentric paths, wherein the track length comprises tap
regions at the ends of the tracks and a central track region which
comprises the concentric paths of the loops, wherein the central
track region comprises a sequence of track sections, each
comprising a loop half turn, and crossings between tracks sections,
with the crossings spaced along the central track region by one or
two track sections, wherein the method comprises defining a
parameter p: p=the sum of squares of normalised differences in
track section sequence number for all adjacent pairs of track
sections in each loop; and selecting the path crossings at
locations such that the parameter p is the minimum possible value
of p.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is a divisional of co-pending U.S. patent
application 13/991616, filed on Jun. 4, 2013.
[0002] This invention relates to integrated circuit inductors
formed using a conductive track.
[0003] Integrated circuit inductors are essential to realize the
voltage-controlled oscillators needed in many fully integrated
transceiver chips serving a multitude of wireless communication
protocols. These are being provided to the market today. The
required inductance value is typically a few nH, and should be
adjustable to the application, whereas the quality factor should be
as high as possible. An additional benefit of an integrated circuit
inductor is a low net magnetic field, resulting in a lower magnetic
coupling to other inductors.
[0004] It is well known to form inductors using multiple loops, and
with multiple paths per loop. The conductive track is preferably
provided on two levels with cross overs between paths of the track,
the paths changing between the two levels at some of all of the
cross overs.
[0005] The invention relates particularly to figure of eight
layouts (i.e. having two loops) or clover-shaped layouts (i.e.
having four loops). Substantially symmetrical inductors, with
figure of eight or clover shaped structures, are well known. The
symmetrical design enables the inductor to be used in common and
differential mode.
[0006] Many known designs attempt to reduce undesired magnetic
field effects. For example (as one of many examples), WO2005/096328
A1 describes a method and system for reducing mutual
electromagnetic coupling between VCO resonators and for
implementing the same on a single semiconductor chip. The method
and system involve using inductors that are substantially
symmetrical about their horizontal and/or their vertical axes and
providing current to the inductors in a way so that the resulting
magnetic field components tend to cancel each other by virtue of
the symmetry. In addition, two such inductors may be placed near
each other and oriented in a way so that the induced current in the
second inductor due to the magnetic field originating from first
inductor is significantly reduced. The inductors may be of various
forms.
[0007] Known designs which provide a lower magnetic coupling can
result in a smaller quality factor of the inductor. One of the
reasons for a reduced quality factor is an increased number of
crossing points.
[0008] Each crossing point gives an additional contribution to the
resistance of an inductor. In order to make a crossing point, at
least two conducting layers are used. Through the length of the
inductor (excluding the crossing points), all of the loop-shaped
conducting layers are preferably connected in parallel using
vias.
[0009] This reduces the sheet resistance of the conducting
material. If two or more resistive materials are connected in
parallel then the total resistance of the construction is smaller
than the resistance of each parallel-connected component. However,
in order to make a crossing point between two turns, each turn must
use only one layer. This leads to an increase of sheet resistance
for the parts of an inductor where such crossings are implemented.
As a result, the total resistance of the inductor increases.
[0010] Each crossing point contributes also to the capacitance
between windings or coils due to potential difference between the
different paths at the crossing point.
[0011] The influence of the crossing points is known to be an area
of interest in obtaining desired performance in such inductor
arrangements. It is for example known to minimise the number of
crossing points. By keeping the number of crossings points at a
minimum, the quality factor of an inductor is increased. This
approach is disclosed in WO2009/101565.
[0012] One of the main characteristic of an inductor is its
resonance frequency
.omega. = 1 LC ( 1 ) ##EQU00001##
[0013] here L is self inductance of an inductor and C is the
parasitic capacitance. As can be seen from this formula,
minimization of the parasitic capacitance leads to an increase of
resonance frequency.
[0014] Another characteristic of an inductor is its Quality factor
(Q-factor):
Q = .omega. L R ( 2 ) ##EQU00002##
[0015] here R is the internal resistance of the inductor.
[0016] From equation (2), it can be seen that the Q-factor of an
inductor is linked to the resonance frequency .omega., such that an
inductor having a higher resonant frequency also tends to have a
higher Q-factor. This is why an increase of the resonance frequency
leads to improvement of the quality factor.
[0017] The parasitic capacitance of an integrated inductor on a
chip has two major contributions: capacitance between the inductor
track and substrate and capacitance between different turns of the
inductor. The capacitance between different turns of the inductor
is dependent on the voltage difference between adjacent turns as
well as the physical proximity of those turns.
[0018] The invention aims to balance the different requirements of
the inductor to achieve high resonance frequency without decreasing
the self inductance.
[0019] According to the invention, there is provided an inductor
comprising a conducting track arranged in loops, each loop
comprising at least two concentric paths, wherein the track length
comprises tap regions at the ends of the tracks and a central track
region which comprises the concentric paths of the loops, wherein
the central track region comprises a sequence of track sections,
each comprising a loop half turn, and crossings between tracks
sections, with the crossings spaced along the central track region
by one or two track sections, wherein the central track section has
a parameter p defined as:
[0020] p=the sum of squares of normalised differences in track
section sequence number for all adjacent pairs of track sections in
each loop,
[0021] wherein the path crossings are at locations such that the
parameter p is the minimum possible value of p.
[0022] This design enables the parasitic capacitance between turns
of substantially symmetrical figure of eight and clover shaped
inductors to be minimised without changing the self inductance.
[0023] The track can comprise a figure of eight with two concentric
paths in each loop, and p=1/4.
[0024] In this design, there can be two crossings, one at the top
and one at the bottom of the figure of eight shape.
[0025] In another design, the track comprises a figure of eight
with three concentric paths in each loop, and p=5/9.
[0026] In this design, there can be four crossings, one at the top
and one at the bottom of the figure of eight shape between the
outermost pair of concentric paths, and two at the crossing area,
one between the innermost pair of concentric paths in one loop and
one between the innermost pair of concentric paths in the other
loop.
[0027] In another design, the track comprises a clover shape with
three concentric paths in each loop, and p=4/9.
[0028] In this design, the track can comprise two figure of eight
shapes side by side, and each figure of eight shape has five
crossings, one at the top and one at the bottom of the figure of
eight shape between the outermost pair of concentric paths, and
three at the crossing area, between the adjacent pairs of
concentric paths.
[0029] The invention also provides a method of designing the layout
of an inductor comprising a conducting track arranged in loops,
each loop comprising at least two concentric paths, wherein the
track length comprises tap regions at the ends of the tracks and a
central track region which comprises the concentric paths of the
loops, wherein the central track region comprises a sequence of
track sections, each comprising a loop half turn, and crossings
between tracks sections, with the crossings spaced along the
central track region by one or two track sections,
[0030] wherein the method comprises defining a parameter p:
[0031] p=the sum of squares of normalised differences in track
section sequence number for all adjacent pairs of track sections in
each loop; and
[0032] selecting the path crossings at locations such that the
parameter p is the minimum possible value of p.
[0033] Examples of the invention will now be described in detail
with reference to the accompanying drawings, in which:
[0034] FIGS. 1A and 1B show two known symmetric inductors;
[0035] FIGS. 2A and 2B show two known symmetric inductors as
disclosed in WO2009/101565;
[0036] FIG. 3 shows a circuit from which the resonance frequency
can be represented;
[0037] FIG. 4 shows a model by which the total parasitic
capacitance for an inductor can be calculated;
[0038] FIGS. 5A, 5B and 5C show examples of figure of eight
configurations of the invention;
[0039] FIG. 6 shows an example of the invention for a clover shape
inductor;
[0040] FIG. 7 shows two possible designs of centre tap connection
for figure of eight designs with three paths per loop;
[0041] FIG. 8 shows two further possible designs of centre tap
connection for figure of eight designs with three paths per loop;
and
[0042] FIG. 9 shows the approach of counting half applied to a
prior art example.
[0043] The invention provides an inductor design in which the path
crossings are designed such that the voltage differences between
the adjacent paths are (in total) minimised. This has the effect of
reducing the capacitance between turns and also reducing the
parasitic capacitances introduced by crossings between those
adjacent turns.
[0044] As mentioned above, the inductors need a substantially
symmetric layout, for example in order to be used as a differential
negative resistance oscillator.
[0045] FIGS. 1A and 1B show two known symmetric inductors. FIG. 1A
shows a figure of eight shape and FIG. 1B shows a clover shape.
[0046] In FIG. 1A, there are two loops, and each loop has three
paths. The track 10 follows a figure of eight shape three times in
series. The centre tap is shown as 12.
[0047] The centre tap is a metal layer beneath the metal layers of
the inductor track. It connects using vias to the inductor
track--for example to the centre point of the track. In common
mode, a potential difference is applied to the terminals and to the
centre tap. In FIG. 1B, there are four loops, and each loop has
three paths. The track 10 follows the clover shape three times in
series. The centre tap is again shown as 12.
[0048] In FIGS. 1A and 1B, the central point of the inductive path
is at the top of the structure, and this is where electrical
connection is made to the centre tap 12.
[0049] FIGS. 2A and 2B show two known symmetric inductors as
disclosed in WO2009/101565. FIG. 2A again shows a figure of eight
shape and FIG. 2B shows a clover shape.
[0050] In FIG. 2A, there are two loops, and each loop has three
paths. Starting from the right hand tap, the track 10 passes from
the centre tap at the bottom to the upper loop, then follows three
turns of the upper loop, then completes the last 2.5 turns of the
bottom loop.
[0051] In FIG. 2B, there are four loops, and each loop has three
paths. Starting from the right hand tap, the track 10 completes
three turns of the four loops, loop by loop (anticlockwise).
[0052] These designs reduce the number of crossing points, and each
crossing is only between two tracks rather than between multiple
tracks as in FIG. 1.
[0053] An inductor at frequencies smaller than the resonance
frequency can be represented by the equivalent network shown in
FIG. 3. Ceff is the effective capacitance. Ceff essentially
comprises the effective capacitance to the substrate, to the ground
shield, and the capacitance between turns.
[0054] For a given technological process, the effective capacitance
between turns of an inductor depends on the distance between turns,
the length of the turns and the average potential difference
between turns. The length of the turns is proportional to the outer
diameter of the inductor. This means that by decreasing the length
of an inductor, the self inductance is decreased. An increase of
the distance between turns also leads to a decrease of the self
inductance of an inductor. Thus, altering the geometrical layout to
reduce the parasitic capacitance will result in an undesirable
reduction in self-inductance.
[0055] FIG. 4 shows a model by which the total parasitic
capacitance for an inductor resulting from parasitic capacitance
between the inductor turns can be calculated.
[0056] Different turns of the inductor have different potential
difference and different capacitance between each other that
contribute to the effective parasitic capacitance.
[0057] An inductor having a voltage V applied across its terminals,
and having a number of turns n, has a total parasitic capacitance
which can be approximated by:
C eff = i 1 / 2 V i 2 C i ( 3 ) ##EQU00003##
[0058] where Vi is the average voltage between the ith pair of
adjacent inductor turns, and Ci is the intrinsic capacitance
between the ith pair of adjacent inductor turns. Thus, by reducing
the potential difference between turns, the effective parasitic
capacitance can be reduced.
[0059] The invention thus provides designs which aim to reduce this
effective capacitance, by designing the inductor path (in
particular the crossing locations) such that the order of the turns
is such that the voltage differences (squared) in total are
minimised. Because the crossings are between adjacent tracks, this
reduction of voltage between adjacent tracks not only reduces the
parasitic capacitance between the turns (this parasitic capacitance
being in the plane of the turns i.e. parallel to the substrate) it
also reduces the parasitic capacitance of the cross overs (this
cross over capacitance being in the layer stacking direction, i.e.
perpendicular to the substrate).
[0060] FIGS. 5A, 5B and 5C show examples of figure of eight
configurations, with reduced potential difference between turns at
the cross over locations and therefore reduced effective
capacitance between turns.
[0061] In all examples of the invention, the inductor comprises a
conducting track 10 arranged in loops, each loop comprising at
least two concentric paths. The track length comprises tap regions
at the ends of the tracks and a central track region which
comprises the concentric paths of the loops.
[0062] There are crossings between paths along the central region.
As explained further below, the design is based on the central
track region design and in particular the choice of the loop
crossings, not the tap design, since various tap design layouts are
possible.
[0063] A detailed analysis of the effective parasitic capacitance
will require an integration, for example a parameter I:
I=.intg.|V1-V2|.sup.2
[0064] where V1 and V2 are the voltages on two adjacent tracks at
the two locations where the tracks are side-by side. It can be
assumed that approximately the track voltage decreases linearly
from one end of the track to the other (although this does not take
account of the changes in resistance at the cross overs). Thus,
this parameter can be simplified by considering the distance from
one end of the track to the locations:
I'=.intg.|d1-d2|.sup.2
[0065] The integration is for all locations where there are
side-by-side track pairs, so that all of the track-to-track
parasitic capacitances are calculated.
[0066] The invention aims to minimise this parameter.
[0067] However, it is possible to model the track in a more simple
manner than suggested by the integral equation above, by virtue of
the symmetry of the layout. In particular, the crossings are
arranged symmetrically (with respect to orthogonal reflection
axes). In addition, the number of crossings should be kept small.
This means that in practice the crossings are all aligned or are
aligned in groups, along symmetry axes of the structure. In the
case of a figure of eight layout, the crossings are aligned along
the central upright axis of the figure of eight shape as in FIG. 1A
and FIG. 2A. In the case of a clover shape layout, the invention is
preferably implemented as two side-by-side figure of eight
layouts.
[0068] This means that in practice, the layouts have crossings
every half loop/turn or every full loop/turn of the inductor
track.
[0069] This means that the effective parasitic capacitance can be
approximated based on a summation of the contribution of each half
turn of the inductor track, since there is a step change each half
turn or full turn. Of course, this simplification disregards the
fact that different loops have different length (as a result of
their different diameter) and that there are some parts of the
track which will not be counted, such as the tap region, but also
any interconnecting track sections which are not part of the
loops.
[0070] To define the invention, the central track section is
defined as having a parameter p:
[0071] p=the sum of squares of normalised differences in track
section sequence number for all adjacent pairs of track sections in
each loop.
[0072] The central track region is considered as comprising a
sequence of track sections, each comprising a loop half turn, and
crossings between tracks sections. The crossings are spaced along
the central track region by one or two track sections. The track
section sequence number represents how far the track section is
from one of the taps.
[0073] FIG. 5A shows a figure of eight shape with only one path per
loop. In this case there are no adjacent track section sequence
numbers.
[0074] FIG. 5B shows a design in accordance with the invention with
two paths per loop. In this design, there are two crossings, one 50
at the top and one 52 at the bottom of the figure of eight
shape.
[0075] The parameter p can be obtained by counting the half turns
from one end of the track to the other.
[0076] FIG. 5B shows this half turn count.
[0077] In FIG. 5B, there are 8 half turns in total, thus eight
sequential track sections.
[0078] The right loop has a lower half with adjacent track sections
1 and 3 and a top half with adjacent track sections 2 and 4.
[0079] The left loop has a lower half with adjacent track sections
5 and 7 and a top half with adjacent track sections 6 and 8.
[0080] This means the parameter p=1/4:
p = ( 3 - 1 8 ) 2 + ( 4 - 2 8 ) 2 + ( 7 - 5 8 ) 2 + ( 8 - 6 8 ) 2 =
1 4 ##EQU00004##
[0081] As is clear from the calculation above, the "normalised"
differences in track section sequence number refer to the
difference in sequence number divided by the total number of track
sections.
[0082] The tail area is between the loops to provide the desired
symmetry.
[0083] In the example of FIG. 5B, the tail area has two crossings
which also contribute to the total capacitance. The two additional
crossings are between the two ends of the track and the
mid-point.
[0084] Thus, the track in this example of the invention comprises a
figure of eight with two paths per loop and p=1/4.
[0085] It is noted that the capacitance between loops is ignored
for this parameter, as it only relates to the adjacent track
sections in the loops. Thus, the parasitic capacitance between
track sections 4 and 8 is ignored, as this is only around one
quarter of a loop. In view of the discrete possible positions for
the cross overs, this does not change the resulting cross over
positions to minimise the value of p.
[0086] FIG. 5C shows a design with three paths per loop. In this
design, there are four crossings, one 54 at the top and one 56 at
the bottom of the figure of eight shape between the outermost pair
of concentric paths, and two at the crossing area, one 58 between
the innermost pair of concentric paths in one loop and one 60
between the innermost pair of concentric paths in the other
loop.
[0087] Using the same approach as explained above for FIG. 5B,
there are 12 half turns in total. Each loop has 4 sets of adjacent
pairs of track sections.
[0088] The right loop has a lower half with adjacent track sections
1 and 5 and 5 and 3, and a top half with adjacent track sections 2
and 4 and 2 and 6.
[0089] The left loop has a lower half with adjacent track sections
7 and 11 and 9 and 11, and a top half with adjacent track sections
10 and 8 and 10 and 12.
[0090] This means the parameter p=5/9:.
p = 4 ( ( 2 12 ) 2 + ( 4 12 ) 2 ) = 5 9 ##EQU00005##
[0091] The tail area is again between the loops to provide the
desired symmetry, and again comprises two additional crossings
between the two ends of the track and the mid-point.
[0092] Thus, the track in this example of the invention comprises a
figure of eight with three paths per loop and p=5/9.
[0093] The inductors of FIGS. 5B and 5C have the same self
inductance as the inductors of FIGS. 2A and 2B.
[0094] Generally, for a figure of eight track, p=(n-1)(2n-1)/6n for
n paths per loop.
[0095] FIG. 6 shows an example of the invention for a clover shape
track with three concentric paths in each loop.
[0096] The track comprises two figure of eight shapes side by side,
and each figure of eight shape has five crossings, one 62 at the
top and one 64 at the bottom of the figure of eight shape between
the outermost pair of concentric paths, and three 66, 68, 70 at the
crossing area, between the adjacent pairs of concentric paths. The
crossings for the right figure of eight are labelled as 62' to
70'.
[0097] Again, using the same approach as explained above, there are
24 half turns in total. The design can be seen as two side-by-side
figure of eight shapes. The track section between the centre tap
location and the cross overs 64 are ignored, as these sections are
considered not part of the loops - they are instead sections simply
joining the two figure of eight shapes together. The track section
numbers are shown in FIG. 6.
[0098] For the right figure of eight:
[0099] The bottom loop has adjacent track sections 1 and 3, 1 and
5, 2 and 4, 4 and 12.
[0100] The top loop has adjacent track sections 9 and 7, 7 and 11,
8 and 10, 6 and 10.
[0101] For the left figure of eight:
[0102] The bottom loop has adjacent track sections 13 and 17, 13
and 15, 14 and 16, 16 and 24.
[0103] The top loop has adjacent track sections 19 and 21, 19 and
23, 20 and 22, 22 and 18.
[0104] Thus, the track in this example of the invention comprises a
clover shape with three paths per loop and p=4/9
(256/24.sup.2).
[0105] Generally, for a clover shaped track, p=(2n.sup.2-3n+7)/12n
for n paths per loop. Thus, for two paths per loop in a clover
layout, p=3/8.
[0106] In FIGS. 5 and 6, the connection of the centre tap to the
inductor track is to the centre of the track.
[0107] There are many different ways to implement the crossing
points at the location of the centre tap 12.
[0108] FIGS. 7 and 8 show four possible designs of centre tap
connection for figure of eight designs with three paths per
loop.
[0109] FIGS. 7 and 8 show that slightly different designs can give
rise to one or two crossings at the tap location. When there are
two crossings, they are between the two ends of the track and the
mid-point. When there is one crossing, it is between one end of the
track and the mid-point.
[0110] The designs of crossing points at the location where centre
tap is connected as shown in FIGS. 7 and 8 can be applied to the
clover shape inductors.
[0111] FIG. 9 shows a known design based on the approach in
WO2009/101565 (of completing the top loop before returning to the
bottom loop).
[0112] In this case, p=48/64=3/4.
[0113] A further advantage of the design of FIG. 5B compared to
FIG. 9 is that the feed lines do not couple magnetically with the
rest of the inductor when it is used in common mode as opposed to
the design of FIG. 9. This means that the point where central tap
is connected is a middle point of the inductor not only from the
resistance but also from the inductance point of view.
[0114] The same logic applied to the prior art of FIG. 1 shows that
this design has even higher capacitance between turns.
[0115] In the designs of the invention, there are crossings only
between two tracks rather than between multiple tracks as in FIG.
1.
[0116] The main aim of the invention is to minimise the
loop-to-loop parasitic capacitances. As explained above, a further
benefit is that the cross over parasitic capacitance is also
reduced.
[0117] The invention allows building inductors of low magnetic
stray field with high resonance frequency. The invention is
especially relevant for multiple turn inductors. Proposed layouts
are substantially symmetric and therefore can be used not only in
differential but also in the common mode.
[0118] As mentioned above, the inductance is typically in the nH
range, such as 1 nH to 60 nH. The inductor track typically has a
width in the range 0.5 .mu.m to 50 .mu.m.
[0119] The inductor track is formed of aluminium or copper for
example. They can be formed as part of a CMOS or QUBIC process.
[0120] Other variations to the disclosed embodiments can be
understood and effected by those skilled in the art in practicing
the claimed invention, from a study of the drawings, the
disclosure, and the appended claims. In the claims, the word
"comprising" does not exclude other elements or steps, and the
indefinite article "a" or "an" does not exclude a plurality. The
mere fact that certain measures are recited in mutually different
dependent claims does not indicate that a combination of these
measured cannot be used to advantage. Any reference signs in the
claims should not be construed as limiting the scope.
* * * * *