U.S. patent application number 14/532725 was filed with the patent office on 2016-03-10 for semiconductor apparatus and test device therefor.
The applicant listed for this patent is SK hynix Inc.. Invention is credited to Young Jun KU, Chang Hyun LEE.
Application Number | 20160069959 14/532725 |
Document ID | / |
Family ID | 55275379 |
Filed Date | 2016-03-10 |
United States Patent
Application |
20160069959 |
Kind Code |
A1 |
LEE; Chang Hyun ; et
al. |
March 10, 2016 |
SEMICONDUCTOR APPARATUS AND TEST DEVICE THEREFOR
Abstract
A semiconductor apparatus includes a clock enable signal buffer
unit configured to receive an input clock enable signal, and
generate an output clock enable signal; a buffer control unit
configured to generate a buffer enable signal in response to the
output clock enable signal and a test enable signal; an
input/output buffer unit configured to receive input patterns and
generate output patterns; and a compression test unit configured to
test the output patterns and the output clock enable signal
according to the test enable signal.
Inventors: |
LEE; Chang Hyun; (Icheon-si
Gyeonggi-do, KR) ; KU; Young Jun; (Icheon-si
Gyeonggi-do, KR) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
SK hynix Inc. |
Icheon-si Gyeonggi-do |
|
KR |
|
|
Family ID: |
55275379 |
Appl. No.: |
14/532725 |
Filed: |
November 4, 2014 |
Current U.S.
Class: |
365/189.05 ;
324/750.3 |
Current CPC
Class: |
G11C 7/1084 20130101;
G01R 31/31727 20130101; G11C 29/022 20130101; G11C 29/40
20130101 |
International
Class: |
G01R 31/317 20060101
G01R031/317; G11C 7/22 20060101 G11C007/22; G11C 29/02 20060101
G11C029/02; G11C 7/10 20060101 G11C007/10 |
Foreign Application Data
Date |
Code |
Application Number |
Sep 5, 2014 |
KR |
10-2014-0118829 |
Claims
1. A semiconductor apparatus comprising: a clock enable signal
buffer unit configured to receive an input clock enable signal, and
generate an output clock enable signal; a buffer control unit
configured to generate a buffer enable signal in response to the
output clock enable signal and a test enable signal; an
input/output buffer unit configured to receive input patterns and
generate output patterns; and a compression test unit configured to
test the output patterns and the output clock enable signal
according to the test enable signal.
2. The semiconductor apparatus according to claim 1, wherein the
buffer control unit generates the buffer enable signal which is
independent of a level of the output clock enable signal.
3. The semiconductor apparatus according to claim 1, wherein the
compression test unit includes a multiple input signature
register.
4. The semiconductor apparatus according to claim 1, wherein the
compression test unit comprises: a compressing section configured
to compress the output patterns in parallel and generate a
compressed signal; and a comparing section configured to compare
the compressed signal and a reference signal, and generate a test
result signal.
5. The semiconductor apparatus according to claim 1, wherein the
input/output buffer unit includes a plurality of input/output
buffers, and the compression test unit receives in parallel the
output patterns respectively outputted from the plurality of
input/output buffers.
6. A test device comprising: a buffer control unit configured to
generate a buffer enable signal in response to an output clock
enable signal provided from a clock enable signal buffer unit and a
test enable signal; and a compression test unit configured to test
output patterns provided from an input/output buffer unit and the
output clock enable signal in response to the test enable
signal.
7. The test device according to claim 6, wherein the buffer control
unit generates the buffer enable signal, wherein the buffer enable
signal is independent of a level of the output clock enable
signal.
8. The test device according to claim 6, wherein the compression
test unit includes a multiple input signature register.
9. The test device according to claim 6, wherein the compression
test unit comprises: a compressing section configured to compress
the output patterns in parallel and generate a compressed signal;
and a comparing section configured to compare the compressed signal
and a reference signal, and generate a test result signal.
10. The test device according to claim 6, wherein the input/output
buffer unit includes a plurality of input/output buffers, and the
compression test unit receives in parallel the output patterns
respectively outputted from the plurality of input/output
buffers.
11. A semiconductor apparatus comprising: a clock enable signal
buffer unit configured to buffer an input enable signal provided
from a memory device and to generate an output clock enable signal;
a logic circuit configured to output a buffer enable signal in
response to the output clock enable signal and a test enable
signal; an input/output buffer unit configured to generate output
patterns in response to the buffer enable signal; and a compression
test unit driven in response to the test enable signal to perform a
test by receiving the output patterns and the output clock enable
signal and to output a test result signal.
12. The semiconductor apparatus according to claim 11, wherein the
compression test unit includes a multiple input signature register
(MISR) configured to compress test patterns.
13. The semiconductor apparatus according to claim 12, where the
compression test unit comprises: a compression section configured
to receive the output patterns and to output a compressed signal;
and a comparing section configured to compare the compressed signal
with a reference signal and output a comparison result as the test
result signal.
14. The semiconductor apparatus according to claim 13, wherein the
test result signal allows for a determination to made as to whether
abnormalities are found with the input/output buffer unit and the
clock enable signal buffer.
15. The semiconductor apparatus according to claim 11, wherein the
clock enable signal buffer unit is tested with a plurality of IO
buffers that are included in the input/output buffer unit.
16. The semiconductor apparatus according to claim 11, wherein the
compression test unit is configured to test in parallel the output
patterns and the output clock enable signal.
17. The semiconductor apparatus according to claim 15, wherein the
plurality of IO buffers and the clock enable signal buffer unit can
be tested when the plurality of IO buffers are in an on-state.
18. The semiconductor apparatus according to claim 17, wherein the
plurality of IO buffers are turned off and on in response to a
clock enable signal.
19. The semiconductor apparatus according to claim 15, wherein the
output patterns are outputted simultaneously from the to plurality
of IO buffers and are provided to the compression test unit.
20. The semiconductor apparatus according to claim 11, wherein the
input/output buffer unit is in an on-state in a test mode.
Description
CROSS-REFERENCES TO RELATED APPLICATION
[0001] The present application claims priority under 35 U.S.C.
.sctn.119(a) to Korean application number 10-2014-0118829, filed on
Sep. 5, 2014, in the Korean Intellectual Property Office, which is
incorporated herein by reference in its entirety.
BACKGROUND
[0002] 1. Technical Field
[0003] Various embodiments generally relate to a semiconductor
integrated apparatus, and more particularly, to a semiconductor
apparatus and a test device therefor.
[0004] 2. Related Art
[0005] The degree of integration of a semiconductor apparatus is
improved as time goes on. Further, a multi-chip structure in which
a plurality of chips are packaged into one package, a
system-on-chip structure in which a system is configured by one
chip, and so forth have been developed.
[0006] After a semiconductor apparatus is manufactured, a procedure
for testing the performance of the semiconductor apparatus is
performed to check whether a fail has occurred in a manufacturing
process.
[0007] In particular, an input/output buffer, a clock enable
buffer, and so forth, which are disposed in a semiconductor
apparatus, should be necessarily tested to check the integrity of
signals to be transmitted and received between a semiconductor
memory apparatus and an external device.
[0008] As a semiconductor apparatus is highly integrated, a precise
and high speed test method has been demanded.
SUMMARY
[0009] In an embodiment, a semiconductor apparatus may include a
clock enable signal buffer unit configured to receive an input
clock enable signal, and generate an output clock enable signal.
The semiconductor apparatus may include a buffer control unit
configured to generate a buffer enable signal in response to the
output clock enable signal and a test enable signal. The
semiconductor apparatus may include an input/output buffer unit
configured to receive input patterns and generate output patterns.
Further, the semiconductor apparatus may include a compression test
unit configured to test the output patterns and the output clock
enable signal according to the test enable signal.
[0010] In an embodiment, a test device may include a buffer control
unit configured to generate a buffer enable signal in response to
an output clock enable signal provided from a clock enable signal
buffer unit and a test enable signal. The test device may also
include a compression test unit configured to test output patterns
provided from an input/output buffer unit and the output clock
enable signal in response to the test enable signal.
[0011] In an embodiment, a semiconductor apparatus may include a
clock enable signal buffer unit configured to buffer an input
enable signal provided from a memory device and to generate an
output clock enable signal. The semiconductor apparatus may also
include a logic circuit configured to output a buffer enable signal
in response to the output clock enable signal and a test enable
signal. Further, the semiconductor apparatus may include an
input/output buffer unit configured to generate output patterns in
response to the buffer enable signal. The semiconductor apparatus
may also include a to compression test unit driven in response to
the test enable signal to perform a test by receiving the output
patterns and the output clock enable signal and to output a test
result signal.
BRIEF DESCRIPTION OF THE DRAWINGS
[0012] FIG. 1 is a configuration diagram illustrating a
representation of an example of a semiconductor apparatus in
accordance with an embodiment.
[0013] FIGS. 2A and 2B are diagrams illustrating representations of
examples of a buffer control unit in accordance with an
embodiment.
[0014] FIG. 3 is a configuration diagram illustrating a
representation of an example of an input/output buffer unit in
accordance with an embodiment.
[0015] FIG. 4 is a configuration diagram illustrating a
representation of an example of a compression test unit in
accordance with an embodiment.
[0016] FIG. 5 is a configuration diagram illustrating a
representation of an example of a compressing section in accordance
with an embodiment.
[0017] FIG. 6 illustrates a block diagram of a system employing a
memory controller circuit in accordance with an embodiment of the
invention.
DETAILED DESCRIPTION
[0018] Hereinafter, a semiconductor apparatus and a test device
therefor will be described with reference to the accompanying
drawings through various embodiments.
[0019] Referring to FIG. 1, a configuration diagram illustrating a
representation of an example of a semiconductor apparatus in
accordance with an embodiment is shown.
[0020] A semiconductor apparatus 10 may include a memory device 20,
a clock enable signal (CKE) buffer unit 100, a buffer control unit
200, an input/output buffer unit 300, and a compression test unit
400. In an embodiment, the buffer control unit 200 and the
compression test unit 400 may configure a test device 30.
[0021] The clock enable signal buffer unit 100 buffers an input
clock enable signal CKEi provided from the memory device 20. The
clock enable signal buffer unit 100 also generates an output clock
enable signal CKEo.
[0022] The buffer control unit 200 generates a buffer enable signal
BUF_EN in response to the output clock enable signal CKEo and a
test enable signal MISR_EN. In particular, the buffer control unit
200 may be configured to output the buffer enable signal BUF_EN
which has a preset level regardless of the level of the output
clock enable signal CKEo when the test enable signal MISR_EN is
enabled.
[0023] Referring to FIGS. 2a and 2b, diagrams illustrating
representations of examples of the buffer control unit 200 are
shown.
[0024] A buffer control unit 200-1 shown in FIG. 2a may include a
first logic circuit 201 which outputs the buffer enable signal
BUF_EN in response to the output clock enable signal CKEo and the
test enable signal MISR_EN. The first logic circuit 201 may be an
OR gate.
[0025] A buffer control unit 200-2 shown in FIG. 2b may include a
second logic circuit 203. The second logic circuit 203 may include,
for example, a NOR gate.
[0026] The input/output buffer unit 300 buffers input patterns
Pin<0:n> provided from the memory device 20. The input/output
buffer unit 300 also generates output patterns Pout<0:n>.
More specifically, the input/output buffer unit 300 generates the
output patterns Pout<0:n> in response to the buffer enable
signal BUF_EN generated by the buffer control unit 200.
Accordingly, the input/output buffer unit 300 retains an on state
without relying on the level of the output clock enable signal CKEo
in a test mode. Further, the input/output buffer unit 300 may
generate the output patterns Pout<0:n> according to the
buffer enable signal BUF_EN which always has a fixed output level
in the test mode.
[0027] Referring to FIG. 3, an example of the input/output buffer
unit 300 is shown.
[0028] An input/output buffer unit 300-1 shown in FIG. 3 may
include a plurality of IO buffers 301-0 to 301-n provided with and
buffer the input patterns Pin<0:n> and generate the output
patterns Pout<0:n>. The output patterns Pout<0:n> which
are outputted simultaneously from the plurality of IO buffers 301-0
to 301-n may be provided to the compression test unit 400.
[0029] The compression test unit 400 is driven in response to the
test enable signal MISR_EN. The compression test unit 400 performs
to a test by receiving the output patterns Pout<0:n> from the
input/output buffer unit 300 and the output clock enable signal
CKEo from the clock enable signal buffer unit 100. The compression
test unit 400 also outputs a test result signal MISR_OUT.
[0030] The compression test unit 400 may use, for example, a
multiple input signature register (MISR). The MISR is a test device
which compresses test patterns in parallel and tests integrity. In
the MISR, a characteristic that a compression result is outputted
differently from a predicted value (a reference signal) when even
one of inputted test patterns has an erroneous value is used.
[0031] Referring to FIG. 4, an example of the compression test unit
400 is shown.
[0032] In FIG. 4, a compression test unit 400-1 may include a
compressing section 401 and a comparing section 403.
[0033] The compressing section 401 receives the output patterns
Pout<0:n> and outputs a compressed signal Pout_COM.
[0034] The comparing section 403 compares the compressed signal
Pout_COM with a reference signal REF which is stored in advance.
The comparing section 403 also outputs a comparison result as the
test result signal MISR_OUT. The reference signal REF may be preset
through a simulation for the input/output buffer unit 300 and the
clock enable signal buffer unit 100. The reference signal REF may
also be stored in advance in a specified register.
[0035] According to the test result signal MISR_OUT outputted from
the comparing section 403, it is possible to check whether the
input/output buffer unit 300 and the clock enable signal buffer
unit 100 are normal or abnormal.
[0036] Referring to FIG. 5, an example of a compressing section
401-1 is shown.
[0037] The compressing section 401-1 may include a plurality of
unit cells 403-0 to 403-n. The number of the unit cells 403-0 to
403-n may correspond to the number of the bits of the output
patterns Pout<0:n>.
[0038] The respective unit cells 403-0 to 403-n may include, but
not limited to, adders which receive, as input signals, the
respective bits of the output patterns Pout<0:n>, the output
signals of previous stage unit cells and the output signal of a
final stage unit cell, and registers which delay the output signals
of the adders by a predetermined time.
[0039] In an embodiment, it is to be noted that the clock enable
signal buffer unit 100 is tested together with the plurality of IO
buffers which configure the input/output buffer unit 300.
[0040] IO buffers are generally turned on and off by a clock enable
signal. In this regard, if the clock enable signal is disabled in a
test mode, since the IO buffers are turned off, a test may not be
normally performed. Moreover, a clock enable signal buffer unit
should be tested in its performance.
[0041] Therefore, by retaining the IO buffers 301-0 to 301-n in on
states regardless of the output signals of the clock enable signal
buffer unit 100, it is possible to test both the IO buffers 301-0
to 301-n and the clock enable signal buffer unit 100.
[0042] The output patterns Pout<0:n> provided from the
input/output buffer unit 300 and the output clock enable signal
CKEo provided from the clock enable signal buffer unit 100 may be
tested at a high speed in parallel by the compression test unit
400.
[0043] Referring to FIG. 6, a system 1000 may include one or more
processors 1100. The processor 1100 may be used individually or in
combination with other processors. A chipset 1150 may operably
electrically coupled to the processor 1100. The chipset 1150 is a
communication pathway for signals between the processor 1100 and
other components of the system 1000. Other components of the system
1000 may include a memory controller 1200, an input/output ("I/O")
bus 1250, and a disk drive controller 1300. Depending on the
configuration of the system 1000, any one of a number of different
signals may be transmitted through the chipset 1150.
[0044] The memory controller 1200 may be operably electrically
coupled to the chipset 1150. The memory controller 1200 can receive
a request provided from the processor 1100 through the chipset
1150. The memory controller 1200 may be operably electrically
coupled to one or more memory devices 1350. The memory devices 1350
may include the semiconductor apparatus 10 described above.
[0045] The chipset 1150 may also be electrically coupled to the I/O
bus 1250. The I/O bus 1250 may serve as a communication pathway for
signals form the chipset 1150 to I/O devices 1410, 1420 and 1430.
The I/O devices 1410, 1420 and 1430 may include a mouse 1410, a
video display 1420, or a keyboard 1430. The I/O bus 1250 may employ
any one of a number of communications protocols to communicate with
the I/O devices 1410, 1420, and 1430.
[0046] The disk drive controller 1300 may also be operably
electrically coupled to the chipset 1150. The disk drive controller
1300 may serve as the communication pathway between the chipset
1150 and one or more internal disk drives 1450. The disk drive
controller 1300 and the internal disk drives 1450 may communicate
with each other or with the chipset 1150 using virtually any type
of communication protocol, including all of those mentioned above
with regard to the I/O bus 1250.
[0047] While various embodiments have been described above, it will
be understood to those skilled in the art that the embodiments
described are by way of example only. Accordingly, the
semiconductor apparatus and the test device described should not be
limited based on the described embodiments.
* * * * *