U.S. patent application number 14/937357 was filed with the patent office on 2016-03-03 for semiconductor device and method for producing a semiconductor device.
The applicant listed for this patent is UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.. Invention is credited to FUJIO MASUOKA, HIROKI NAKAMURA.
Application Number | 20160064662 14/937357 |
Document ID | / |
Family ID | 52437471 |
Filed Date | 2016-03-03 |
United States Patent
Application |
20160064662 |
Kind Code |
A1 |
MASUOKA; FUJIO ; et
al. |
March 3, 2016 |
SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING A SEMICONDUCTOR
DEVICE
Abstract
A semiconductor device includes first pillar-shaped silicon
layers, a first gate insulating film formed around the first
pillar-shaped silicon layers, gate electrodes formed of metal and
formed around the first gate insulating film, gate lines formed of
metal and connected to the gate electrodes, a second gate
insulating film formed around upper portions of the first
pillar-shaped silicon layers, first contacts formed of a first
metal material and formed around the second gate insulating film,
second contacts formed of a second metal material and connecting
upper portions of the first contacts and upper portions of the
first pillar-shaped silicon layers, second diffusion layers formed
in lower portions of the first pillar-shaped silicon layers, and
variable-resistance memory elements formed on the second
contacts.
Inventors: |
MASUOKA; FUJIO; (TOKYO,
JP) ; NAKAMURA; HIROKI; (TOKYO, JP) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
UNISANTIS ELECTRONICS SINGAPORE PTE. LTD. |
SINGAPORE |
|
SG |
|
|
Family ID: |
52437471 |
Appl. No.: |
14/937357 |
Filed: |
November 10, 2015 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
PCT/JP2013/076031 |
Sep 26, 2013 |
|
|
|
14937357 |
|
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Current U.S.
Class: |
257/4 ;
438/268 |
Current CPC
Class: |
H01L 29/66545 20130101;
H01L 27/10879 20130101; H01L 45/04 20130101; H01L 27/2454 20130101;
H01L 45/144 20130101; H01L 27/0886 20130101; H01L 45/06 20130101;
H01L 45/1233 20130101; H01L 45/16 20130101; H01L 29/66666 20130101;
H01L 29/785 20130101; H01L 45/126 20130101; G11C 13/0002 20130101;
H01L 29/66795 20130101 |
International
Class: |
H01L 45/00 20060101
H01L045/00; H01L 29/66 20060101 H01L029/66; H01L 27/24 20060101
H01L027/24 |
Claims
1. A semiconductor device, comprising: a first pillar-shaped
semiconductor layer, a first gate insulating film formed around
said first pillar-shaped semiconductor layer, a gate electrode
formed of metal and formed around said first gate insulating film,
a gate line formed of metal and connected to said gate electrode, a
second gate insulating film formed around an upper portion of said
first pillar-shaped semiconductor layer, a first contact formed of
a first metal material and formed around said second gate
insulating film, a second contact formed of a second metal material
and connecting an upper portion of said first contact and an upper
portion of said first pillar-shaped semiconductor layer, a second
diffusion layer formed in a lower portion of said first
pillar-shaped semiconductor layer, and a variable-resistance memory
element formed on said second contact.
2. The semiconductor device according to claim 1, wherein said
first metal material forming said first contact has a work function
of between 4.0 and 4.2 eV.
3. The semiconductor device according to claim 1, wherein said
first metal material forming said first contact has a work function
of between 5.0 and 5.2 eV.
4. The semiconductor device according to claim 1, further
comprising: a fin-shaped semiconductor layer formed on a
semiconductor substrate so as to extend in one direction, a first
insulating film formed around said fin-shaped semiconductor layer,
said first pillar-shaped semiconductor layer formed on said
fin-shaped semiconductor layer, and said first gate insulating film
formed around and below said gate electrode and said gate line,
wherein said gate line extends in a direction orthogonal to said
fin-shaped semiconductor layer, and said second diffusion layer is
formed in said fin-shaped semiconductor layer.
5. The semiconductor device according to claim 4, wherein said
second diffusion layer formed in said fin-shaped semiconductor
layer is further formed in said semiconductor substrate.
6. The semiconductor device according to claim 4, further
comprising a contact line extending parallel with said gate line
and connected to said second diffusion layer.
7. The semiconductor device according to claim 6, further
comprising: said fin-shaped semiconductor layer formed on said
semiconductor substrate, said first insulating film formed around
said fin-shaped semiconductor layer, a second pillar-shaped
semiconductor layer formed on said fin-shaped semiconductor layer,
a contact electrode formed of metal and formed around said second
pillar-shaped semiconductor layer, said contact line formed of
metal, extending in a direction orthogonal to said fin-shaped
semiconductor layer, and connected to said contact electrode, and
said second diffusion layer formed in said fin-shaped semiconductor
layer and in a lower portion of said second pillar-shaped
semiconductor layer, wherein said contact electrode is connected to
said second diffusion layer.
8. The semiconductor device according to claim 4, wherein: an outer
linewidth of said gate electrode is equal to a linewidth of said
gate line, and a linewidth of said first pillar-shaped
semiconductor layer in the direction orthogonal to said fin-shaped
semiconductor layer is equal to a linewidth of said fin-shaped
semiconductor layer in the direction orthogonal to said fin-shaped
semiconductor layer.
9. The semiconductor device according to claim 7, wherein a portion
of said first gate insulating film is formed between said second
pillar-shaped semiconductor layer and said contact electrode.
10. The semiconductor device according to claim 7, wherein a
linewidth of said second pillar-shaped semiconductor layer
extending in the direction orthogonal to said fin-shaped
semiconductor layer is equal to a linewidth of said fin-shaped
semiconductor layer in a direction orthogonal to a direction in
which said fin-shaped semiconductor layer extends.
11. The semiconductor device according to claim 9, wherein a
portion of said first gate insulating film is formed around said
contact electrode and around said contact line.
12. The semiconductor device according to claim 7, wherein an outer
linewidth of said contact electrode is equal to a linewidth of said
contact line.
13. The semiconductor device according to claim 1, further
comprising: said first pillar-shaped semiconductor layer formed on
a semiconductor substrate, and said first gate insulating film
formed around and below said gate electrode and said gate line,
wherein said second diffusion layer is formed in said semiconductor
substrate.
14. The semiconductor device according to claim 13, further
comprising a contact line extending parallel with said gate line
and connected to said second diffusion layer.
15. The semiconductor device according to claim 14, further
comprising: a second pillar-shaped semiconductor layer formed on
said semiconductor substrate, a contact electrode formed of metal
and formed around said second pillar-shaped semiconductor layer, a
contact line connected to said contact electrode, and said second
diffusion layer formed in a lower portion of said second
pillar-shaped semiconductor layer, wherein said contact electrode
is connected to said second diffusion layer.
16. The semiconductor device according to claim 12, wherein an
outer linewidth of said gate electrode is equal to a linewidth of
said gate line.
17. The semiconductor device according to claim 15, wherein a
portion of said first gate insulating film is formed between said
second pillar-shaped semiconductor layer and said contact
electrode.
18. The semiconductor device according to claim 17, wherein a
portion of said first gate insulating film is formed around said
contact electrode and around said contact line.
19. The semiconductor device according to claim 15, wherein an
outer linewidth of said contact electrode is equal to a linewidth
of said contact line.
20. A method for producing a semiconductor device, the method
comprising: a first step of forming a fin-shaped semiconductor
layer on a semiconductor substrate so as to extend in one direction
and forming a first insulating film around the fin-shaped
semiconductor layer, a second step, following the first step, of
forming a first pillar-shaped semiconductor layer, a first dummy
gate derived from a first polysilicon, a second pillar-shaped
semiconductor layer, and a second dummy gate derived from the first
polysilicon, a third step, following the second step, of forming a
third dummy gate and a fourth dummy gate on side walls of the first
dummy gate, the first pillar-shaped semiconductor layer, the second
dummy gate, and the second pillar-shaped semiconductor layer, a
fourth step, following the third step, of forming a second
diffusion layer in an upper portion of the fin-shaped semiconductor
layer, in a lower portion of the first pillar-shaped semiconductor
layer, and in a lower portion of the second pillar-shaped
semiconductor layer, a fifth step, following the fourth step, of
depositing a first interlayer insulating film and performing
chemical mechanical polishing to expose upper portions of the first
dummy gate, the second dummy gate, the third dummy gate, and the
fourth dummy gate, removing the first dummy gate, the second dummy
gate, the third dummy gate, and the fourth dummy gate, forming a
first gate insulating film around the first pillar-shaped
semiconductor layer and around the second pillar-shaped
semiconductor layer, removing the first gate insulating film from
around a bottom portion of the second pillar-shaped semiconductor
layer, depositing a first metal layer and performing etch back to
expose an upper portion of the first pillar-shaped semiconductor
layer and an upper portion of the second pillar-shaped
semiconductor layer, to form a gate electrode and a gate line
around the first pillar-shaped semiconductor layer, and to form a
contact electrode and a contact line around the second
pillar-shaped semiconductor layer, a sixth step, following the
fifth step, of depositing a second gate insulating film around the
first pillar-shaped semiconductor layer, on the gate electrode and
the gate line, around the second pillar-shaped semiconductor layer,
and on the contact electrode and the contact line, depositing a
second metal layer and performing etch back to expose an upper
portion of the first pillar-shaped semiconductor layer and an upper
portion of the second pillar-shaped semiconductor layer, removing
the second gate insulating film on the first pillar-shaped
semiconductor layer, depositing a third metal layer, partially
etching the third metal layer and the second metal layer to form,
from the second metal layer, a first contact surrounding an upper
side wall of the first pillar-shaped semiconductor layer and to
form, from the third metal layer, a second contact connecting an
upper portion of the first contact and an upper portion of the
first pillar-shaped semiconductor layer, and a seventh step,
following the sixth step, of depositing a second interlayer
insulating film, performing planarization to expose an upper
portion of the second contact, and forming a variable-resistance
memory element on the second contact.
21. The method for producing a semiconductor device according to
claim 20, wherein the second step comprises: forming a second
insulating film around the fin-shaped semiconductor layer,
depositing the first polysilicon on the second insulating film and
planarizing the first polysilicon, forming a second resist for
forming the gate line, the first pillar-shaped semiconductor layer,
the contact line, and the second pillar-shaped semiconductor layer
in a direction orthogonal to a direction in which the fin-shaped
semiconductor layer extends, using the second resist as a mask and
etching the first polysilicon, the second insulating film, and the
fin-shaped semiconductor layer to form the first pillar-shaped
semiconductor layer, the first dummy gate derived from the first
polysilicon, the second pillar-shaped semiconductor layer, and the
second dummy gate derived from the first polysilicon.
22. The method for producing a semiconductor device according to
claim 21, which comprises, after the first polysilicon is deposited
on the second insulating film and planarized, forming a third
insulating film on the first polysilicon.
23. The method for producing a semiconductor device according to
claim 21, wherein the third step comprises: forming a fourth
insulating film around the first pillar-shaped semiconductor layer,
the second pillar-shaped semiconductor layer, the first dummy gate,
and the second dummy gate; depositing a second polysilicon around
the fourth insulating film and etching the second polysilicon so as
to remain on side walls of the first dummy gate, the first
pillar-shaped semiconductor layer, the second dummy gate, and the
second pillar-shaped semiconductor layer to form the third dummy
gate and the fourth dummy gate.
24. The method for producing a semiconductor device according to
claim 23, wherein the fourth step comprises: forming the second
diffusion layer in an upper portion of the fin-shaped semiconductor
layer, in a lower portion of the first pillar-shaped semiconductor
layer, and in a lower portion of the second pillar-shaped
semiconductor layer; forming a fifth insulating film around the
third dummy gate and the fourth dummy gate and etching the fifth
insulating film so as to have a sidewall shape to form sidewalls
derived from the fifth insulating film; and forming a compound
layer formed of metal and semiconductor on the second diffusion
layer.
25. The method for producing a semiconductor device according to
claim 24, wherein the fifth step comprises: depositing the first
interlayer insulating film and performing chemical mechanical
polishing to expose upper portions of the first dummy gate, the
second dummy gate, the third dummy gate, and the fourth dummy gate;
removing the first dummy gate, the second dummy gate, the third
dummy gate, and the fourth dummy gate; removing the second
insulating film and the fourth insulating film; forming the first
gate insulating film around the first pillar-shaped semiconductor
layer, around the second pillar-shaped semiconductor layer, and on
inner sides of the fifth insulating film; forming a third resist
for removing the first gate insulating film from around a bottom
portion of the second pillar-shaped semiconductor layer; removing
the first gate insulating film from around the bottom portion of
the second pillar-shaped semiconductor layer; depositing a metal
layer; and performing etch back to expose an upper portion of the
first pillar-shaped semiconductor layer and an upper portion of the
second pillar-shaped semiconductor layer, to form the gate
electrode and the gate line around the first pillar-shaped
semiconductor layer and to form the contact electrode and the
contact line around the second pillar-shaped semiconductor layer.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application is a continuation of copending
international patent application PCT/JP2013/076031, filed Sep. 26,
2013; the entire contents of the prior application are incorporated
herein by reference.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates to a semiconductor device and
a method for producing a semiconductor device.
[0004] 2. Description of the Related Art
[0005] In recent years, phase-change memories have been developed
(for example, refer to Japanese Unexamined Patent Application
Publication No. 2012-204404 and its counterpart U.S. Pat. No.
9,025,369 B2). Such a phase-change memory records changes in the
resistances of information memory elements in memory cells to
thereby store information.
[0006] The phase-change memory uses the following mechanism:
turning on a cell transistor causes a current to pass between a bit
line and a source line; this causes a high-resistance-element
heater to generate heat; this melts chalcogenide glass (GST:
Ge.sub.2Sb.sub.2Te.sub.5) in contact with the heater to thereby
cause a state transition. Chalcogenide glass that is melted at a
high temperature (with a large current) and rapidly cooled (by
stopping the current) is brought to an amorphous state (Reset
operation). On the other hand, chalcogenide glass that is melted at
a relatively-low high temperature (with a small current) and slowly
cooled (with a gradual decrease in the current) is brought to
crystallization (Set operation). Thus, at the time of reading
information, the binary information ("0" or "1") is determined on
the basis of whether a large current passes between the bit line
and the source line (a low resistance, that is, the crystalline
state) or a small current passes (a high resistance, that is, the
amorphous state) (for example, refer to Japanese Unexamined Patent
Application Publication No. 2012-204404 and U.S. Pat. No. 9,025,369
B2).
[0007] In this case, for example, a very large reset current of 200
.mu.A passes. In order to pass such a large reset current through
cell transistors, the memory cells need to have a considerably
large size. In order to pass such a large current, selection
elements such as bipolar transistors and diodes can be used (for
example, refer to Japanese Unexamined Patent Application
Publication No. 2012-204404 and U.S. Pat. No. 9,025,369 B2).
[0008] A diode is a two-terminal element. Thus, when one source
line is selected for the purpose of selecting a memory cell, the
current of all the memory cells connected to the source line passes
through the one source line. This results in a large IR drop, which
is a voltage drop equal to the product of IR (current and
resistance) based on the resistance of the source line.
[0009] On the other hand, a bipolar transistor is a three-terminal
element. However, a current passes through the gate, which makes it
difficult to connect a large number of transistors to the word
line.
[0010] A Surrounding Gate Transistor (hereafter, referred to as an
"SGT") has been proposed that has a structure in which a source, a
gate, and a drain are arranged in a direction perpendicular to a
substrate and a gate electrode surrounds a pillar-shaped
semiconductor layer. SGTs allow a larger current per unit gate
width to pass than double-gate transistors (for example, refer to
Japanese Unexamined Patent Application Publication No. 2004-356314
and its counterpart U.S. Publication US 2004/0262681 A1). In
addition, SGTs have a structure in which the gate electrode
surrounds the pillar-shaped semiconductor layer. Thus, the gate
width per unit area can be increased, so that an even larger
current can be passed.
[0011] In a phase-change memory, a large reset current is used and
hence the resistance of the source line needs to be decreased.
[0012] In existing MOS transistors, in order to successfully
perform a metal gate process and a high-temperature process, a
metal gate-last process of forming a metal gate after a
high-temperature process is used (for example, refer to IEDM2007 K.
Mistry et. al, pp 247-250). In that process, a gate is formed of
polysilicon; an interlayer insulating film is subsequently
deposited; chemical mechanical polishing is then performed to
expose the polysilicon gate; the polysilicon gate is etched; and
metal is subsequently deposited. Thus, also in the production of an
SGT, in order to successfully perform a metal gate process and a
high-temperature process, a metal gate-last process of forming a
metal gate after a high-temperature process needs to be used.
[0013] In the metal gate-last process, after a polysilicon gate is
formed, a diffusion layer is formed by ion implantation. However,
in an SGT, the upper portion of the pillar-shaped silicon layer is
covered with a polysilicon gate. Accordingly, it is necessary to
find a way to form the diffusion layer.
[0014] Silicon has a density of about 5.times.10.sup.22
atoms/cm.sup.3. Accordingly, for narrow silicon pillars, it is
difficult to make impurities be present within the silicon
pillars.
[0015] Regarding existing SGTs, it has been proposed that, while
the channel concentration is set to a low impurity concentration of
10.sup.17 cm.sup.-3 or less, the work function of the gate material
is changed to adjust the threshold voltage (for example, refer to
Japanese Unexamined Patent Application Publication No. 2004-356314
and US 2004/0262681 A1).
[0016] A planar MOS transistor has been disclosed in which a
sidewall on an LDD region is formed of a polycrystalline silicon of
the same conductivity type as that of the lightly doped layer and
the surface carriers of the LDD region are induced by the
work-function difference between the sidewall and the LDD region,
so that the impedance of the LDD region can be reduced, compared
with oxide film sidewall LDD MOS transistors (for example, refer to
Japanese Unexamined Patent Application Publication No. 11-297984).
This publication states that the polycrystalline silicon sidewall
is electrically insulated from the gate electrode. That publication
also shows that, in a drawing, the polycrystalline silicon sidewall
and the source-drain are insulated from each other with an
interlayer insulating film.
SUMMARY OF THE INVENTION
[0017] In order to address the above-described problems, the
present invention has been accomplished. An object of the present
invention is to provide a memory structure that allows a large
current to pass through a selected transistor and includes a
variable-resistance memory element, and a method for producing the
memory structure.
[0018] With the above and other objects in view there is provided,
in accordance with a first embodiment of the invention, a
semiconductor device which includes:
[0019] a first pillar-shaped semiconductor layer,
[0020] a first gate insulating film formed around the first
pillar-shaped semiconductor layer,
[0021] a gate electrode formed of metal and formed around the first
gate insulating film,
[0022] a gate line formed of metal and connected to the gate
electrode,
[0023] a second gate insulating film formed around an upper portion
of the first pillar-shaped semiconductor layer,
[0024] a first contact formed of a first metal material and formed
around the second gate insulating film,
[0025] a second contact formed of a second metal material and
connecting an upper portion of the first contact and an upper
portion of the first pillar-shaped semiconductor layer,
[0026] a second diffusion layer formed in a lower portion of the
first pillar-shaped semiconductor layer, and
[0027] a variable-resistance memory element formed on the second
contact.
[0028] The first metal material forming the first contact
preferably has a work function of 4.0 to 4.2 eV.
[0029] The first metal material forming the first contact
preferably has a work function of 5.0 to 5.2 eV.
[0030] The semiconductor device preferably further includes:
[0031] a fin-shaped semiconductor layer formed on a semiconductor
substrate so as to extend in one direction,
[0032] a first insulating film formed around the fin-shaped
semiconductor layer,
[0033] the first pillar-shaped semiconductor layer formed on the
fin-shaped semiconductor layer, and
[0034] the first gate insulating film formed around and below the
gate electrode and the gate line,
[0035] wherein the gate line extends in a direction orthogonal to
the fin-shaped semiconductor layer, and
[0036] the second diffusion layer is formed in the fin-shaped
semiconductor layer.
[0037] The second diffusion layer formed in the fin-shaped
semiconductor layer is preferably further formed in the
semiconductor substrate.
[0038] The semiconductor device preferably further includes a
contact line extending parallel with the gate line and connected to
the second diffusion layer.
[0039] The semiconductor device preferably further includes
[0040] the fin-shaped semiconductor layer formed on the
semiconductor substrate,
[0041] the first insulating film formed around the fin-shaped
semiconductor layer,
[0042] a second pillar-shaped semiconductor layer formed on the
fin-shaped semiconductor layer,
[0043] a contact electrode formed of metal and formed around the
second pillar-shaped semiconductor layer,
[0044] the contact line formed of metal, extending in a direction
orthogonal to the fin-shaped semiconductor layer, and connected to
the contact electrode, and
[0045] the second diffusion layer formed in the fin-shaped
semiconductor layer and in a lower portion of the second
pillar-shaped semiconductor layer,
[0046] wherein the contact electrode is connected to the second
diffusion layer.
[0047] Preferably, an outer linewidth of the gate electrode is
equal to a linewidth of the gate line, and a linewidth of the first
pillar-shaped semiconductor layer in the direction orthogonal to
the fin-shaped semiconductor layer is equal to a linewidth of the
fin-shaped semiconductor layer in the direction orthogonal to the
fin-shaped semiconductor layer.
[0048] A portion of the first gate insulating film is preferably
formed between the second pillar-shaped semiconductor layer and the
contact electrode.
[0049] A linewidth of the second pillar-shaped semiconductor layer
extending in the direction orthogonal to the fin-shaped
semiconductor layer is preferably equal to a linewidth of the
fin-shaped semiconductor layer in a direction orthogonal to a
direction in which the fin-shaped semiconductor layer extends.
[0050] A portion of the first gate insulating film is preferably
formed around the contact electrode and around the contact
line.
[0051] An outer linewidth of the contact electrode is preferably
equal to a linewidth of the contact line.
[0052] The semiconductor device preferably further includes
[0053] the first pillar-shaped semiconductor layer formed on a
semiconductor substrate, and
[0054] the first gate insulating film formed around and below the
gate electrode and the gate line,
[0055] wherein the second diffusion layer is formed in the
semiconductor substrate.
[0056] The semiconductor device preferably further includes a
contact line extending parallel with the gate line and connected to
the second diffusion layer.
[0057] The semiconductor device preferably further includes
[0058] a second pillar-shaped semiconductor layer formed on the
semiconductor substrate,
[0059] a contact electrode formed of metal and formed around the
second pillar-shaped semiconductor layer,
[0060] a contact line connected to the contact electrode, and
[0061] the second diffusion layer formed in a lower portion of the
second pillar-shaped semiconductor layer,
[0062] wherein the contact electrode is connected to the second
diffusion layer.
[0063] An outer linewidth of the gate electrode is preferably equal
to a linewidth of the gate line.
[0064] A portion of the first gate insulating film is preferably
formed between the second pillar-shaped semiconductor layer and the
contact electrode.
[0065] A portion of the first gate insulating film is preferably
formed around the contact electrode and around the contact
line.
[0066] An outer linewidth of the contact electrode is preferably
equal to a linewidth of the contact line.
[0067] With the above and other objects in view there is also
provided, in accordance with the invention, a method for producing
a semiconductor device according to a second aspect of the present
invention includes
[0068] a first step of forming a fin-shaped semiconductor layer on
a semiconductor substrate so as to extend in one direction and
forming a first insulating film around the fin-shaped semiconductor
layer,
[0069] a second step of, after the first step, forming a first
pillar-shaped semiconductor layer, a first dummy gate derived from
a first polysilicon, a second pillar-shaped semiconductor layer,
and a second dummy gate derived from the first polysilicon,
[0070] a third step of, after the second step, forming a third
dummy gate and a fourth dummy gate on side walls of the first dummy
gate, the first pillar-shaped semiconductor layer, the second dummy
gate, and the second pillar-shaped semiconductor layer,
[0071] a fourth step of, after the third step, forming a second
diffusion layer in an upper portion of the fin-shaped semiconductor
layer, in a lower portion of the first pillar-shaped semiconductor
layer, and in a lower portion of the second pillar-shaped
semiconductor layer,
[0072] a fifth step of, after the fourth step, depositing a first
interlayer insulating film and performing chemical mechanical
polishing to expose upper portions of the first dummy gate, the
second dummy gate, the third dummy gate, and the fourth dummy gate,
removing the first dummy gate, the second dummy gate, the third
dummy gate, and the fourth dummy gate, forming a first gate
insulating film around the first pillar-shaped semiconductor layer
and around the second pillar-shaped semiconductor layer, removing
the first gate insulating film from around a bottom portion of the
second pillar-shaped semiconductor layer, depositing a first metal
layer and performing etch back to expose an upper portion of the
first pillar-shaped semiconductor layer and an upper portion of the
second pillar-shaped semiconductor layer, to form a gate electrode
and a gate line around the first pillar-shaped semiconductor layer,
and to form a contact electrode and a contact line around the
second pillar-shaped semiconductor layer,
[0073] a sixth step of, after the fifth step, depositing a second
gate insulating film around the first pillar-shaped semiconductor
layer, on the gate electrode and the gate line, around the second
pillar-shaped semiconductor layer, and on the contact electrode and
the contact line, depositing a second metal layer and performing
etch back to expose an upper portion of the first pillar-shaped
semiconductor layer and an upper portion of the second
pillar-shaped semiconductor layer, removing the second gate
insulating film on the first pillar-shaped semiconductor layer,
depositing a third metal layer, partially etching the third metal
layer and the second metal layer to form, from the second metal
layer, a first contact surrounding an upper side wall of the first
pillar-shaped semiconductor layer and to form, from the third metal
layer, a second contact connecting an upper portion of the first
contact and an upper portion of the first pillar-shaped
semiconductor layer, and
[0074] a seventh step of, after the sixth step, depositing a second
interlayer insulating film, performing planarization to expose an
upper portion of the second contact, and
[0075] forming a variable-resistance memory element on the second
contact.
[0076] Preferably, in the second step,
[0077] a second insulating film is formed around the fin-shaped
semiconductor layer,
[0078] the first polysilicon is deposited on the second insulating
film and planarized,
[0079] a second resist for forming the gate line, the first
pillar-shaped semiconductor layer, the contact line, and the second
pillar-shaped semiconductor layer is formed in a direction
orthogonal to a direction in which the fin-shaped semiconductor
layer extends,
[0080] the second resist is used as a mask and the first
polysilicon, the second insulating film, and the fin-shaped
semiconductor layer are etched to form the first pillar-shaped
semiconductor layer, the first dummy gate derived from the first
polysilicon, the second pillar-shaped semiconductor layer, and the
second dummy gate derived from the first polysilicon.
[0081] After the first polysilicon is deposited on the second
insulating film and planarized, a third insulating film is
preferably formed on the first polysilicon.
[0082] The method for producing a semiconductor device preferably
includes, as the third step, forming a fourth insulating film
around the first pillar-shaped semiconductor layer, the second
pillar-shaped semiconductor layer, the first dummy gate, and the
second dummy gate, depositing a second polysilicon around the
fourth insulating film and etching the second polysilicon so as to
remain on side walls of the first dummy gate, the first
pillar-shaped semiconductor layer, the second dummy gate, and the
second pillar-shaped semiconductor layer to form the third dummy
gate and the fourth dummy gate.
[0083] The method for producing a semiconductor device preferably
includes, as the fourth step, forming the second diffusion layer in
an upper portion of the fin-shaped semiconductor layer, in a lower
portion of the first pillar-shaped semiconductor layer, and in a
lower portion of the second pillar-shaped semiconductor layer,
forming a fifth insulating film around the third dummy gate and the
fourth dummy gate and etching the fifth insulating film so as to
have a sidewall shape to form sidewalls derived from the fifth
insulating film, and forming a compound layer formed of metal and
semiconductor on the second diffusion layer.
[0084] The method for producing a semiconductor device preferably
includes, as the fifth step, depositing the first interlayer
insulating film and performing chemical mechanical polishing to
expose upper portions of the first dummy gate, the second dummy
gate, the third dummy gate, and the fourth dummy gate, removing the
first dummy gate, the second dummy gate, the third dummy gate, and
the fourth dummy gate, removing the second insulating film and the
fourth insulating film, forming the first gate insulating film
around the first pillar-shaped semiconductor layer, around the
second pillar-shaped semiconductor layer, and on inner sides of the
fifth insulating film, forming a third resist for removing the
first gate insulating film from around a bottom portion of the
second pillar-shaped semiconductor layer, removing the first gate
insulating film from around the bottom portion of the second
pillar-shaped semiconductor layer, depositing a metal layer, and
performing etch back to expose an upper portion of the first
pillar-shaped semiconductor layer and an upper portion of the
second pillar-shaped semiconductor layer, to form the gate
electrode and the gate line around the first pillar-shaped
semiconductor layer and to form the contact electrode and the
contact line around the second pillar-shaped semiconductor
layer.
[0085] The present invention can provide a memory structure that
allows a large current to pass through a selected transistor and
includes a variable-resistance memory element.
BRIEF DESCRIPTION OF THE DRAWINGS
[0086] FIG. 1A is a plan view of a semiconductor device according
to an embodiment of the present invention; FIG. 1B is a sectional
view taken along line X-X' in FIG. 1A; and FIG. 1C is a sectional
view taken along line Y-Y' in FIG. 1A.
[0087] FIG. 2A is a plan view of a semiconductor device according
to an embodiment of the present invention; FIG. 2B is a sectional
view taken along line X-X' in FIG. 2A; and FIG. 2C is a sectional
view taken along line Y-Y' in FIG. 2A.
[0088] FIG. 3A is a plan view of a semiconductor device according
to an embodiment of the present invention; FIG. 3B is a sectional
view taken along line X-X' in FIG. 3A; and FIG. 3C is a sectional
view taken along line Y-Y' in FIG. 3A.
[0089] FIG. 4A is a plan view relating to a method for producing a
semiconductor device according to an embodiment of the present
invention; FIG. 4B is a sectional view taken along line X-X' in
FIG. 4A; and FIG. 4C is a sectional view taken along line Y-Y' in
FIG. 4A.
[0090] FIG. 5A is a plan view relating to a method for producing a
semiconductor device according to an embodiment of the present
invention; FIG. 5B is a sectional view taken along line X-X' in
FIG. 5A; and FIG. 5C is a sectional view taken along line Y-Y' in
FIG. 5A.
[0091] FIG. 6A is a plan view relating to a method for producing a
semiconductor device according to an embodiment of the present
invention; FIG. 6B is a sectional view taken along line X-X' in
FIG. 6A; and FIG. 6C is a sectional view taken along line Y-Y' in
FIG. 6A.
[0092] FIG. 7A is a plan view relating to a method for producing a
semiconductor device according to an embodiment of the present
invention; FIG. 7B is a sectional view taken along line X-X' in
FIG. 7A; and FIG. 7C is a sectional view taken along line Y-Y' in
FIG. 7A.
[0093] FIG. 8A is a plan view relating to a method for producing a
semiconductor device according to an embodiment of the present
invention; FIG. 8B is a sectional view taken along line X-X' in
FIG. 8A; and FIG. 8C is a sectional view taken along line Y-Y' in
FIG. 8A.
[0094] FIG. 9A is a plan view relating to a method for producing a
semiconductor device according to an embodiment of the present
invention; FIG. 9B is a sectional view taken along line X-X' in
FIG. 9A; and FIG. 9C is a sectional view taken along line Y-Y' in
FIG. 9A.
[0095] FIG. 10A is a plan view relating to a method for producing a
semiconductor device according to an embodiment of the present
invention; FIG. 10B is a sectional view taken along line X-X' in
FIG. 10A; and FIG. 10C is a sectional view taken along line Y-Y' in
FIG. 10A.
[0096] FIG. 11A is a plan view relating to a method for producing a
semiconductor device according to an embodiment of the present
invention; FIG. 11B is a sectional view taken along line X-X' in
FIG. 11A; and FIG. 11C is a sectional view taken along line Y-Y' in
FIG. 11A.
[0097] FIG. 12A is a plan view relating to a method for producing a
semiconductor device according to an embodiment of the present
invention; FIG. 12B is a sectional view taken along line X-X' in
FIG. 12A; and FIG. 12C is a sectional view taken along line Y-Y' in
FIG. 12A.
[0098] FIG. 13A is a plan view relating to a method for producing a
semiconductor device according to an embodiment of the present
invention; FIG. 13B is a sectional view taken along line X-X' in
FIG. 13A; and FIG. 13C is a sectional view taken along line Y-Y' in
FIG. 13A.
[0099] FIG. 14A is a plan view relating to a method for producing a
semiconductor device according to an embodiment of the present
invention; FIG. 14B is a sectional view taken along line X-X' in
FIG. 14A; and FIG. 14C is a sectional view taken along line Y-Y' in
FIG. 14A.
[0100] FIG. 15A is a plan view relating to a method for producing a
semiconductor device according to an embodiment of the present
invention; FIG. 15B is a sectional view taken along line X-X' in
FIG. 15A; and FIG. 15C is a sectional view taken along line Y-Y' in
FIG. 15A.
[0101] FIG. 16A is a plan view relating to a method for producing a
semiconductor device according to an embodiment of the present
invention; FIG. 16B is a sectional view taken along line X-X' in
FIG. 16A; and FIG. 16C is a sectional view taken along line Y-Y' in
FIG. 16A.
[0102] FIG. 17A is a plan view relating to a method for producing a
semiconductor device according to an embodiment of the present
invention; FIG. 17B is a sectional view taken along line X-X' in
FIG. 17A; and FIG. 17C is a sectional view taken along line Y-Y' in
FIG. 17A.
[0103] FIG. 18A is a plan view relating to a method for producing a
semiconductor device according to an embodiment of the present
invention; FIG. 18B is a sectional view taken along line X-X' in
FIG. 18A; and FIG. 18C is a sectional view taken along line Y-Y' in
FIG. 18A.
[0104] FIG. 19A is a plan view relating to a method for producing a
semiconductor device according to an embodiment of the present
invention; FIG. 19B is a sectional view taken along line X-X' in
FIG. 19A; and FIG. 19C is a sectional view taken along line Y-Y' in
FIG. 19A.
[0105] FIG. 20A is a plan view relating to a method for producing a
semiconductor device according to an embodiment of the present
invention; FIG. 20B is a sectional view taken along line X-X' in
FIG. 20A; and FIG. 20C is a sectional view taken along line Y-Y' in
FIG. 20A.
[0106] FIG. 21A is a plan view relating to a method for producing a
semiconductor device according to an embodiment of the present
invention; FIG. 21B is a sectional view taken along line X-X' in
FIG. 21A; and FIG. 21C is a sectional view taken along line Y-Y' in
FIG. 21A.
[0107] FIG. 22A is a plan view relating to a method for producing a
semiconductor device according to an embodiment of the present
invention; FIG. 22B is a sectional view taken along line X-X' in
FIG. 22A; and FIG. 22C is a sectional view taken along line Y-Y' in
FIG. 22A.
[0108] FIG. 23A is a plan view relating to a method for producing a
semiconductor device according to an embodiment of the present
invention; FIG. 23B is a sectional view taken along line X-X' in
FIG. 23A; and FIG. 23C is a sectional view taken along line Y-Y' in
FIG. 23A.
[0109] FIG. 24A is a plan view relating to a method for producing a
semiconductor device according to an embodiment of the present
invention; FIG. 24B is a sectional view taken along line X-X' in
FIG. 24A; and FIG. 24C is a sectional view taken along line Y-Y' in
FIG. 24A.
[0110] FIG. 25A is a plan view relating to a method for producing a
semiconductor device according to an embodiment of the present
invention; FIG. 25B is a sectional view taken along line X-X' in
FIG. 25A; and FIG. 25C is a sectional view taken along line Y-Y' in
FIG. 25A.
[0111] FIG. 26A is a plan view relating to a method for producing a
semiconductor device according to an embodiment of the present
invention; FIG. 26B is a sectional view taken along line X-X' in
FIG. 26A; and FIG. 26C is a sectional view taken along line Y-Y' in
FIG. 26A.
[0112] FIG. 27A is a plan view relating to a method for producing a
semiconductor device according to an embodiment of the present
invention; FIG. 27B is a sectional view taken along line X-X' in
FIG. 27A; and FIG. 27C is a sectional view taken along line Y-Y' in
FIG. 27A.
[0113] FIG. 28A is a plan view relating to a method for producing a
semiconductor device according to an embodiment of the present
invention; FIG. 28B is a sectional view taken along line X-X' in
FIG. 28A; and FIG. 28C is a sectional view taken along line Y-Y' in
FIG. 28A.
[0114] FIG. 29A is a plan view relating to a method for producing a
semiconductor device according to an embodiment of the present
invention; FIG. 29B is a sectional view taken along line X-X' in
FIG. 29A; and FIG. 29C is a sectional view taken along line Y-Y' in
FIG. 29A.
[0115] FIG. 30A is a plan view relating to a method for producing a
semiconductor device according to an embodiment of the present
invention; FIG. 30B is a sectional view taken along line X-X' in
FIG. 30A; and FIG. 30C is a sectional view taken along line Y-Y' in
FIG. 30A.
[0116] FIG. 31A is a plan view relating to a method for producing a
semiconductor device according to an embodiment of the present
invention; FIG. 31B is a sectional view taken along line X-X' in
FIG. 31A; and FIG. 31C is a sectional view taken along line Y-Y' in
FIG. 31A.
[0117] FIG. 32A is a plan view relating to a method for producing a
semiconductor device according to an embodiment of the present
invention; FIG. 32B is a sectional view taken along line X-X' in
FIG. 32A; and FIG. 32C is a sectional view taken along line Y-Y' in
FIG. 32A.
[0118] FIG. 33A is a plan view relating to a method for producing a
semiconductor device according to an embodiment of the present
invention; FIG. 33B is a sectional view taken along line X-X' in
FIG. 33A; and FIG. 33C is a sectional view taken along line Y-Y' in
FIG. 33A.
[0119] FIG. 34A is a plan view relating to a method for producing a
semiconductor device according to an embodiment of the present
invention; FIG. 34B is a sectional view taken along line X-X' in
FIG. 34A; and FIG. 34C is a sectional view taken along line Y-Y' in
FIG. 34A.
[0120] FIG. 35A is a plan view relating to a method for producing a
semiconductor device according to an embodiment of the present
invention; FIG. 35B is a sectional view taken along line X-X' in
FIG. 35A; and FIG. 35C is a sectional view taken along line Y-Y' in
FIG. 35A.
[0121] FIG. 36A is a plan view relating to a method for producing a
semiconductor device according to an embodiment of the present
invention; FIG. 36B is a sectional view taken along line X-X' in
FIG. 36A; and FIG. 36C is a sectional view taken along line Y-Y' in
FIG. 36A.
[0122] FIG. 37A is a plan view relating to a method for producing a
semiconductor device according to an embodiment of the present
invention; FIG. 37B is a sectional view taken along line X-X' in
FIG. 37A; and FIG. 37C is a sectional view taken along line Y-Y' in
FIG. 37A.
[0123] FIG. 38A is a plan view relating to a method for producing a
semiconductor device according to an embodiment of the present
invention; FIG. 38B is a sectional view taken along line X-X' in
FIG. 38A; and FIG. 38C is a sectional view taken along line Y-Y' in
FIG. 38A.
[0124] FIG. 39A is a plan view relating to a method for producing a
semiconductor device according to an embodiment of the present
invention; FIG. 39B is a sectional view taken along line X-X' in
FIG. 39A; and FIG. 39C is a sectional view taken along line Y-Y' in
FIG. 39A.
[0125] FIG. 40A is a plan view relating to a method for producing a
semiconductor device according to an embodiment of the present
invention; FIG. 40B is a sectional view taken along line X-X' in
FIG. 40A; and FIG. 40C is a sectional view taken along line Y-Y' in
FIG. 40A.
[0126] FIG. 41A is a plan view relating to a method for producing a
semiconductor device according to an embodiment of the present
invention; FIG. 41B is a sectional view taken along line X-X' in
FIG. 41A; and FIG. 41C is a sectional view taken along line Y-Y' in
FIG. 41A.
[0127] FIG. 42A is a plan view relating to a method for producing a
semiconductor device according to an embodiment of the present
invention; FIG. 42B is a sectional view taken along line X-X' in
FIG. 42A; and FIG. 42C is a sectional view taken along line Y-Y' in
FIG. 42A.
[0128] FIG. 43A is a plan view relating to a method for producing a
semiconductor device according to an embodiment of the present
invention; FIG. 43B is a sectional view taken along line X-X' in
FIG. 43A; and FIG. 43C is a sectional view taken along line Y-Y' in
FIG. 43A.
[0129] FIG. 44A is a plan view relating to a method for producing a
semiconductor device according to an embodiment of the present
invention; FIG. 44B is a sectional view taken along line X-X' in
FIG. 44A; and FIG. 44C is a sectional view taken along line Y-Y' in
FIG. 44A.
[0130] FIG. 45A is a plan view relating to a method for producing a
semiconductor device according to an embodiment of the present
invention; FIG. 45B is a sectional view taken along line X-X' in
FIG. 45A; and FIG. 45C is a sectional view taken along line Y-Y' in
FIG. 45A.
[0131] FIG. 46A is a plan view relating to a method for producing a
semiconductor device according to an embodiment of the present
invention; FIG. 46B is a sectional view taken along line X-X' in
FIG. 46A; and FIG. 46C is a sectional view taken along line Y-Y' in
FIG. 46A.
[0132] FIG. 47A is a plan view relating to a method for producing a
semiconductor device according to an embodiment of the present
invention; FIG. 47B is a sectional view taken along line X-X' in
FIG. 47A; and FIG. 47C is a sectional view taken along line Y-Y' in
FIG. 47A.
[0133] FIG. 48A is a plan view relating to a method for producing a
semiconductor device according to an embodiment of the present
invention; FIG. 48B is a sectional view taken along line X-X' in
FIG. 48A; and FIG. 48C is a sectional view taken along line Y-Y' in
FIG. 48A.
[0134] FIG. 49A is a plan view relating to a method for producing a
semiconductor device according to an embodiment of the present
invention; FIG. 49B is a sectional view taken along line X-X' in
FIG. 49A; and FIG. 49C is a sectional view taken along line Y-Y' in
FIG. 49A.
[0135] FIG. 50A is a plan view relating to a method for producing a
semiconductor device according to an embodiment of the present
invention; FIG. 50B is a sectional view taken along line X-X' in
FIG. 50A; and FIG. 50C is a sectional view taken along line Y-Y' in
FIG. 50A.
[0136] FIG. 51A is a plan view relating to a method for producing a
semiconductor device according to an embodiment of the present
invention; FIG. 51B is a sectional view taken along line X-X' in
FIG. 51A; and FIG. 51C is a sectional view taken along line Y-Y' in
FIG. 51A.
[0137] FIG. 52A is a plan view relating to a method for producing a
semiconductor device according to an embodiment of the present
invention; FIG. 52B is a sectional view taken along line X-X' in
FIG. 52A; and FIG. 52C is a sectional view taken along line Y-Y' in
FIG. 52A.
[0138] FIG. 53A is a plan view relating to a method for producing a
semiconductor device according to an embodiment of the present
invention; FIG. 53B is a sectional view taken along line X-X' in
FIG. 53A; and FIG. 53C is a sectional view taken along line Y-Y' in
FIG. 53A.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0139] Referring now to the figures of the drawing in detail and
first, particularly, to FIGS. 1A to 1C thereof, there is shown the
structure of a semiconductor device according to an exemplary
embodiment of the present invention.
[0140] As illustrated in FIGS. 1A to 1C, in the 3.times.2 matrix
cell arrangement, memory cells according to the embodiment are
disposed in the first row and the first column, in the first row
and the third column, in the second row and the first column, and
in the second row and the third column. In the 3.times.2 matrix
cell arrangement, contact devices that have a contact electrode and
a contact line for connecting source lines to each other are
disposed in the first row and the second column and in the second
row and the second column.
[0141] The memory cell that is positioned in the second row and the
first column includes a fin-shaped silicon layer 104 formed on a
semiconductor substrate 101 so as to extend in the horizontal
direction, a first insulating film 106 formed around the fin-shaped
silicon layer 104, a first pillar-shaped silicon layer 129 formed
on the fin-shaped silicon layer 104, a gate insulating film 162
formed around the first pillar-shaped silicon layer 129, a gate
electrode 168a formed of metal and formed around the gate
insulating film 162, and a gate line 168b formed of metal and
connected to the gate electrode 168a. The gate line 168b extends in
a direction orthogonal to the fin-shaped silicon layer 104.
[0142] The memory cell that is positioned in the second row and the
first column further includes the gate electrode 168a, a gate
insulating film 162 formed around and below the gate electrode 168a
and the gate line 168b, a gate insulating film 173 formed around an
upper portion of the first pillar-shaped silicon layer 129, a first
contact 179a formed of a first metal material and formed around the
gate insulating film 173, a second contact 183a formed of a second
metal material and connecting an upper portion of the first contact
179a and an upper portion of the first pillar-shaped silicon layer
129, a second diffusion layer 143a formed in a lower portion of the
first pillar-shaped silicon layer 129, and a variable-resistance
memory element 201a formed on the second contact 183a. The second
diffusion layer 143a is formed in the fin-shaped silicon layer 104.
A heater 199a that is a high-resistance element is formed between
the variable-resistance memory element 201a and the second contact
183a.
[0143] The variable-resistance memory element 201a is preferably
constituted by a phase-change film formed of chalcogenide glass
(GST: Ge.sub.2Sb.sub.2Te.sub.5), for example. The heater 199a is
preferably formed of titanium nitride, for example.
[0144] The memory cell positioned in the second row and the third
column includes a fin-shaped silicon layer 104 formed on a
semiconductor substrate 101 so as to extend in the horizontal
direction, a first insulating film 106 formed around the fin-shaped
silicon layer 104, a first pillar-shaped silicon layer 131 formed
on the fin-shaped silicon layer 104, a gate insulating film 163
formed around the first pillar-shaped silicon layer 131, a gate
electrode 170a formed of metal and formed around the gate
insulating film 163, and a gate line 170b formed of metal and
connected to the gate electrode 170a. The gate line 170b extends in
a direction orthogonal to the fin-shaped silicon layer 104.
[0145] The memory cell positioned in the second row and the third
column further includes the gate electrode 170a, the gate
insulating film 163 formed around and below the gate line 170b, a
gate insulating film 174 formed around an upper portion of the
first pillar-shaped silicon layer 131, a first contact 181a formed
of a first metal material and formed around the gate insulating
film 174, a second contact 185a formed of a second metal material
and connecting an upper portion of the first contact 181a and an
upper portion of the first pillar-shaped silicon layer 131, a
second diffusion layer 143a formed in a lower portion of the first
pillar-shaped silicon layer 131, and a variable-resistance memory
element 202a formed on the second contact 185a. The second
diffusion layer 143a is formed in the fin-shaped silicon layer 104.
A heater 200a that is a high-resistance element is formed between
the variable-resistance memory element 202a and the second contact
185a.
[0146] The variable-resistance memory element 201a is connected to
the variable-resistance memory element 202a via a bit line 207.
[0147] The memory cell positioned in the first row and the first
column includes a fin-shaped silicon layer 105 formed on a
semiconductor substrate 101 so as to extend in the horizontal
direction, a first insulating film 106 formed around the fin-shaped
silicon layer 105, a first pillar-shaped silicon layer 132 formed
on the fin-shaped silicon layer 105, a gate insulating film 162
formed around the first pillar-shaped silicon layer 132, a gate
electrode 168a formed of metal and formed around the gate
insulating film 162, and a gate line 168b formed of metal and
connected to the gate electrode 168a. The gate line 168b extends in
a direction orthogonal to the fin-shaped silicon layer 105.
[0148] The memory cell positioned in the first row and the first
column further includes the gate electrode 168a, the gate
insulating film 162 formed around and below the gate line 168b, a
gate insulating film 173 formed around an upper portion of the
first pillar-shaped silicon layer 132, a first contact 179b formed
of a first metal material and formed around the gate insulating
film 173, a second contact 183b formed of a second metal material
and connecting an upper portion of the first contact 179b and an
upper portion of the first pillar-shaped silicon layer 132, a
second diffusion layer 143b formed in a lower portion of the first
pillar-shaped silicon layer 132, and a variable-resistance memory
element 201b formed on the second contact 183b. The second
diffusion layer 143b is formed in the fin-shaped silicon layer 105.
A heater 199b that is a high-resistance element is formed between
the variable-resistance memory element 201b and the second contact
183b.
[0149] The memory cell positioned in the first row and the third
column includes a fin-shaped silicon layer 105 formed on a
semiconductor substrate 101 so as to extend in the horizontal
direction, a first insulating film 106 formed around the fin-shaped
silicon layer 105, a first pillar-shaped silicon layer 134 formed
on the fin-shaped silicon layer 105, a gate insulating film 163
formed around the first pillar-shaped silicon layer 134, a gate
electrode 170a formed of metal and formed around the gate
insulating film 163, and a gate line 170b formed of metal and
connected to the gate electrode 170a. The gate line 170b extends in
a direction orthogonal to the fin-shaped silicon layer 105.
[0150] The memory cell positioned in the first row and the third
column further includes the gate electrode 170a, the gate
insulating film 163 formed around and below the gate line 170b, a
gate insulating film 174 formed around an upper portion of the
first pillar-shaped silicon layer 134, a first contact 181b formed
of a first metal material and formed around the gate insulating
film 174, a second contact 185b formed of a second metal material
and connecting an upper portion of the first contact 181b and an
upper portion of the first pillar-shaped silicon layer 134, a
second diffusion layer 143b formed in a lower portion of the first
pillar-shaped silicon layer 134, and a variable-resistance memory
element 202b formed on the second contact 185b. The second
diffusion layer 143b is formed in the fin-shaped silicon layer 105.
A heater 200b that is a high-resistance element is formed between
the variable-resistance memory element 202b and the second contact
185b.
[0151] The variable-resistance memory element 201b is connected to
the variable-resistance memory element 202b via a bit line 208.
[0152] SGTs allow a larger current per unit gate width to pass than
double-gate transistors. In addition, SGTs have a structure in
which the gate electrode surrounds the pillar-shaped semiconductor
layer. Thus, the gate width per unit area can be increased, so that
an even larger current can be passed. Thus, SGTs allow a large
reset current to pass, so that phase-change films such as the
variable-resistance memory elements 201a and 201b can be melted at
a high temperature (with a large current). For the subthreshold
swing (a gate voltage required to change by an order of magnitude a
drain-source current of a MOSFET that operates in a weak inversion
region) of SGTs, an ideal value can be achieved. Accordingly, off
current can be decreased, so that phase-change films such as the
variable-resistance memory elements 201a and 201b can be rapidly
cooled (by stopping the current).
[0153] The gate electrodes 168a and 170a are formed of metal. The
gate lines 168b and 170b are formed of metal. Furthermore, the
first contacts 179a, 179b, 181a, and 181b formed around the gate
insulating films 173 and 174 and formed of a first metal material,
and the second contacts 183a, 183b, 185a, and 185b connecting upper
portions of the first contacts 179a, 179b, 181a, and 181b and upper
portions of the first pillar-shaped silicon layers 129, 131, 132,
and 134 and formed of a second metal material, are also formed of
metal. Thus, a large amount of metal is used so that the heat
dissipation effect of the metal can promote cooling of portions
heated by a large reset current. In addition, a semiconductor
device according to this embodiment includes the gate electrodes
168a and 170a and the gate insulating films 162 and 163 formed
around and below the gate electrodes 168a and 170a and the gate
lines 168b and 170b. Accordingly, a gate last process of forming
metal gates at the final stage of the heat-treatment step is
carried out to form the gate electrodes 168a and 170a that are
metal gates. Thus, both of the metal gate process and the
high-temperature process can be successfully performed.
[0154] The gate insulating films 162 and 163 are formed around and
below the gate electrodes 168a and 170a and the gate lines 168b and
170b. The gate electrodes 168a and 170a and the gate lines 168b and
170b are formed of metal. The gate lines 168b and 170b extend in a
direction orthogonal to the fin-shaped silicon layers 104 and 105.
The second diffusion layers 143a and 143b are formed in the
fin-shaped silicon layers 104 and 105. The gate electrodes 168a and
170a have outer linewidths equal to the linewidths of the gate
lines 168b and 170b. Also, the first pillar-shaped silicon layers
129, 131, 132, and 134 have linewidths equal to the linewidths of
the fin-shaped silicon layers 104 and 105. Accordingly, in the
semiconductor device according to this embodiment, the fin-shaped
silicon layers 104 and 105, the first pillar-shaped silicon layers
129, 131, 132, and 134, the gate electrodes 168a and 170a, and the
gate lines 168b and 170b are formed by self alignment with two
masks. As a result, according to the embodiment, the number of
steps required to produce the semiconductor device can be
reduced.
[0155] The contact device positioned in the second row and the
second column includes a fin-shaped silicon layer 104 formed on a
semiconductor substrate 101 so as to extend in the horizontal
direction, a first insulating film 106 formed around the fin-shaped
silicon layer 104, and a second pillar-shaped silicon layer 130
formed on the fin-shaped silicon layer 104. A linewidth of the
second pillar-shaped silicon layer 130 in a direction orthogonal to
the fin-shaped silicon layer 104 is equal to a linewidth of the
fin-shaped silicon layer 104 in the direction orthogonal to the
fin-shaped silicon layer 104.
[0156] The contact device positioned in the second row and the
second column further includes a contact electrode 169a formed of
metal and formed around the second pillar-shaped silicon layer 130,
a gate insulating film 165 formed between the second pillar-shaped
silicon layer 130 and the contact electrode 169a, a contact line
169b formed of metal, extending in a direction orthogonal to the
fin-shaped silicon layer 104, and connected to the contact
electrode 169a, and a gate insulating film 164 formed around the
contact electrode 169a and the contact line 169b. The outer
linewidth of the contact electrode 169a is equal to the linewidth
of the contact line 169b. A second diffusion layer 143a is formed
in the fin-shaped silicon layer 104 and in a lower portion of the
second pillar-shaped silicon layer 130. The contact electrode 169a
is electrically connected to the second diffusion layer 143a.
[0157] The contact device positioned in the second row and the
second column further includes a gate insulating film 175 formed
around an upper portion of the second pillar-shaped silicon layer
130, a third contact 180a formed of a first metal material and
formed around the gate insulating film 175, and a fourth contact
184a formed of a second metal material and connecting an upper
portion of the third contact 180a and an upper portion of the
second pillar-shaped silicon layer 130. The third contact 180a is
electrically connected to the contact electrode 169a.
[0158] Thus, the second diffusion layer 143a, the contact electrode
169a, the contact line 169b, the third contact 180a, and the fourth
contact 184a are electrically interconnected.
[0159] The contact device positioned in the first row and the
second column includes a fin-shaped silicon layer 105 formed on a
semiconductor substrate 101 so as to extend in the horizontal
direction, a first insulating film 106 formed around the fin-shaped
silicon layer 105, and a second pillar-shaped silicon layer 133
formed on the fin-shaped silicon layer 105. A linewidth of the
second pillar-shaped silicon layer 133 in a direction orthogonal to
the fin-shaped silicon layer 105 is equal to a linewidth of the
fin-shaped silicon layer 105 in the direction orthogonal to the
fin-shaped silicon layer 105.
[0160] The contact device positioned in the first row and the
second column further includes a contact electrode 169a formed of
metal and formed around the second pillar-shaped silicon layer 133,
a gate insulating film 166 formed between the second pillar-shaped
silicon layer 133 and the contact electrode 169a, a contact line
169b formed of metal, extending in a direction orthogonal to the
fin-shaped silicon layer 105, and connected to the contact
electrode 169a, a gate insulating film 164 formed around the
contact electrode 169a and the contact line 169b, and a second
diffusion layer 143b in the fin-shaped silicon layer 105 and in a
lower portion of the second pillar-shaped silicon layer 133. The
outer linewidth of the contact electrode 169a is equal to the
linewidth of the contact line 169b. The contact electrode 169a is
electrically connected to the second diffusion layer 143b.
[0161] The contact device positioned in the first row and the
second column further includes a gate insulating film 176 formed
around an upper portion of the second pillar-shaped silicon layer
133, a third contact 180b formed around the gate insulating film
176 and formed of a first metal material, and a fourth contact 184b
connecting an upper portion of the third contact 180b and an upper
portion of the second pillar-shaped silicon layer 133 and formed of
a second metal material. The third contact 180b is electrically
connected to the contact electrode 169a.
[0162] Thus, the second diffusion layer 143b, the contact electrode
169a, the contact line 169b, the third contact 180b, and the fourth
contact 184b are electrically interconnected.
[0163] The semiconductor device according to this embodiment
includes the contact line 169b extending parallel with the gate
lines 168b and 170b and connected to the second diffusion layers
143a and 143b. Thus, the second diffusion layers 143a and 143b are
connected to each other and the resistance of the source lines can
be decreased. As a result, a large reset current can be passed
through the source lines. The contact line 169b extending parallel
with the gate lines 168b and 170b is preferably disposed such that,
for example, a single contact line 169b is disposed every 2, 4, 8,
16, 32, or 64 memory cells arranged in a line in the direction in
which the bit lines 207 and 208 extend.
[0164] In this embodiment, the structure including the second
pillar-shaped silicon layers 130 and 133 and the contact electrode
169a and the contact line 169b formed around the second
pillar-shaped silicon layers 130 and 133, is the same as the
transistor structure of the memory cell positioned, for example, in
the first row and the first column except that the contact
electrode 169a is connected to the second diffusion layers 143a and
143b. All the source lines constituted by the second diffusion
layers 143a and 143b and extending parallel with the gate lines
168b and 170b are connected to the contact line 169b. As a result,
the number of steps required to produce the semiconductor device
can be reduced.
[0165] FIGS. 2A to 2C illustrate a semiconductor device that has a
structure in which, compared with the second diffusion layers 143a
and 143b in FIGS. 1A to 1C, a second diffusion layer 143c is formed
to a deep level in the semiconductor substrate 101 and is formed in
the fin-shaped silicon layers 104 and 105, and is connected in the
same manner as in the second diffusion layers 143a and 143b in
FIGS. 1A to 1C. This structure allows a further decrease in the
source resistance.
[0166] FIGS. 3A to 3C illustrate a semiconductor device that has a
structure in which the fin-shaped silicon layer 105 and the first
insulating film 106 formed around the fin-shaped silicon layer 105
in FIGS. 2A to 2C are not formed, and a second diffusion layer 143d
is directly formed in the semiconductor substrate 101. This
structure allows a further decrease in the source resistance.
[0167] Hereinafter, steps for producing a semiconductor device
according to an embodiment of the present invention will be
described with reference to FIGS. 4A to 53C.
[0168] First, a first step according to the embodiment will be
described. The first step includes forming fin-shaped silicon
layers 104 and 105 on a semiconductor substrate 101 and forming a
first insulating film 106 around the fin-shaped silicon layers 104
and 105. In this embodiment, a silicon substrate is used as the
semiconductor substrate 101. Alternatively, a substrate that is
formed of another semiconductor material may be used.
[0169] First, as illustrated in FIGS. 4A to 4C, first resists 102
and 103 for forming fin-shaped silicon layers 104 and 105 extending
in the horizontal direction on a silicon substrate 101 are
formed.
[0170] Subsequently, as illustrated in FIGS. 5A to 5C, the silicon
substrate 101 is etched to form the fin-shaped silicon layers 104
and 105. Here, the fin-shaped silicon layers 104 and 105 are formed
with the resists serving as masks. Alternatively, instead of the
resists, hard masks such as oxide films and nitride films may be
used.
[0171] Subsequently, as illustrated in FIGS. 6A to 6C, the first
resists 102 and 103 are removed.
[0172] Subsequently, as illustrated in FIGS. 7A to 7C, a first
insulating film 106 is deposited around the fin-shaped silicon
layers 104 and 105. The first insulating film 106 may be an oxide
film formed with high-density plasma or an oxide film formed by
low-pressure CVD (Chemical Vapor Deposition).
[0173] Subsequently, as illustrated in FIGS. 8A to 8C, the first
insulating film 106 is subjected to etch back to expose upper
portions of the fin-shaped silicon layers 104 and 105.
[0174] Thus, the first step according to the embodiment has been
described, the first step including forming fin-shaped silicon
layers 104 and 105 on a semiconductor substrate 101 and forming a
first insulating film 106 around the fin-shaped silicon layers 104
and 105.
[0175] Hereafter, a second step according to an embodiment of the
present invention will be described. In the second step, after the
first step, second insulating films 107 and 108 are formed around
the fin-shaped silicon layers 104 and 105, and a first polysilicon
109 is deposited on the second insulating films 107 and 108 and
planarized. Subsequently, second resists 111, 112, and 113 for
forming gate lines 168b and 170b, first pillar-shaped silicon
layers 129, 131, 132, and 134, a contact line 169b, and second
pillar-shaped silicon layers 130 and 133 are formed so as to extend
in a direction orthogonal to a direction in which the fin-shaped
silicon layers 104 and 105 extend. Subsequently, the first
polysilicon 109, the second insulating films 107 and 108, and the
fin-shaped silicon layers 104 and 105 are etched to form the first
pillar-shaped silicon layers 129, 131, 132, and 134, first dummy
gates 117 and 119 derived from the first polysilicon 109, the
second pillar-shaped silicon layers 130 and 133, and a second dummy
gate 118 derived from the first polysilicon 109.
[0176] First, as illustrated in FIGS. 9A to 9C, second insulating
films 107 and 108 are formed around the fin-shaped silicon layers
104 and 105 and on the semiconductor substrate 101 so as to extend
in the horizontal direction. The second insulating films 107 and
108 are preferably oxide films.
[0177] Subsequently, as illustrated in FIGS. 10A to 10C, a first
polysilicon 109 is deposited on the second insulating films 107 and
108 and planarized.
[0178] Subsequently, as illustrated in FIGS. 11A to 11C, a third
insulating film 110 is formed on the first polysilicon 109. The
third insulating film 110 is preferably a nitride film.
[0179] Subsequently, as illustrated in FIGS. 12A to 12C, second
resists 111, 112, and 113 for forming gate lines 168b and 170b,
first pillar-shaped silicon layers 129, 131, 132, and 134, second
pillar-shaped silicon layers 130 and 133, and a contact line 169b,
are formed in a direction orthogonal to a direction in which the
fin-shaped silicon layers 104 and 105 extend.
[0180] Subsequently, as illustrated in FIGS. 13A to 13C, while the
second resists 111, 112, and 113 are used as masks, the third
insulating film 110, the first polysilicon 109, the second
insulating films 107 and 108, and the fin-shaped silicon layers 104
and 105 are etched to form the first pillar-shaped silicon layers
129, 131, 132, and 134, first dummy gates 117 and 119 derived from
the first polysilicon 109, the second pillar-shaped silicon layers
130 and 133, and a second dummy gate 118 derived from the first
polysilicon 109. Here, the third insulating film 110 is divided
into a plurality of portions to provide third insulating films 114,
115, and 116 on the first dummy gates 117 and 119 and the second
dummy gate 118. The second insulating films 107 and 108 are divided
into a plurality of portions to provide second insulating films
123, 124, 125, 126, 127, and 128. In a case where the second
resists 111, 112, and 113 are removed during this etching, the
third insulating films 114, 115, and 116 function as hard masks. On
the other hand, in a case where the second resists 111, 112, and
113 are not removed during the etching, it is not necessary to use
the third insulating films 114, 115, and 116 as masks.
[0181] Subsequently, as illustrated in FIGS. 14A to 14C, the second
resists 111, 112, and 113 are removed.
[0182] Thus, the second step has been described. In the second
step, after the first step, second insulating films 107 and 108 are
formed around the fin-shaped silicon layers 104 and 105, and a
first polysilicon 109 is deposited on the second insulating films
107 and 108 and planarized. Subsequently, second resists 111, 112,
and 113 for forming gate lines 168b and 170b, first pillar-shaped
silicon layers 129, 131, 132, and 134, a contact line 169b, and
second silicon layers 130 and 133 are formed so as to extend in a
direction orthogonal to a direction in which the fin-shaped silicon
layers 104 and 105 extend. Subsequently, the first polysilicon 109,
the second insulating films 107 and 108, and the fin-shaped silicon
layers 104 and 105 are etched to form the first pillar-shaped
silicon layers 129, 131, 132, and 134, first dummy gates 117 and
119 derived from the first polysilicon 109, the second
pillar-shaped silicon layers 130 and 133, and a second dummy gate
118 derived from the first polysilicon 109.
[0183] Hereafter, a third step according to an embodiment of the
present invention will be described. In the third step, after the
second step, a fourth insulating film 135 is formed around the
first pillar-shaped silicon layers 129, 131, 132, and 134, the
second pillar-shaped silicon layers 130 and 133, the first dummy
gates 117 and 119, and the second dummy gate 118. Subsequently, a
second polysilicon 136 is deposited around the fourth insulating
film 135 and etched such that the second polysilicon 136 remains on
side walls of the first dummy gates 117 and 119, the first
pillar-shaped silicon layers 129, 131, 132, and 134, the second
dummy gate 118, and the second pillar-shaped silicon layers 130 and
133 to form third dummy gates 137 and 139 and a fourth dummy gate
138.
[0184] Subsequently, as illustrated in FIGS. 15A to 15C, a fourth
insulating film 135 is formed around the first pillar-shaped
silicon layers 129, 131, 132, and 134, the second pillar-shaped
silicon layers 130 and 133, the first dummy gates 117 and 119, and
the second dummy gate 118. Subsequently, a second polysilicon 136
is deposited around the fourth insulating film 135.
[0185] Subsequently, as illustrated in FIGS. 16A to 16C, the second
polysilicon 136 is etched such that the second polysilicon 136
remains on side walls of the first dummy gates 117 and 119, the
first pillar-shaped silicon layers 129, 131, 132, and 134, the
second dummy gate 118, and the second pillar-shaped silicon layers
130 and 133. As a result, third dummy gates 137 and 139 and a
fourth dummy gate 138 are formed. At this time, the fourth
insulating film 135 may be divided into a plurality of portions to
provide fourth insulating films 140, 141, and 142.
[0186] Thus, the third step has been described. In the third step,
after the second step, a fourth insulating film 135 is formed
around the first pillar-shaped silicon layers 129, 131, 132, and
134, the second pillar-shaped silicon layers 130 and 133, the first
dummy gates 117 and 119, and the second dummy gate 118.
Subsequently, a second polysilicon 136 is deposited around the
fourth insulating film 135 and etched such that the second
polysilicon 136 remains on side walls of the first dummy gates 117
and 119, the first pillar-shaped silicon layers 129, 131, 132, and
134, the second dummy gate 118, and the second pillar-shaped
silicon layers 130 and 133 to form third dummy gates 137 and 139
and a fourth dummy gate 138.
[0187] Hereafter, a fourth step according to an embodiment of the
present invention will be described. In the fourth step, after the
third step, second diffusion layers 143a and 143b are formed in
upper portions of the fin-shaped silicon layers 104 and 105, lower
portions of the first pillar-shaped silicon layers 129, 131, 132,
and 134, and lower portions of the second pillar-shaped silicon
layers 130 and 133. Subsequently, a fifth insulating film 144 is
formed around the third dummy gates 137 and 139 and the fourth
dummy gate 138 and etched so as to have a sidewall shape to form
sidewalls 145, 146, and 147 derived from the fifth insulating film
144. Furthermore, compound layers 148, 149, 150, 151, 152, 153,
154, and 155 formed of metal and semiconductor are formed on the
second diffusion layers 143a and 143b.
[0188] First, as illustrated in FIGS. 17A to 17C, an impurity is
introduced to form second diffusion layers 143a and 143b in lower
portions of the first pillar-shaped silicon layers 129, 131, 132,
and 134 and lower portions of the second pillar-shaped silicon
layers 130 and 133. In a case where the impurity is introduced to
form n-type diffusion layers, arsenic or phosphorus is preferably
introduced. On the other hand, in a case where the impurity is
introduced to form p-type diffusion layers, boron is preferably
introduced. The diffusion layers may be formed after formation of
sidewalls 145, 146, and 147 derived from a fifth insulating film
144 described below.
[0189] Subsequently, as illustrated in FIGS. 18A to 18C, a fifth
insulating film 144 is formed around the third dummy gates 137 and
139 and the fourth dummy gate 138. The fifth insulating film 144 is
preferably a nitride film.
[0190] Subsequently, as illustrated in FIGS. 19A to 19C, the fifth
insulating film 144 is etched so as to have a sidewall shape. As a
result, sidewalls 145, 146, and 147 are formed from the fifth
insulating film 144.
[0191] Subsequently, as illustrated in FIGS. 20A to 20C, compound
layers 148, 149, 150, 151, 152, 153, 154, and 155 formed of metal
and semiconductor are formed on the second diffusion layers 143a
and 143b. At this time, compound layers 156, 158, and 157 formed of
metal and semiconductor are also formed in upper portions of the
third dummy gates 137 and 139 and an upper portion of the fourth
dummy gate 138.
[0192] Thus, the fourth step has been described. In the fourth
step, second diffusion layers 143a and 143b are formed in upper
portions of the fin-shaped silicon layers 104 and 105, lower
portions of the first pillar-shaped silicon layers 129, 131, 132,
and 134, and lower portions of the second pillar-shaped silicon
layers 130 and 133. Subsequently, a fifth insulating film 144 is
formed around the third dummy gates 137 and 139 and the fourth
dummy gate 138 and etched so as to have a sidewall shape to form
sidewalls 145, 146, and 147 derived from the fifth insulating film
144. Furthermore, compound layers 148, 149, 150, 151, 152, 153,
154, and 155 formed metal and semiconductor are formed on the
second diffusion layers 143a and 143b.
[0193] Hereafter, a fifth step according to an embodiment of the
present invention will be described. In the fifth step, after the
fourth step, a first interlayer insulating film 159 is deposited
and chemical mechanical polishing is performed to expose upper
portions of the first dummy gates 117 and 119, the second dummy
gate 118, the third dummy gates 137 and 139, and the fourth dummy
gate 138; and the first dummy gates 117 and 119, the second dummy
gate 118, the third dummy gates 137 and 139, and the fourth dummy
gate 138 are removed. Subsequently, the second insulating films
123, 124, 125, 126, 127, and 128 and the fourth insulating films
140, 141, and 142 are removed; and a gate insulating film 160 is
formed around the first pillar-shaped silicon layers 129, 131, 132,
and 134, around the second pillar-shaped silicon layers 130 and
133, and on inner sides of the fifth insulating film 144.
Subsequently, a third resist 161 for removing the gate insulating
film 160 from around the bottom portions of the second
pillar-shaped silicon layers 130 and 133 is formed; the gate
insulating film 160 is removed from around the bottom portions of
the second pillar-shaped silicon layers 130 and 133; and a metal
layer 167 is deposited. Subsequently, etch back is performed to
expose upper portions of the first pillar-shaped silicon layers
129, 131, 132, and 134 and upper portions of the second
pillar-shaped silicon layers 130 and 133, so that gate electrodes
168a and 170a and gate lines 168b and 170b are formed around the
first pillar-shaped silicon layers 129, 131, 132, and 134. After
that, a contact electrode 169a and a contact line 169b are formed
around the second pillar-shaped silicon layers 130 and 133.
[0194] First, as illustrated in FIGS. 21A to 21C, a first
interlayer insulating film 159 is deposited. Here, a contact
stopper film may be used.
[0195] Subsequently, as illustrated in FIGS. 22A to 22C, chemical
mechanical polishing (CMP) is performed to expose upper portions of
the first dummy gates 117 and 119, the second dummy gate 118, the
third dummy gates 137 and 139, and the fourth dummy gate 138. At
this time, the compound layers 156, 158, and 157 formed of metal
and semiconductor and formed in the upper portions of the third
dummy gates 137 and 139 and in the upper portion of the fourth
dummy gate 138 are removed.
[0196] Subsequently, as illustrated in FIGS. 23A to 23C, the first
dummy gates 117 and 119, the second dummy gate 118, the third dummy
gates 137 and 139, and the fourth dummy gate 138 are removed.
[0197] Subsequently, as illustrated in FIGS. 24A to 24C, the second
insulating films 123, 124, 125, 126, 127, and 128 and the fourth
insulating films 140, 141, and 142 are removed.
[0198] Subsequently, as illustrated in FIGS. 25A to 25C, a gate
insulating film 160 is formed around the first pillar-shaped
silicon layers 129, 131, 132, and 134, around the second
pillar-shaped silicon layers 130 and 133, and on inner sides of the
fifth insulating films 145, 146, and 147.
[0199] Subsequently, as illustrated in FIGS. 26A to 26C, a third
resist 161 for removing the gate insulating film 160 from around
the bottom portions of the second pillar-shaped silicon layers 130
and 133 is formed.
[0200] Subsequently, as illustrated in FIGS. 27A to 27C, while the
third resist 161 is used as a mask, the gate insulating film 160 is
removed from around the bottom portions of the second pillar-shaped
silicon layers 130 and 133. At this time, the first gate insulating
film 160 is divided into a plurality of portions to provide gate
insulating films 162, 163, 164, 165, and 166. Incidentally, the
gate insulating films 164, 165, and 166 may be removed by isotropic
etching.
[0201] Subsequently, as illustrated in FIGS. 28A to 28C, the third
resist 161 is removed.
[0202] Subsequently, as illustrated in FIGS. 29A to 29C, a metal
layer 167 is deposited.
[0203] Subsequently, as illustrated in FIGS. 30A to 30C, the metal
layer 167 is subjected to etch back to form gate electrodes 168a
and 170a and gate lines 168b and 170b around the first
pillar-shaped silicon layers 129, 131, 132, and 134 and to form a
contact electrode 169a and a contact line 169b around the second
pillar-shaped silicon layers 130 and 133.
[0204] Thus, the fifth step has been described. In the fifth step,
after the fourth step, a first interlayer insulating film 159 is
deposited and chemical mechanical polishing is performed to expose
upper portions of the first dummy gates 117 and 119, the second
dummy gate 118, the third dummy gates 137 and 139, and the fourth
dummy gate 138; and the first dummy gates 117 and 119, the second
dummy gate 118, the third dummy gates 137 and 139, and the fourth
dummy gate 138 are removed. Subsequently, the second insulating
films 123, 124, 125, 126, 127, and 128 and the fourth insulating
films 140, 141, and 142 are removed; and a gate insulating film 160
is formed around the first pillar-shaped silicon layers 129, 131,
132, and 134, around the second pillar-shaped silicon layers 130
and 133, and on inner sides of the fifth insulating film 144.
Subsequently, a third resist 161 for removing the gate insulating
film 160 from around the bottom portions of the second
pillar-shaped silicon layers 130 and 133 is formed; the gate
insulating film 160 is removed from around the bottom portions of
the second pillar-shaped silicon layers 130 and 133; and a metal
layer 167 is deposited. Subsequently, etch back is performed to
expose upper portions of the first pillar-shaped silicon layers
129, 131, 132, and 134 and upper portions of the second
pillar-shaped silicon layers 130 and 133 to form gate electrodes
168a and 170a and gate lines 168b and 170b around the first
pillar-shaped silicon layers 129, 131, 132, and 134. After that, a
contact electrode 169a and a contact line 169b are formed around
the second pillar-shaped silicon layers 130 and 133.
[0205] Hereafter, a sixth step according to an embodiment of the
present invention will be described. In the sixth step, gate
insulating films 123, 124, 125, 126, 127, and 128 are deposited
around the first pillar-shaped silicon layers 129, 131, 132, and
134, on the gate electrodes 168a and 170a and the gate lines 168b
and 170b, around the second pillar-shaped silicon layers 130 and
133, and on the contact electrode 169a and the contact line 169b.
Subsequently, a metal layer 178 is deposited and etch back is
performed to expose upper portions of the first pillar-shaped
silicon layers 129, 131, 132, and 134 and upper portions of the
second pillar-shaped silicon layers 130 and 133. Subsequently, the
gate insulating films 123, 124, 125, 126, 127, and 128 on the first
pillar-shaped silicon layers 129, 131, 132, and 134 are removed.
Subsequently, a metal layer 182 is deposited and the metal layer
182 and the metal layer 178 are partially etched to form, from the
metal layer 178, first contacts 179a, 179b, 181a, and 181b
surrounding upper side walls of the first pillar-shaped silicon
layers 129, 131, 132, and 134 and to form, from the metal layer
182, second contacts 183a, 183b, 185a, and 185b connecting upper
portions of the first contacts 179a, 179b, 181a, and 181b and upper
portions of the first pillar-shaped silicon layers 129, 131, 132,
and 134. The first contacts 179a, 179b, 181a, and 181b are formed
of a first metal material forming the metal layer 178. The second
contacts 183a, 183b, 185a, and 185b are formed of a second metal
material forming the metal layer 182.
[0206] First, as illustrated in FIGS. 31A to 31C, the exposed gate
insulating films 162, 163, 164, 165, and 166 are removed.
[0207] Subsequently, as illustrated in FIGS. 32A to 32C, a gate
insulating film 171 is deposited around the first pillar-shaped
silicon layers 129, 131, 132, and 134, on the gate electrodes 168a
and 170a and the gate lines 168b and 170b, around the second
pillar-shaped silicon layers 130 and 133, and on the contact
electrode 169a and the contact line 169b.
[0208] Subsequently, as illustrated in FIGS. 33A to 33C, a fourth
resist 172 for removing the gate insulating film 171 present on at
least a portion of the contact electrode 169a and the contact line
169b is formed.
[0209] Subsequently, as illustrated in FIGS. 34A to 34C, the gate
insulating film 171 present on at least a portion of the contact
electrode 169a and the contact line 169b is removed. Here, the gate
insulating film 171 is divided into a plurality of portions to
provide gate insulating films 173, 174, 175, 176, and 177.
Incidentally, the gate insulating films 175, 176, and 177 may be
removed by isotropic etching.
[0210] As described above, contacts are formed by etching only for
the thickness of the gate insulating film 160 and the thickness of
the gate insulating film 171. This eliminates the necessity of
performing the steps of forming deep contact holes.
[0211] Subsequently, as illustrated in FIGS. 35A to 35C, the fourth
resist 172 is removed.
[0212] Subsequently, as illustrated in FIGS. 36A to 36C, a metal
layer 178 is deposited. In a case where the transistor to be formed
is of an n-type, the first metal material forming the metal layer
178 preferably has a work function of 4.0 to 4.2 eV. In this case,
examples of the first metal material include a compound (TaTi)
formed of tantalum and titanium and tantalum nitride (TaN). On the
other hand, in a case where the transistor to be formed is of a
p-type, the first metal material forming the metal layer 178
preferably has a work function of 5.0 to 5.2 eV. In this case,
examples of the first metal material include ruthenium (Ru) and
titanium nitride (TiN).
[0213] Subsequently, as illustrated in FIGS. 37A to 37C, the metal
layer 178 is subjected to etch back to expose upper portions of the
first pillar-shaped silicon layers 129, 131, 132, and 134 and upper
portions of the second pillar-shaped silicon layers 130 and 133. At
this time, metal lines 179, 180, and 181 are formed from the metal
layer 178.
[0214] Subsequently, as illustrated in FIGS. 38A to 38C, the
exposed gate insulating films 173 and 174 on the first
pillar-shaped silicon layers 129, 131, 132, and 134 are
removed.
[0215] Subsequently, as illustrated in FIGS. 39A to 39C, a metal
layer 182 is deposited. The metal layer 182 may be formed of the
same metal material as that for the metal layer 178 and the type of
the metal material is not particularly limited.
[0216] Subsequently, as illustrated in FIGS. 40A to 40C, the metal
layer 182 is subjected to etch back to form metal lines 183, 184,
and 185.
[0217] Subsequently, as illustrated in FIGS. 41A to 41C, fifth
resists 186 and 187 are formed so as to be orthogonal to the
direction in which the metal lines 179, 180, and 181 and the metal
lines 183, 184, and 185 extend.
[0218] Subsequently, as illustrated in FIGS. 42A to 42C, the metal
lines 179, 180, and 181 and the metal lines 183, 184, and 185 are
etched to form first contacts 179a, 179b, 181a, and 181b, second
contacts 183a, 183b, 185a, and 185b, third contacts 180a and 180b,
and fourth contacts 184a and 184b.
[0219] Subsequently, as illustrated in FIGS. 43A to 43C, the fifth
resists 186 and 187 are removed.
[0220] Thus, the sixth step has been described. In the sixth step,
after the fifth step, gate insulating films 123, 124, 125, 126,
127, and 128 are deposited around the first pillar-shaped silicon
layers 129, 131, 132, and 134, on the gate electrodes 168a and 170a
and the gate lines 168b and 170b, around the second pillar-shaped
silicon layers 130 and 133, and on the contact electrode 169a and
the contact line 169b. Subsequently, a metal layer 178 is deposited
and etch back is performed to expose upper portions of the first
pillar-shaped silicon layers 129, 131, 132, and 134 and upper
portions of the second pillar-shaped silicon layers 130 and 133.
Subsequently, the gate insulating films 123, 124, 125, 126, 127,
and 128 on the first pillar-shaped silicon layers 129, 131, 132,
and 134 are removed. Subsequently, a metal layer 182 is deposited
and the metal layer 182 and the metal layer 178 are partially
etched to form, from the metal layer 178, first contacts 179a,
179b, 181a, and 181b surrounding upper side walls of the first
pillar-shaped silicon layers 129, 131, 132, and 134 and to form,
from the metal layer 182, second contacts 183a, 183b, 185a, and
185b connecting upper portions of the first contacts 179a, 179b,
181a, and 181b and upper portions of the first pillar-shaped
silicon layers 129, 131, 132, and 134.
[0221] Hereafter, a seventh step will be described. In the seventh
step, after the sixth step, a second interlayer insulating film 194
is deposited and planarized to expose upper portions of the second
contacts 183a, 183b, 185a, and 185b; and variable-resistance memory
elements 201a, 201b, 202a, and 202b are formed on the second
contacts 183a, 183b, 185a, and 185b.
[0222] First, as illustrated in FIGS. 44A to 44C, a second
interlayer insulating film 194 is deposited and planarized to
expose upper portions of the second contacts 183a, 183b, 185a, and
185b. At this time, upper portions of the fourth contacts 184a and
184b may be exposed.
[0223] Subsequently, as illustrated in FIGS. 45A to 45C, a metal
layer 195 and a variable-resistance film 196 are deposited.
[0224] Subsequently, as illustrated in FIGS. 46A to 46C, sixth
resists 197 and 198 are formed in a direction orthogonal to the bit
lines such that upper portions of the second contacts 183a, 183b,
185a, and 185b are connected to the metal layer 195.
[0225] Subsequently, as illustrated in FIGS. 47A to 47C, the metal
layer 195 and the variable-resistance film 196 are etched. The
metal layer 195 is divided into metal lines 199 and 200 and the
variable-resistance film 196 is divided into variable-resistance
film lines 201 and 202.
[0226] Subsequently, as illustrated in FIGS. 48A to 48C, the sixth
resists 197 and 198 are removed.
[0227] Subsequently, as illustrated in FIGS. 49A to 49C, a third
interlayer insulating film 203 is deposited and etch back is
performed to expose upper portions of the variable-resistance film
lines 201 and 202.
[0228] Subsequently, as illustrated in FIGS. 50A to 50C, a metal
layer 204 is deposited.
[0229] Subsequently, as illustrated in FIGS. 51A to 51C, seventh
resists 205 and 206 for forming bit lines are formed. The seventh
resists 205 and 206 are preferably formed so as to extend in a
direction orthogonal to the metal lines 199 and 200 and the
variable-resistance film lines 201 and 202.
[0230] Subsequently, as illustrated in FIGS. 52A to 52C, the metal
layer 204, the metal lines 199 and 200, and the variable-resistance
film lines 201 and 202 are etched to form bit lines 207 and 208. At
this time, the metal lines 199 and 200 and the variable-resistance
film lines 201 and 202 are divided to form heaters 199a, 199b,
200a, and 200b that are high-resistance elements and
variable-resistance memory elements 201a, 201b, 202a, and 202b.
[0231] Subsequently, as illustrated in FIGS. 53A to 53C, the
seventh resists 205 and 206 are removed.
[0232] Thus, the seventh step has been described. In the seventh
step, after the sixth step, a second interlayer insulating film 194
is deposited and planarized to expose upper portions of the second
contacts 183a, 183b, 185a, and 185b; and variable-resistance memory
elements 201a, 201b, 202a, and 202b are formed on the second
contacts 183a, 183b, 185a, and 185b.
[0233] Thus, steps for producing a semiconductor device according
to an embodiment of the present invention have been described.
According to this embodiment, all structures of the semiconductor
device are formed with liner resists, which facilitates
microprocessing.
[0234] SGTs allow a larger current per unit gate width to pass than
double-gate transistors. In addition, SGTs have a structure in
which the gate electrode surrounds the pillar-shaped semiconductor
layer. Thus, the gate linewidth per unit area can be increased, so
that an even larger current can be passed. Thus, SGTs allow a large
reset current to pass, so that phase-change films such as the
variable-resistance memory elements 201a, 201b, 202a, and 202b can
be melted at a high temperature (with a large current). For the
subthreshold swing of SGTs, an ideal value can be achieved.
Accordingly, off current can be decreased, so that phase-change
films can be rapidly cooled (by stopping the current).
[0235] The semiconductor device according to the embodiment
includes the gate insulating film 194 formed around upper portions
of the first pillar-shaped silicon layers 129, 131, 132, and 134,
the first contacts 179a, 179b, 181a, and 181b formed around the
gate insulating film 194 and derived from the metal layer 178, and
the second contacts 183a, 183b, 185a, and 185b connecting upper
portions of the first contacts 179a, 179b, 181a, and 181b and upper
portions of the first pillar-shaped silicon layers 129, 131, 132,
and 134 and derived from the metal layer 182. This provides an SGT
in which upper portions of the first pillar-shaped silicon layers
129, 131, 132, and 134 function as n-type semiconductor layers or
p-type semiconductor layers by using the work function difference
between metal and semiconductor. This eliminates the necessity of
performing the step of forming diffusion layers in upper portions
of the first pillar-shaped silicon layers 129, 131, 132, and
134.
[0236] The gate electrode 168a and the gate line 168b are formed of
metal. The first contacts 179a, 179b, 181a, and 181b formed around
the gate insulating film 173 are formed of metal. The second
contacts 183a, 183b, 185a, and 185b connecting upper portions of
the first contacts 179a, 179b, 181a, and 181b and upper portions of
the first pillar-shaped silicon layers 129, 131, 132, and 134 are
formed of metal. Thus, a large amount of metal is used, so that the
heat dissipation effect of the metal can promote cooling of
portions heated by a large reset current. In addition, the gate
electrode 168a and the gate insulating film 162 formed around and
below the gate electrode 168a and the gate line 168b are formed.
Accordingly, a gate last process of forming metal gates at the
final stage of the heat-treatment step is carried out to form the
gate electrodes 168a and 170a that are metal gates. Thus, both of
the metal gate process and the high-temperature process can be
successfully performed.
[0237] The semiconductor device according to the embodiment
includes the fin-shaped silicon layers 104 and 105 formed on the
semiconductor substrate 101, the first insulating film 106 formed
around the fin-shaped silicon layers 104 and 105, the first
pillar-shaped silicon layers 129, 131, 132, and 134 formed on the
fin-shaped silicon layers 104 and 105, and the gate insulating
films 162 and 163 formed around and below the gate electrodes 168a
and 170a and the gate lines 168b and 170b. The gate electrodes 168a
and 170a and the gate lines 168b and 170b are formed of metal. The
gate lines 168b and 170b extend in a direction orthogonal to the
fin-shaped silicon layers 104 and 105. The second diffusion layers
143a and 143b are formed in the fin-shaped silicon layers 104 and
105. The outer linewidths of the gate electrodes 168a and 170a are
equal to the linewidths of the gate lines 168b and 170b. The
linewidths of the first pillar-shaped silicon layers 129, 131, 132,
and 134 are equal to the linewidths of the fin-shaped silicon
layers 104 and 105. Thus, in the semiconductor device according to
the embodiment, the fin-shaped silicon layers 104 and 105, the
first pillar-shaped silicon layers 129, 131, 132, and 134, the gate
electrodes 168a and 170a, and the gate lines 168b and 170b are
formed by self alignment with two masks. As a result, according to
the embodiment, the number of steps required to produce the
semiconductor device can be reduced.
[0238] The semiconductor device according to the embodiment
includes the contact line 169b extending parallel with the gate
lines 168b and 170b and connected to the second diffusion layers
143a and 143b. Thus, the second diffusion layers 143a and 143b are
connected to each other and the resistance of the source lines can
be decreased. As a result, a large reset current can be passed
through the source lines. The contact line 169b extending parallel
with the gate lines 168b and 170b is preferably disposed such that,
for example, a single contact line 169b is disposed every 2, 4, 8,
16, 32, or 64 memory cells arranged in a line in the direction in
which the bit lines 207 and 208 extend.
[0239] In the semiconductor device according to the embodiment, the
structure including the second pillar-shaped silicon layers 130 and
133 and the contact electrode 169a and the contact line 169b formed
around the second pillar-shaped silicon layers 130 and 133, is the
same as the transistor structure of the memory cell positioned, for
example, in the first row and the first column except that the
contact electrode 169a is connected to the second diffusion layers
143a and 143b. All the source lines constituted by the second
diffusion layers 143a and 143b and extending parallel with the gate
lines 168b and 170b are connected to the contact line 169b. As a
result, the number of steps required to produce the semiconductor
device can be reduced.
[0240] Note that the present invention encompasses various
embodiments and modifications without departing from the broad
spirit and scope of the present invention. The above-described
embodiments are used to describe examples of the present invention
and do not limit the scope of the present invention.
[0241] For example, a method for producing a semiconductor device
in which the p-type (including p.sup.+ type) and the n-type
(including n.sup.+ type) in the above-described embodiment are
changed to the opposite conductivity types and a semiconductor
device produced by this method are obviously within the technical
scope of the present invention.
* * * * *