U.S. patent application number 14/428863 was filed with the patent office on 2016-02-04 for array substrate, display device, and manufacturing method of array substrate.
This patent application is currently assigned to BOE TECHNOLOGY GROUP CO., LTD.. The applicant listed for this patent is BOE TECHNOLOGY GROUP CO., LTD.. Invention is credited to Zhanfeng CAO, Jingxia GU, Qi YAO, Feng ZHANG.
Application Number | 20160035573 14/428863 |
Document ID | / |
Family ID | 50571431 |
Filed Date | 2016-02-04 |
United States Patent
Application |
20160035573 |
Kind Code |
A1 |
ZHANG; Feng ; et
al. |
February 4, 2016 |
ARRAY SUBSTRATE, DISPLAY DEVICE, AND MANUFACTURING METHOD OF ARRAY
SUBSTRATE
Abstract
An array substrate is provided, wherein a pixel electrode has
the same material as a source/drain and has a thickness less than
that of the source/drain, or a common electrode has the same
material as a gate and has a thickness less than that of the gate,
which guarantees transmittance of the array substrate while
reducing the process complexity. A display device and a
manufacturing method of the array substrate are also provided.
Inventors: |
ZHANG; Feng; (Beijing,
CN) ; CAO; Zhanfeng; (Beijing, CN) ; YAO;
Qi; (Beijing, CN) ; GU; Jingxia; (Beijing,
CN) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
BOE TECHNOLOGY GROUP CO., LTD. |
Beijing |
|
CN |
|
|
Assignee: |
BOE TECHNOLOGY GROUP CO.,
LTD.
Beijing
CN
|
Family ID: |
50571431 |
Appl. No.: |
14/428863 |
Filed: |
May 28, 2014 |
PCT Filed: |
May 28, 2014 |
PCT NO: |
PCT/CN2014/078702 |
371 Date: |
March 17, 2015 |
Current U.S.
Class: |
257/72 ;
438/669 |
Current CPC
Class: |
H01L 27/124 20130101;
G02F 1/134363 20130101; G02F 1/13439 20130101; H01L 29/45 20130101;
H01L 27/1288 20130101; G02F 2001/134372 20130101; G02F 1/1368
20130101; H01L 21/283 20130101 |
International
Class: |
H01L 21/283 20060101
H01L021/283; G02F 1/1343 20060101 G02F001/1343; G02F 1/1368
20060101 G02F001/1368; H01L 29/45 20060101 H01L029/45 |
Foreign Application Data
Date |
Code |
Application Number |
Jan 24, 2014 |
CN |
201410036343.3 |
Claims
1. An array substrate including a gate, a common electrode,
source/drain and a pixel electrode, wherein the gate and the common
electrode are disposed in a same layer or the source/drain and the
pixel electrode are disposed in a same layer, where the gate and
the common electrode are disposed in the same layer, the common
electrode and the gate are manufactured with a same electrode
material and the common electrode has a thickness less than that of
the gate, the common electrode is formed with a plurality of slits,
and the common electrode has a transmittance greater than 30%;
where the source/drain and the pixel electrode are disposed in the
same layer, the pixel electrode and the source/drain are
manufactured with a same electrode material and the pixel electrode
has a thickness less than that of the source/drain, the pixel
electrode is formed with a plurality of slits, and the pixel
electrode has a transmittance greater than 30%.
2. The array substrate of claim 1, wherein the electrode material
is a single-layer metal film or a multi-layer composite film of Al,
Cu, Mo, AlNd, Cr, Ti, Ag, or a composite film with a metal/medium
one-dimension photonic crystal structure.
3. The array substrate of claim 2, wherein the electrode material
is a single-layer metal film of Ag, the gate has a thickness of
2000 .ANG. and the common electrode has a thickness of 50
.ANG..
4. The array substrate of claim 2, wherein the electrode material
is a composite film comprising ZnS, Ag, ZnS, and Ag, wherein ZnS,
Ag, ZnS and Ag are disposed in sequence in a direction from the
substrate to the composite film, the common electrode/pixel
electrode comprises only a composite layer of ZnS, Ag and ZnS, and
ZnS, Ag, ZnS and Ag has a thicknesses of 400 .ANG., 180 .ANG., 400
.ANG. and 2000 .ANG., respectively.
5. The array substrate of wherein the common electrode or the pixel
electrode has a thickness of 10.about.100 .ANG. and a transmittance
of 30%-90%.
6. The array substrate of claim 1, wherein each of the common
electrode and the pixel electrode is formed with a plurality of
slits and slits in the common electrode and slits in the pixel
electrode are parallel to each other.
7. The array substrate of claim 6, wherein projections of slits in
the common electrode on the substrate and projections of slits in
the pixel electrode on the substrate do not overlap.
8. A method for manufacturing an array substrate, comprising:
depositing an electrode material layer; forming a photoresist layer
on the electrode material layer and forming patterned photoresist
on the electrode material for a source/drain with a dual-tone mask;
after forming the source/drain pattern through ethcing, thinning
the photoresist by an ashing process to expose the electrode
material in a pixel electrode region; and forming a pixel electrode
pattern through etching again.
9. A method for manufacturing an array substrate, comprising:
depositing an electrode material layer on a substrate; forming a
photoresist layer on the electrode material layer and forming
patterned photoresist on the electrode material for a gate with a
dual-tone mask; after forming the gate pattern through etching,
thinning the photoresist by an ashing process to expose the
electrode material in a common electrode region; forming a common
electrode pattern through etching again.
10. (canceled)
11. The array substrate of claim 2, wherein the common electrode or
the pixel electrode has a thickness of 10.about.100 .ANG. and a
transmittance of 30%-90%.
12. The array substrate of claim 3, wherein the common electrode or
the pixel electrode has a thickness of 10.about.100 .ANG. and a
transmittance of 30%-90%.
13. The array substrate of claim 4, wherein the common electrode or
the pixel electrode has a thickness of 10.about.100 .ANG. and a
transmittance of 30%-90%.
14. The array substrate of claim 2, wherein each of the common
electrode and the pixel electrode is formed with a plurality of
slits and slits in the common electrode and slits in the pixel
electrode are parallel to each other.
15. The array substrate of claim 3, wherein each of the common
electrode and the pixel electrode is formed with a plurality of
slits and slits in the common electrode and slits in the pixel
electrode are parallel to each other.
16. The array substrate of claim 4, wherein each of the common
electrode and the pixel electrode is formed with a plurality of
slits and slits in the common electrode and slits in the pixel
electrode are parallel to each other.
17. The array substrate of claim 5, wherein each of the common
electrode and the pixel electrode is formed with a plurality of
slits and slits in the common electrode and slits in the pixel
electrode are parallel to each other.
18. The array substrate of claim 14, wherein projections of slits
in the common electrode on the substrate and projections of slits
in the pixel electrode on the substrate do not overlap.
19. The array substrate of claim 15, wherein projections of slits
in the common electrode on the substrate and projections of slits
in the pixel electrode on the substrate do not overlap.
20. The array substrate of claim 16, wherein projections of slits
in the common electrode on the substrate and projections of slits
in the pixel electrode on the substrate do not overlap.
21. The array substrate of claim 17, wherein projections of slits
in the common electrode on the substrate and projections of slits
in the pixel electrode on the substrate do not overlap.
Description
TECHNICAL FIELD
[0001] Embodiments of the present disclosure relate to an array
substrate, a display device comprising the array substrate and a
method for manufacturing the array substrate.
BACKGROUND
[0002] Thin film transistor liquid crystal displays (TFT-LCDs) are
characterized in small volume, low power consumption and free of
irradiation and dominate the market of flat-panel displays
currently. With the advanced super dimension switch technology
(ADS), a fringe electric field is generated by electrodes between
pixels in the same plane to enable aligned liquid crystal molecules
disposed between electrodes and right above electrodes to rotate in
the plane direction (parallel to the substrate), which increases
the viewing angle while enhancing light transmittance of the liquid
crystal layer.
[0003] FIG. 1 is a schematic structural view of an array substrate
of ADS mode liquid crystal display known by the inventor. The array
substrate is completed on a glass substrate by 5 masking processes
from bottom to top, including a masking for fabricating common
electrodes 13 on the glass substrate 10, a masking for fabricating
gates 11 and common electrode connecting lines 12, a masking for
fabricating an active layer and source/drain and a masking for
fabricating vias in passivation layer and a masking for fabricating
pixel electrodes 14.
[0004] As known by the inventor, the common electrodes 13 and the
gates 11 are fabricated by two masking processes, respectively by
transparent conductive metal oxide film and metal materials, which
is relatively complex and at high costs.
SUMMARY
[0005] Embodiments of the present disclosure provide an array
substrate and a manufacturing method of the array substrate to
simplify the manufacturing processes of the array substrate and
improve the display effect of the array substrate.
[0006] An array substrate comprises a gate, a common electrode, a
source/drain and a pixel electrode, wherein the gate and the common
electrode are disposed in a same layer or the source/drain and the
pixel electrode are disposed in a same layer,
[0007] When the gate and the common electrode are disposed in the
same layer, the common electrode and the gate are manufactured with
a same material and the common electrode has a thickness less than
that of the gate, the common electrode is formed with a plurality
of slits, and the common electrodes has a transmittance greater
than 30%;
[0008] when the source/drain and the pixel electrode are disposed
in the same layer, the pixel electrode and the source/drain are
manufactured with a same material and the pixel electrode has a
thickness less than that of the source/drain, the pixel electrode
is formed with a plurality of slits, and the pixel electrode has a
transmittance greater than 30%.
[0009] Since the gate and the common electrode are made of the same
material, it is possible to reduce process complexity. The common
electrode with a thickness less than that of the gate guarantees
the transmittance of the common electrode. Furthermore, it is
possible to manufacture the gate and the common electrode in the
same layer by one dual-tone mask, or manufacture the source/drain
and the pixel electrode in the same layer by one dual-tone mask,
which saves one mask and reduces process complexity and process
costs.
[0010] In one embodiment of the present disclosure, the gate
material or source/drain material can be a single-layer metal film
or a multi-layer composite film of Al, Cu, Mo, AlNd, Cr, Ti, Ag or
a composite film with a metal/medium one-dimension photonic crystal
structure.
[0011] In one embodiment of the present disclosure, in order to
obtain a better transmittance, the gate material is specifically a
single-layer metal film of Ag, and the gate has a thickness of 2000
.ANG., the common electrode has a thickness of 50 .ANG..
[0012] In one embodiment of the present disclosure, in order to
obtain a better transmittance, the gate material is a composite
film comprising ZnS, Ag, ZnS, and Ag, wherein ZnS, Ag, znS and Ag
are disposed in sequence in a direction from the substrate to the
composite film, and ZnS, Ag, ZnS and Ag in the gate has a
thicknesses of 400 .ANG., 180 .ANG., 400 .ANG. and 2000 .ANG.
respectively, the common electrode just comprises a composite
layers of ZnS, Ag and ZnS with a thickness of 400 .ANG., 180.ANG.
and 400 .ANG. respectively.
[0013] In one embodiment of the present disclosure, the common
electrode or the pixel electrode has a thickness of 10-100.ANG. and
a transmittance of 30%-90%.
[0014] In one embodiment of the present disclosure, in order to
reduce storage capacitance between the common electrode and the
pixel electrode, each of the common electrode and the pixel
electrode is formed with a plurality of slits and slits in the
common electrode and slits in the pixel electrode are parallel to
each other.
[0015] In one embodiment of the present disclosure, in order to
further reduce the storage capacitance between the common electrode
and the pixel electrode, projections of slits in the common
electrode on the substrate and projections of slits in the pixel
electrode on the substrate do not overlap.
[0016] At least one embodiment of the present disclosure further
provides a method for manufacturing an array substrate
comprising:
[0017] depositing a source/drain material;
[0018] forming patterned photoresist on the source/drain material
by a dual-tone mask;
[0019] after forming the source/drain pattern through etching,
thinning the photoresist by an ashing process to expose the
source/drain material in a pixel electrode region;
[0020] forming a pixel electrode pattern by etching again.
[0021] The source/drain and the pixel electrode are manufactured by
one masking, hence one mask is saved and the manufacturing process
of the array substrate is simplified.
[0022] At least one embodiment of the present disclosure further
provides a manufacturing method of an array substrate
comprising:
[0023] depositing a gate material on a substrate;
[0024] forming patterned photoresist on the gate material by a
dual-tone mask;
[0025] after forming the gate pattern through etching, thinning the
photoresist by an ashing process to expose gate material in a
common electrode region;
[0026] forming a common electrode pattern by etching again.
[0027] Since the gate and the common electrode are manufactured by
one masking, hence one mask is saved and the manufacturing process
of the array substrate is simplified.
[0028] At least one embodiment of the present disclosure further
provides a display device comprising the above-mentioned array
substrate.
[0029] With an array substrate, a display device and a
manufacturing method of the array substrate according to at least
one embodiment of the present disclosure, the pixel electrode has
the same material as the source/drain and has a thickness less than
that of the source/drain, or the common electrode has the same
material as the gate and has a thickness less than that of the
gate, thereby ensuring transmittance of the array substrate while
decreasing process complexity.
BRIEF DESCRIPTION OF THE DRAWINGS
[0030] In order to clearly illustrate the technical solution of the
embodiments of the disclosure, the drawings of the embodiments will
be briefly described in the following; it is obvious that the
described drawings are only related to some embodiments of the
disclosure and thus are not limitative of the disclosure.
[0031] FIG. 1 is a schematic structural view of an array substrate
known by the inventor;
[0032] FIGS. 2a and 2b are schematic structural views of an array
substrate according to one embodiment of the present
disclosure;
[0033] FIGS. 3a-3f are schematic diagrams of a manufacturing
process of the array substrate according to one embodiment of the
present disclosure;
[0034] FIG. 4 is a graph of the transmittance of Ag film for the
maximum potential vs. a film thickness according to one embodiment
of the present disclosure;
[0035] FIG. 5 is a graph of the transmittance of a composite film
layer of ZnS, Ag and ZnS vs. a film thickness according to one
embodiment of the present disclosure;
[0036] FIG. 6 is a flow chart I of a manufacturing method of the
array substrate according to one embodiment of the present
disclosure; and
[0037] FIG. 7 is a flow chart II of a manufacturing method of the
array substrate provided in one embodiment of the present
disclosure.
DETAILED DESCRIPTION
[0038] In order to make objects, technical details and advantages
of the embodiments of the disclosure apparent, the technical
solutions of the embodiment will be described in a clearly and
fully understandable way in connection with the drawings related to
the embodiments of the disclosure. It is obvious that the described
embodiments are just a part but not all of the embodiments of the
disclosure. Based on the described embodiments herein, those
skilled in the art can obtain other embodiment(s), without any
inventive work, which should be within the scope of the
disclosure.
[0039] At least one embodiment of the present disclosure provides
an array substrate, a display device and a manufacturing method of
the array substrate in which a pixel electrode has the same
material as a source/drain and has a thickness less than that of
the source/drain, or a common electrode has the same material as a
gate and has a thickness less than that of the gate, thereby
ensuring transmittance of the array substrate while decreasing
process complexity.
[0040] As illustrated in FIG. 2a or 2b, an array substrate
according to one embodiment of the present disclosure comprises a
gate 201, a common electrode 202, a source/drain 203 and a pixel
electrode 204, wherein the gate 201 and the common electrode 202
are disposed in the same layer or the source/drain 203 and the
pixel electrode 204 are disposed in the same layer, when the gate
201 and the common electrode 202 are disposed in the same layer,
they are manufactured with the same material, and the common
electrode 202 has a thickness less than that of the gate 201, the
common electrode 202 are formed with a plurality of slits and has a
transmittance greater than 30%; when the source/drain 203 and the
pixel electrode 204 are disposed in the same layer, they are
manufactured with the same material, the pixel electrode 204 has a
thickness less than that of the source/drain 203, the pixel
electrode 204 is formed with a plurality of slits, and the pixel
electrode 204 has a transmittance greater than 30%.
[0041] Since the gate and the common electrode are made of the same
material, it is possible to reduce process complexity. The common
electrode with a thickness less than that of the gate guarantees
the transmittance of the common electrode. Furthermore, it is
possible to manufacture the gate and the common electrode in the
same layer by one dual-tone mask, or manufacture the source/drain
and the pixel electrode in the same layer by one dual-tone mask,
which saves one mask and reduces process complexity and process
costs.
[0042] For example, the dual-tone mask can be a halftone mask or a
gray-tone mask.
[0043] Gate material for manufacturing the gate and the common
electrode or source/drain material for manufacturing the
source/drain and the pixel electrode can be: a single-layer metal
film or a multi-layer composite film of Al(aluminum), Cu(copper),
Mo(molybdenum), AlNd(aluminum neodymium alloy), Cr(chromium),
Ti(titanium), Ag(silver) or a composite film with a metal/medium
one dimension photonic crystal structure.
[0044] In this embodiment, the common electrode or the pixel
electrode has a thickness of 10 .ANG..about.100 .ANG. and a
transmittance of 30%-90%.
[0045] In this embodiment, taking the gate and the common electrode
disposed in the same layer as an example, the process steps of
forming patterns of the common electrode and the gate with one
dual-tone mask comprising:
[0046] Step 1: depositing a layer of electrode material 302 on a
base substrate 301, as illustrated in FIG. 3a;
[0047] Step 2: forming a photoresist layer on the layer of gate
material, and exposing the photoresist layer by a dual-tone masking
process to form patterned photoresist 303 with various heights on
the gate material 302, as illustrated in FIG. 3b;
[0048] Step 3: etching the gate material 302 not protected by the
photoresist through the first etching process to form a patterned
common electrode 304 and a patterned gate 305, as illustrated in
FIG. 3c;
[0049] Step 4: thinning the photoresist 303 by an ashing process to
remove photoresist on the common electrode 304 and expose the
common electrode pattern, as illustrated in FIG. 3d;
[0050] Step 5: etching common electrode pattern not protected by
the photoresist by a second etching process that is controlled
strictly such that the common electrode 304 has a thickness of 10
.ANG..about.500 .ANG. and a transmittance of 30%.about.90%, as
illustrated in FIG. 3e;
[0051] Step 6: stripping the photoresist 303 by a stripping process
to complete fabrication of common electrodes 304 and gates 305, as
illustrated in FIG. 3f.
[0052] The common electrode or the pixel electrode can be obtained
by thinning a single-layer metal film of Al, Cu, Mo, AlNd, Cr, Ti
and Ag or a composite film consisting of the mentioned material by
an etching process. For example, Ag can be used for the gate metal
layer, wherein the gate Ag has a thickness of 2000 .ANG., the Ag in
the common electrode part has a thickness of 50 .ANG., then the
transmittance of the common electrode part is about 90%.
Transmittance of Ag vs. its thickness is illustrated in FIG. 4.
[0053] A composite film layer with metal/medium one dimension
photonic crystal structure can also be used for the gate, for
example, a composite film layer of ZnS (zinc sulfide), Ag, ZnS and
a metal in sequence, wherein ZnS, Ag, ZnS and Ag are disposed in
sequence in the direction pointing to the composite film from the
substrate, and a transparent electrode of metal/medium one
dimension photonic crystal can be used for the common electrode,
for example, a composite film layer of ZnS, Ag and ZnS in sequence,
which is obtained by removing the metal film on the surface of the
composite film layer of ZnS, Ag, ZnS and a metal in sequence
through an etching process. For example, it is possible to use a
composite film layer of ZnS, Ag, ZnS and Ag in sequence as a gate,
in which thickness of ZnS, Ag, znS and Ag in the gate region is 400
.ANG., 180 .ANG., 400 .ANG. and 2000 .ANG. respectively, and
thickness of ZnS, Ag and ZnS in the common electrode is 400 .ANG.,
180 .ANG. and 400 .ANG. respectively, and the transmittance curve
in visible light range thereof is illustrated in FIG. 5 with the
maximum transmittance approaching 90% (X=550 nm).
[0054] As can be seen, when each of the gate and the common
electrode is made of gate metal material with different
thicknesses, it is guaranteed that the transmittance of the common
electrode part can meet the display demand of an liquid crystal
display apparatus of ADS mode, thereby enhancing the display effect
of the array substrate.
[0055] Further, each of the common electrode and the pixel
electrode in the array substrate is formed with a plurality of
slits and slits in the common electrode are parallel to slits in
the pixel electrode. Since both the common electrode and the pixel
electrode have a shape of line, it is possible to reduce storage
capacitance between the common electrode and the pixel electrode,
and at the same time as the metal material for the common electrode
has a shape of line, it is also possible to enhance transmittance
of the pixel part to a certain extent.
[0056] Still further, it is possible to make projections of slits
in the common electrode on the substrate and slits in the pixel
electrode on the substrate not to overlap, thereby further reducing
the storage capacitance between common electrode and pixel
electrode.
[0057] As illustrated in FIG. 6, an embodiment of the present
disclosure provides a manufacturing method of an array substrate
comprising:
[0058] Step S601, depositing an electrode material on a base
substrate;
[0059] Step S602, forming a photoresist layer on the gate material
and forming patterned photoresist on the electrode material with a
dual-tone mask;
[0060] Step S603, after forming a gate pattern by etching, thinning
the photoresist by an ashing process to expose electrode material
in a common electrode region;
[0061] Step S604, etching again to forming a common electrode
pattern by etching again.
[0062] For example, the dual-tone mask can be specifically a
gray-tone mask or a halftone mask.
[0063] Since the gate and the common electrode are made of the same
material, it is possible to reduce process complexity. The common
electrode with a thickness less than that of the gate guarantees
the transmittance of the common electrode. And the method
manufactures the gate and the common electrode by one masking,
hence saving one mask and simplifying the manufacturing process of
the array substrate.
[0064] For the array substrate in which the common electrode and
the gate are not in the same layer while the pixel electrode and
the source/drain are in the same layer, embodiments of the present
disclosure further provides a manufacturing method of an array
substrate as illustrated in FIG. 7, comprising:
[0065] Step S701, depositing a layer of an electrode material;
[0066] Step S702, forming a photoresist layer on the electrode
material layer and forming patterned photoresist on the electrode
material with a dual-tone mask;
[0067] Step S703, after forming the source/drain pattern by
etching, thinning the photoresist by an ashing process to expose
electrode material in a pixel electrode region;
[0068] Step S704, forming a pixel electrode pattern through etching
again.
[0069] For example, the dual-tone mask may be specifically a
gray-tone mask or a halftone mask.
[0070] In the embodiment, the source/drain and the pixel electrode
are manufactured by one masking, hence saving one mask and
simplifying the manufacturing process of the array substrate.
[0071] An embodiment of the present disclosure further provides a
display device including the array substrate provided in the
embodiment of the present disclosure.
[0072] Embodiments of the present disclosure provide an array
substrate, a display device and a manufacturing method of the array
substrate in which the pixel electrode has the same material as the
source/drain and has a thickness less than that of the
source/drain, or the common electrode has the same material as the
gate and has a thickness less than that of the gate, thereby
ensuring transmittance of the array substrate while decreasing
process complexity.
[0073] The foregoing are merely exemplary embodiments of the
disclosure, but are not used to limit the protection scope of the
disclosure. The protection scope of the disclosure shall be defined
by the attached claims.
[0074] The present application claims priority of a China patent
application no. 201410036343.3 filed on Jan. 24, 2014, the
disclosure of which is hereby entirely incorporated by
reference.
* * * * *