U.S. patent application number 14/876765 was filed with the patent office on 2016-01-28 for semiconductor device with gate electrodes buried in trenches.
The applicant listed for this patent is RENESAS ELECTRONICS CORPORATION. Invention is credited to Hiroaki KATOU, Hiroyoshi KUDOU, Taro MORIYA, Satoshi UCHIYA.
Application Number | 20160027916 14/876765 |
Document ID | / |
Family ID | 49291619 |
Filed Date | 2016-01-28 |
United States Patent
Application |
20160027916 |
Kind Code |
A1 |
KATOU; Hiroaki ; et
al. |
January 28, 2016 |
SEMICONDUCTOR DEVICE WITH GATE ELECTRODES BURIED IN TRENCHES
Abstract
Trenches are formed in a base layer and extend parallel to each
other. A gate insulating film is formed on the inner wall of each
of multiple trenches. A gate electrode GE is buried in each of the
trenches. The source layer is formed in the base layer to a depth
less than the base layer. The source layer is disposed between each
of the trenches. A second conduction type high concentration layer
is formed between the source layer and the trench in a plan view.
The trench, the source layer, and the second conduction type high
concentration are arranged in this order repetitively in a plan
view. One lateral side of the trench faces the source layer and the
other lateral side of the trench faces the second conduction type
high concentration layer.
Inventors: |
KATOU; Hiroaki; (Tokyo,
JP) ; KUDOU; Hiroyoshi; (Tokyo, JP) ; MORIYA;
Taro; (Tokyo, JP) ; UCHIYA; Satoshi; (Tokyo,
JP) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
RENESAS ELECTRONICS CORPORATION |
Tokyo |
|
JP |
|
|
Family ID: |
49291619 |
Appl. No.: |
14/876765 |
Filed: |
October 6, 2015 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
13851875 |
Mar 27, 2013 |
9184285 |
|
|
14876765 |
|
|
|
|
Current U.S.
Class: |
257/330 |
Current CPC
Class: |
H01L 29/42368 20130101;
H01L 27/088 20130101; H01L 29/0615 20130101; H01L 29/42372
20130101; H01L 29/4236 20130101; H01L 29/7827 20130101; H01L
29/0865 20130101; H01L 29/456 20130101; H01L 29/7811 20130101; H01L
21/823487 20130101; H01L 29/7813 20130101 |
International
Class: |
H01L 29/78 20060101
H01L029/78; H01L 29/423 20060101 H01L029/423; H01L 27/088 20060101
H01L027/088 |
Foreign Application Data
Date |
Code |
Application Number |
Apr 9, 2012 |
JP |
2012-088373 |
Claims
1. A semiconductor device comprising: a semiconductor substrate; a
first conduction type drain layer formed to the semiconductor
substrate and situated at the rear face of the semiconductor
device; a second conduction type base layer formed to the
semiconductor substrate and situated above the drain layer; a
plurality of trenches formed in the base layer; a gate insulating
film formed on the inner wall of each of the trenches; a gate
electrode buried in each of the trenches; a first conduction type
source layer formed in the base layer to a depth less than in the
base layer, and situated between each of the trenches; and a source
electrode coupled to the source layer, wherein two lateral sides of
the trench faces respectively to source layers different from each
other, wherein the source layer facing the one lateral side is
coupled to the source electrode, and wherein the source layer
facing the other lateral side is not coupled to the source
electrode.
Description
CROSS-REFERENCE TO RELATED SPECIFICATIONS
[0001] This application is a Divisional application of U.S. patent
application Ser. No. 13/851,875, filed on Mar. 27, 2013, which in
turn claims the benefit of Japanese Patent Application No.
2012-088373 filed on Apr. 9, 2012, the disclosures of which
Applications are incorporated herein by reference.
BACKGROUND
[0002] The present invention relates to a semiconductor device and,
in particular, to a semiconductor device having a vertical
transistor.
[0003] Some semiconductor devices have vertical transistors. The
vertical transistor is used, for example, in a device for
controlling a high current. Some vertical transistors have a trench
gate structure. The transistor having the trench gate structure has
a structure in which a p-layer as a channel layer is formed over an
n-layer as a drain and, further, an n-layer as a source is formed
to the surface layer of the p-layer as shown, for example, in
Japanese Unexamined Patent Application Publication No. 2000-353805
and Japanese Unexamined Patent Application Publication (Translation
of PCT Application) No. 2004-513518. The gate electrode of the
trench structure extends from the p-layer to the n-layer. The lower
end of the gate electrode enters in the n-layer.
[0004] Further, in Japanese Unexamined Patent Application
Publication No. 2000-353805 and Japanese Unexamined Patent
Application Publication (Translation of PCT Application) No.
2004-513518, the n-layer as the source is disposed only on one
lateral side of the trench gate. The p.sup.- region is formed to a
depth more than the p well on the other lateral side of the trench
gate. The p.sup.- region is disposed so as to lower the resistance
of the drain region and ensure the withstand voltage of the
transistor.
SUMMARY
[0005] One of the indexes for the performance of the vertical
transistors is that the on-resistance of the drain is low. In order
to lower the drain resistance, the gates are preferably arranged
densely, thereby increasing the channel density. On the other hand,
the index for the performance of the vertical transistor also
includes that safety operating area (SOA) is wide in the graph
showing Vd-Id characteristics (refer to FIG. 19). SOA is an area
where the semiconductor device can be used without causing thermal
runaway. However, if the gates are arranged densely, SOA is
narrowed. As described above, it was difficult to ensure SOA while
lowering the drain resistance.
[0006] Other subjects and novel features of the invention will
become apparent by reading the description of the present
specification and with reference to the appended drawings.
[0007] According to an aspect of the invention, multiple trenches
are formed in a semiconductor substrate. A gate insulating film is
formed on the lateral side of the trench. A gate electrode is
buried in the trench. A first conduction type source layer and a
second conduction type high concentration layer are formed in a
second conduction type base layer. The second conduction type high
concentration layer has an impurity concentration higher than that
of the base layer. The trench, the source layer, and the second
conduction type high concentration layer are arranged in this order
repetitively in a plan view, and one lateral side of the trench
faces the source layer and the other lateral side of trench faces
the second conduction type high concentration layer.
[0008] According to another aspect of the invention, two lateral
sides of the trench described respectively face source layers
different from each other. The source layer facing one lateral side
is coupled to a source electrode and the source layer facing the
other lateral side is not coupled to the source electrode.
[0009] According to the aspect of the invention, a wide SOA can be
ensured while lowering the drain resistance.
BRIEF DESCRIPTION OF THE DRAWINGS
[0010] FIG. 1 is a cross sectional view showing a configuration of
a semiconductor device according to a first embodiment;
[0011] FIG. 2 is a plan view of the semiconductor device;
[0012] FIG. 3 is a view of showing a path of current flowing from a
drain to a source in semiconductor device of a comparative
example;
[0013] FIG. 4 is a view of a semiconductor device of a preferred
embodiment showing a path of a current flow from a drain to a
source;
[0014] FIG. 5 is a graph showing a relation between the value of a
drain current and a specific resistivity (Rsp) when the temperature
reaches 150.degree. C. in the vertical transistor of the preferred
embodiment and the vertical transistor of the structure shown in
FIG. 3;
[0015] FIG. 6 is a plan view of a semiconductor device according to
a second embodiment;
[0016] FIG. 7 is a cross sectional view showing a structure of the
semiconductor device shown in FIG. 6;
[0017] FIG. 8 is a cross sectional view showing a method of
manufacturing the semiconductor device shown in FIG. 6 and FIG.
7;
[0018] FIG. 9 is a cross sectional view showing the method of
manufacturing the semiconductor device shown in FIG. 6 and FIG.
7;
[0019] FIG. 10 is a cross sectional view showing the method of
manufacturing the semiconductor device shown in FIG. 6 and FIG.
7;
[0020] FIG. 11 is a cross sectional view showing the method of
manufacturing the semiconductor device shown in FIG. 6 and FIG.
7;
[0021] FIG. 12 is a cross sectional view showing the method of
manufacturing the semiconductor device shown in FIG. 6 and FIG.
7;
[0022] FIG. 13 is a cross sectional view showing the configuration
of a semiconductor device according to a third embodiment;
[0023] FIG. 14 is a cross sectional view showing the configuration
of a semiconductor device according to a fourth embodiment;
[0024] FIG. 15 is a cross sectional view showing the configuration
of a semiconductor device according to a fifth embodiment;
[0025] FIG. 16 is a cross sectional view showing the configuration
of a semiconductor device according to a sixth embodiment; and
[0026] FIG. 17A is a cross sectional view along line A-A' in FIG.
16;
[0027] FIG. 17B is a cross sectional view along line B-B' in FIG.
16;
[0028] FIG. 18 is a view showing a circuit configuration of an
electronic device according to a seventh embodiment; and
[0029] FIG. 19 is a view for explaining SOA.
DETAILED DESCRIPTION
[0030] Preferred embodiments of the invention are to be described
with reference to the drawings. Throughout the drawings, identical
constitutional elements carry same reference numerals for which
explanations are optionally omitted.
First Embodiment
[0031] FIG. 1 is a cross sectional view sowing a configuration of a
semiconductor device SC according to a first embodiment. FIG. 2 is
a plan view of the semiconductor device SC. The semiconductor
device SC has a vertical transistor PTR. The vertical transistor
PTR is, for example, a power control transistor. The vertical
transistor PTR is formed by using a semiconductor substrate SUB.
Specifically, the vertical transistor PTR has a drain layer DRN, a
base layer BSE, trenches TRN, a gate insulating film GIN, a gate
electrode GE, a source layer SOU, and a second conduction type high
concentration layer HIN. The drain layer DRN is of a first
conduction type (for example, n-type) and formed in the
semiconductor substrate SUB, the base layer BSE is of a second
conduction type (for example, p-type), formed in the semiconductor
substrate SUB, situated above the drain layer DRN. The trenches TRN
are formed in the base layer BSE and extend in parallel to each
other to form a stripe pattern. The gate insulating films GIN are
formed each on the inner wall of the trenches TRN. The gate
electrode GE is buried in each of the trenches TRN. The source
layer SOU is formed in the base layer BSE to a depth less than the
base layer BSE. The source layer SOU is disposed between each of
the multiple trenches TRN. Second conduction type high
concentration layer HIN is formed between each of the source layer
SOU and the trench TRN in a plan view. The second conduction type
high concentration layer HIN is a second conduction type impurity
layer which is coupled at the bottom to the base layer BSE and has
higher concentration than that of the base layer BSE.
[0032] In a plan view, the trench TRN, the source layer SOU, and
the second conduction type high concentration layer HIN are
arranged in this order repetitively. The trench TRN faces at one
lateral side to the source layer SOU and the trench TRN faces at
the other lateral side to the second conduction type high
concentration layer HIN. Details are to be described assuming the
n-type for first conduction type and the p-type for the second
conduction type.
[0033] The semiconductor substrate SUB comprises a substrate WFR
and an epitaxial layer EPI which is epitaxially grown thereover.
The substrate WFR is an n.sup.+-type substrate and formed, for
example, of silicon. In this embodiment, the substrate WFR serves
as a drain layer DRN. The epitaxial layer EPI is an n-type
epitaxial layer, for example, an n-type silicon layer. A base layer
BSE is formed by implanting a p-type impurity into the surface
layer of the epitaxial layer EPI. A layer in the epitaxial layer
EPI in which the base layer BSE is not formed is an n-type
epitaxial layer NEP (first conduction type low concentration
layer). The n-type epitaxial layer NEP couples the drain layer DRN
and the base layer BSE.
[0034] The impurity concentration of the base layer BSE is
5.times.10.sup.16 atoms/cm.sup.3 or more and 5.times.10.sup.17
atoms/cm.sup.3 or less, and the specific resistivity of the n-type
epitaxial layer NEP is, for example, 0.4 .OMEGA.cm or more and 1.0
.OMEGA.cm or less. The thickness of the substrate WFR is, for
example, 150 nm or more and 300 nm or less and the thickness of the
epitaxial layer EPI is, for example, 4.0 .mu.m or more and 15 .mu.m
or less.
[0035] Trenches TRN are disposed in the epitaxial layer EPI. The
trench TRN penetrates the base layer BSE and the lower end of the
epitaxial layer EPI intrudes in the n-type epitaxial layer NEP. A
gate insulating film GIN is formed on the inner wall and the bottom
of the trench TRN. The gate insulating film GIN is formed, for
example, by a thermal oxidation method and it may be formed also by
a deposition method. The gate insulating film GIN is, for example,
a silicon oxide film. Further, a gate electrode GE fills the
remaining space of the trench TRN. The gate electrode GE is, for
example, a polysilicon film.
[0036] The source layer SOU and the second conduction type high
concentration layer HIN are disposed each by one between adjacent
trenches TRN. Accordingly, only one of two lateral sides of the
trench TRN faces the source layer SOU. That is, only the side of
the base layer BSE facing one lateral side of the trench TRN serves
as a channel of the vertical transistor PTR. The second conduction
type high concentration layer HIN is an impurity layer for
providing a reference potential to the base layer BSE and formed to
a depth more than that of the source layer SOU. The source layer
SOU and the second conduction type high concentration HIN situated
between two adjacent trenches are in adjacent to each other. The
width of the source layer SOU in the direction perpendicular to the
trench TRN is preferably, for example, 1.0 .mu.m or less.
[0037] The width of the trench TRN is 0.2 .mu.m or more and 0.7
.mu.m or less. The distance between the center of a trench TRN and
the center of the trench TRN situated adjacent therewith is, for
example, 0.8 .mu.m or more and 4.5 .mu.m or less. The depth of the
trench TRN is, for example, 0.6 .mu.m or more and 3.5 .mu.m or
less.
[0038] A drain electrode EL1 is formed to the surface of the
substrate WFR not formed with the epitaxial layer EPI. In
interlayer insulating film INS and a source electrode EL2 are
formed in this order over the epitaxial layer EPI. The source
electrode EL2 is coupled by way of contacts CON buried in the
interlayer insulating film INS with the source layer SOU and the
second conduction type high concentration layer HIN. The drain
electrode EL1 is, for example, a stacked Ti/Ni/Ag film. The source
electrode EL2 comprises, for example, Al or an Al alloy. The
contact CON comprises, for example, W (tungsten). The contacts CON
are disposed, for example, in plurality in the direction where the
trenches TRN extend. In a plan view, each of the contacts CON may
be arranged so as to overlap the source layer SOU and the second
conduction type high concentration layer HIN.
[0039] Then, the function and the effect of the first embodiment
are to be described with reference to FIG. 3 and FIG. 4.
[0040] FIG. 3 shows a path of current CUR in a semiconductor device
SC of a comparative example when the current CUR flows from the
drain to the source. In the vertical transistor shown in the
drawing, the source layer SOU is formed so as to face the two
lateral sides of the trench TRN respectively. Accordingly, when a
voltage higher than a threshold voltage is applied to the gate
electrode GE, channels are formed in the portion of the base layer
BSE situated on the two lateral sides of the trench TRN
respectively. In the vertical transistor, electrons reaching by way
of the channel to the n-type epitaxial layer NEP move to the drain
electrode ELL in which the width of the current enlarges as it
approaches the drain electrode EL1. Therefore, as the distance
between the gate electrodes GE is narrowed, current CUR flowing by
way of different channels may sometimes overlap to each other
(region shown as a current overlap region DCUR in the drawing).
Since the current density increases in the current overlap region
DCUR, the on-resistance of the drain increases. Further, the amount
of heat generation increases in the current overlap region DCUR to
narrow SOA.
[0041] FIG. 4 shows a path of current CUR when the current CUR
flows from the drain to the source in the semiconductor device SC
shown in FIG. 1 and FIG. 2. In this embodiment, when a voltage
higher than a threshold voltage is applied to the gate electrode
GE, a channel is formed only in the portion of the base layer BSE
situated on one lateral side of the trench TRN. Accordingly,
currents CUR flowing by way of different channels are suppressed
from overlapping each other. Therefore, increase in the
on-resistance of the drain can be suppressed. Further, since
generation of the current overlap region DCUR can be suppressed,
narrowing of SOA can be suppressed.
[0042] Further, when a parasitic bipolar transistor comprising the
source layer SOU, the base layer BSE, and the n-type epitaxial
layer NEP operates, SOA of the semiconductor device SC is narrowed.
When the width of the source layer SOU in the direction
perpendicular to the trench TRN is 1.0 .mu.m or less, operation of
the parasitic bipolar transistor can be suppressed. Accordingly,
narrowing of SOA can be suppressed.
[0043] A graph in FIG. 5 shows a relation between a drain current
value and a specific resistivity (Rsp) per unit area when the
temperature reaches 150.degree. C. in the vertical transistor PTR
according to this embodiment (described as one side channel) and
vertical transistor PTR of the structure shown in FIG. 3 (described
as both side channel) respectively. It can be seen from the graph
that the vertical transistor PTR according to this embodiment
generates less amount of heat when an identical current is supplied
and also shows low on-resistance of the drain when the identical
current is supplied compared with the vertical transistor PTR shown
in FIG. 3.
[0044] Further, different from Japanese Unexamined Patent
Application Publication No. 2000-353805 and Japanese Unexamined
Patent Application Publication (Translation of PCT Application) No.
2004-513518, impurity layers other than the second conduction type
high concentration layer HIN and the source layer SOU are not
formed in the base layer BSE of the vertical transistor PTR.
Accordingly, increase in the size of the vertical transistor PTR
can be suppressed.
Second Embodiment
[0045] FIG. 6 is a plan view of a semiconductor device SC according
to a second embodiment. In the semiconductor device SC, vertical
transistors PTR and a logic transistor LTR are formed over an
identical substrate and used, for example, as intelligent power
device (IPD). The semiconductor device SC may have one vertical
transistor PTR or multiple PTRs as shown in the drawing. The logic
transistor LTR provides a control circuit for the vertical
transistors PTR.
[0046] FIG. 7 is a cross sectional view showing a structure of the
semiconductor device SC shown in FIG. 6. The vertical transistors
PTR and the logic transistor LTR are isolated from each other by a
device isolation films LCS. The device isolation film LCS is
formed, for example, by a LOCOS oxidation method or may also be
formed by an STI method of filling a device isolation film in a
trench.
[0047] The structure of the vertical transistor PTR is identical
with that of the first embodiment. Further, a method of
manufacturing the vertical transistor PTR to be described later is
identical with the manufacturing method of the first
embodiment.
[0048] The logic transistor LTR is formed in the epitaxial layer
EPI. The logic transistor LTR shown in the drawing is a planar type
MIS transistor. The logic transistor LTR may also be a fin type MIS
transistor.
[0049] More specifically, a p-type well WEL is formed in the
epitaxial layer EPI. The well WEL is formed in a region in which
the logic transistor LTR is formed and at the periphery of the
vertical transistor PTR. A source-drain layer SD of the logic
transistor LTR is formed in the portion of the well WEL situated in
a region where the logic transistor LTR is formed. The source-drain
layer SD has a lightly doped drain (LDD) region.
[0050] The logic transistor LTR has, in addition to the source
drain layer SD, a gate insulating film GIN2, a gate electrode GE2,
and a side wall SW. The gate insulating film GIN2 is formed over
the epitaxial layer EPI. The gate electrode GE2 is situated over
the gate insulating film GIN2. The side wall SW covers the lateral
side of the gate electrode GE2. The logic transistor LTR is not
restricted to the illustrated planar type (lateral type) MIS
transistor but may be configured also as an LDMIS transistor
(Laterally Diffused MIS transistor) structure that moderates an
electric field strength between the drain and the gate. Further, a
planar type MIS transistor and an LDMIS transistor may be
hybridized together over an identical semiconductor substrate
SUB.
[0051] Multiple interconnects ITC are formed in a layer identical
with the source electrode EL2. The interconnects ITC are coupled by
way of contacts CON to the source drain layers SD or the gate
electrode GE2.
[0052] FIG. 8 to FIG. 12 are cross sectional views showing a method
of manufacturing the semiconductor device SC shown in FIG. 6 and
FIG. 7. At first, as shown in FIG. 8, an epitaxial layer EPI is
formed over a substrate WFR. Then, a well WEL is formed by
implanting a p-type impurity into the epitaxial layer EPI. Then, a
mask film MSK1 is formed over the epitaxial layer EPI. The mask
film MSK1 is, for example, a silicon nitride film and has an
opening in a region in which a device isolation film LSC is to be
formed. Then, the epitaxial layer EPI is thermally oxidized by
using the mask film MSK1 as a mask. Thus, a device isolation film
LSC is formed.
[0053] Then, as shown in FIG. 9, a mask film MSK2 is formed over
the mask film MSK1 and over the device isolation film LCS. The mask
film MSK2 is, for example, a silicon oxide film and has an opening
in a region where the trenches TRM are to be formed. Then, the mask
MSK1 and the epitaxial layer EPI are etched by using the mask film
MSK2 as a mask to form stripe-patterned trenches extending parallel
to each other. Thus, multiple trenches TRN are formed in the
epitaxial layer EPI.
[0054] Then, as shown in FIG. 10, the mask film MSK1 and the mask
film MSK2 are removed. Then, the surface layer of the epitaxial
layer EPI (including the lateral sides and the bottoms of the
trenches TRN) is thermally oxidized. Thus, a gate insulating film
GIN and a gate insulating film GIN2 are formed. When the thickness
of the gate insulating film GIN and that of the gate insulating
film GIN2 are different, the gate insulating film GIN and the gate
insulating film GIN2 may be formed by thermal oxidation steps
different from each other. Further, the steps may also be designed
such that the thermal oxidation of forming a thicker film (for
example, gate insulating film GIN) is made longer.
[0055] Then, an electroconductive film is formed in the trench TRN
and over the epitaxial layer EPI. Then, the electroconductive film
is removed selectively. Thus, the gate electrode GE and the gate
electrode GE2 are formed.
[0056] Then, as shown in FIG. 11, a p-type impurity is implanted
into the epitaxial layer EPI. Thus, a base layer BSE is formed. A
region of the epitaxial layer EPI which is not formed as the base
layer BSE remains as an n-type epitaxial layer NEP.
[0057] Then, as shown in FIG. 12, an n-type impurity is implanted
into the well WEL. Thus, an LDD region of the logic transistor LTR
is formed. Then, a side wall SW is formed on the lateral side of
the gate electrode GE2. Then, an n-type impurity is implanted into
the well WEL and the base layer BSE. Thus, the source drain layer
SD and the source layer SOU are formed. Further, a p-type impurity
is implanted into the base layer BSE. Thus, a second conduction
type high concentration layer HIN is formed.
[0058] Subsequently, a drain electrode ELL an interlayer insulating
film INS, contacts CON, and a source electrode EL2 are formed.
Thus, the semiconductor device SC shown in FIG. 6 and FIG. 7 is
formed.
[0059] Also in this embodiment, the same effect as that of the
first embodiment can be obtained. Further, the vertical transistors
PTR and the control circuit for the vertical transistors PTR can be
formed over an identical semiconductor substrate SUB.
Third Embodiment
[0060] FIG. 13 is a cross sectional view showing a configuration of
a semiconductor device SC according to a third embodiment. The
semiconductor device SC according to this embodiment has the same
configuration as that of the semiconductor device SC according to
the first or second embodiment except for having a field plate
insulating film FP. The drawing shows a case identical with the
second embodiment.
[0061] In the field plate insulating film FP, the thickness of the
gate insulating film situated in the lower lateral side of the
trench TRN is larger than that of the gate insulating film situated
in the upper lateral side. The field plate insulating film FP is
formed by making the thermal oxidation time longer for the bottom
of the trench TRN in the thermal oxidation step for forming the
gate insulating film GIN and the gate insulating film GIN2.
[0062] Also in this embodiment, the same effect as that of the
second embodiment can be obtained. Further, the field plate
insulating film FP is formed to the lower lateral wall of the
trench TRN. The thickness of the field plate insulating film FP is
larger than that of the gate insulating film GIN. Accordingly,
lowering of the drain withstand voltage of the vertical transistor
PTR caused by concentration of electric fields to the lower portion
of the trench TRN can be suppressed. Further, a parasitic
capacitance formed between adjacent gate electrodes GE is also
lowered.
Fourth Embodiment
[0063] FIG. 14 is a cross sectional view showing a configuration of
a semiconductor device SC according to a fourth embodiment. A
semiconductor device SC according to this embodiment has the
configuration identical with that of the semiconductor device SC
according to the third embodiment except for having a silicide
layer SIL.
[0064] The silicide layer SIL is formed continuously over the
source layer SOU and over the second conduction type high
concentration HIN. The silicide layer SIL is formed also over the
gate electrode GE, over the source-drain layer GE2, and over the
gate electrode GD.
[0065] The method of manufacturing the semiconductor device SC
according to this embodiment is identical with the method of
manufacturing the semiconductor device SC according to the third
embodiment except for having a step of forming the silicide layer
SIL after forming the source-drain layer SD, the source layer SOU,
and the second conduction type high concentration layer HIN and
before forming the interlayer insulating film INS. The silicide
layer SIL is formed by forming a metal layer that serves as the
silicide layer SIL (for example, Ti, Ni, or Co) over the epitaxial
layer EPI and over the gate electrode GE2, and then applying a heat
treatment. A remaining portion of metal not forming the silicide
layer SIL is removed by etching.
[0066] Also in this embodiment, the same effect as that of the
third embodiment can be obtained. Further, the source layer SOU and
the second conduction type high concentration layer HIN are coupled
by the silicide layer SIL. Accordingly, generation of difference in
the potential between the source layer SOU and the second
conduction type high concentration layer HIN, that is, generation
of the potential between the source layer SOU and the base layer
BSE can be suppressed. Accordingly, operation of a parasitic
bipolar transistor comprising the source layer SOU, the base layer
BSE, and the n-type epitaxial layer NEP can be suppressed. As a
result, narrowing of SOA of the semiconductor device SC can be
suppressed.
Fifth Embodiment
[0067] FIG. 15 is a cross sectional view showing a structure of a
semiconductor device SC according to a fifth embodiment. The
semiconductor device SC according to this embodiment has a
configuration identical with that of the semiconductor device SC
according to the fourth embodiment excepting that the bottom of the
trench TRN is filled with a field plate insulating film FP. Such a
structure can be achieved by narrowing the width of the trench TRN,
for example, to 0.3 .mu.m or less.
[0068] Also in this embodiment, the same effect as that of the
fourth embodiment can be obtained. Further, since the gate
electrode GE is not situated at the bottom of the trench TRN, a
parasitic capacitance generated between adjacent gate electrodes GE
can be lowered further.
Sixth Embodiment
[0069] A peripheral portion of a vertical transistor PTR forming
region is to be described. FIG. 16 is a plan view showing a
structure of a semiconductor device SC according to a sixth
embodiment. FIG. 17A is a cross sectional view along line A-A' in
FIG. 16 and FIG. 17B is a cross sectional view along line B-B' in
FIG. 16. The semiconductor device SC according to this embodiment
has a configuration identical with one of the first to fifth
embodiments except for the followings.
[0070] At first, the source layers SOU and the second conduction
type high concentration layers HIN are arranged alternately in the
direction where the trench TRN and the gate electrode GE extend.
The width of the source layer SOU is larger than the width of the
second conduction type high concentration layer HIN in the
direction where the trench TRN and the gate electrode GE
extend.
[0071] Then, in a certain portion (for example, along cross section
shown B-B in FIG. 17B), both of lateral sides of the trench TRN
face the source layers SOU. The source layer SOU is divided into
multiple regions by the trenches TRN and the gate electrodes GE.
Contacts CON for coupling the source layer SOU and the source
electrode EL2 are disposed on every other of the divided source
layers SOU when viewed in the direction perpendicular to the trench
TRN and the gate electrode GE. That is, the source layer SOU facing
the one lateral side is coupled by way of the contact CON to the
source electrode EL2 but the source layer SOU facing the other
lateral side is not coupled to the source electrode EL2 but is in a
floating state. Also in such a structure, the channel is formed
only to the portion of the base layer BSE situated on the one
lateral side of the trench TRN.
[0072] The well WEL is formed also to a position surrounding the
periphery of the base layer BSE. The trench TRN and the gate
electrode GE are formed in the well WEL. The gate electrode GE in
the well WEL is used as a portion of a gate interconnect. That is,
the gate electrode GE of the vertical transistor PTR is applied
with a potential by way of the gate electrode GE in the well
WEL.
[0073] Also in this embodiment, the same effect as that of the
first to fifth embodiments can be obtained.
Seventh Embodiment
[0074] FIG. 18 is a view showing a configuration of a circuit of an
electronic device according to a seventh embodiment. The electronic
device is used, for example, for vehicles such as automobiles and
has an electronic device ED, a power source BAT, and a load LD. The
power source BAT is, for example, a battery mounted on a vehicle.
The load LD is an electronic part, for example, an electronic part
mounted on the vehicle, such as a head lump. The electronic device
ED controls power supplied from the electric source BAT to the load
LD.
[0075] The electronic device ED comprises a semiconductor device SC
and a semiconductor device MCP mounted over a circuit substrate
(for example, printed wiring board). The semiconductor device SC
has a structure shown in one of the first to sixth embodiments. The
semiconductor device MCP is a microcomputer which is connected by
way of interconnects of the circuit substrate to the logic
transistor LPR of the semiconductor device SC. The semiconductor
device MCP controls the semiconductor device SC. Specifically, the
semiconductor device MCP inputs a control signal to the logic
transistor LTR. The logic transistor LTR inputs a signal to the
gate electrode GE of the vertical transistor PTR in accordance with
the control signal inputted from the semiconductor device MCP. By
the control of the vertical transistor PTR, power from the electric
source BAT is supplied appropriately to the load LD. This
embodiment can improve SOA of the semiconductor device SC and can
improve the device characteristics of the electronic device ED
having the semiconductor device SC. Further, the embodiment can
improve the characteristics of the electronic system using the
semiconductor device SC.
[0076] The invention made by the present inventors has been
described specifically based on the preferred embodiments but it
will be apparent that the invention is not restricted to the
embodiments but can be modified variously within a range not
departing the gist of the invention.
* * * * *