U.S. patent application number 14/422365 was filed with the patent office on 2016-01-21 for cmos transistor and method for fabricating the same, display panel and display device.
The applicant listed for this patent is BOE TECHNOLOGY GROUP CO., LTD.. Invention is credited to Chunsheng JIANG.
Application Number | 20160020228 14/422365 |
Document ID | / |
Family ID | 50362117 |
Filed Date | 2016-01-21 |
United States Patent
Application |
20160020228 |
Kind Code |
A1 |
JIANG; Chunsheng |
January 21, 2016 |
CMOS TRANSISTOR AND METHOD FOR FABRICATING THE SAME, DISPLAY PANEL
AND DISPLAY DEVICE
Abstract
The present invention provides a CMOS transistor and a method
for fabricating the same, a display panel and a display device. The
CMOS transistor comprises a first region and a second region
provided on a base substrate, the first region comprises a first
gate electrode, a first active layer, a first source electrode and
a first drain electrode, and the second region comprises a second
gate electrode, a second active layer, a second source electrode
and a second drain electrode, first dopant ions are formed in the
first active layer, second dopant ions are formed in the second
active layer, a concentration of the first dopant ions is smaller
than that of the second dopant ions, the first active layer is an
n-type active layer, and the second active layer is a p-type active
layer. The technical solution of the present invention can reduce
power consumption of display panel.
Inventors: |
JIANG; Chunsheng; (Beijing,
CN) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
BOE TECHNOLOGY GROUP CO., LTD. |
Beijing |
|
CN |
|
|
Family ID: |
50362117 |
Appl. No.: |
14/422365 |
Filed: |
March 25, 2014 |
PCT Filed: |
March 25, 2014 |
PCT NO: |
PCT/CN2014/074038 |
371 Date: |
February 19, 2015 |
Current U.S.
Class: |
257/43 ;
438/104 |
Current CPC
Class: |
H01L 27/1259 20130101;
H01L 27/127 20130101; H01L 27/1288 20130101; H01L 27/092 20130101;
H01L 27/1225 20130101; H01L 29/36 20130101; H01L 29/22
20130101 |
International
Class: |
H01L 27/12 20060101
H01L027/12; H01L 29/22 20060101 H01L029/22; H01L 27/092 20060101
H01L027/092; H01L 29/36 20060101 H01L029/36 |
Foreign Application Data
Date |
Code |
Application Number |
Dec 26, 2013 |
CN |
201310732715.1 |
Claims
1-18. (canceled)
19. A CMOS transistor, comprising a first region and a second
region provided on a base substrate, the first region comprising a
first gate electrode, a first active layer, a first source
electrode and a first drain electrode, and the second region
comprising a second gate electrode, a second active layer, a second
source electrode and a second drain electrode, wherein first dopant
ions are formed in the first active layer, second dopant ions are
formed in the second active layer, and a concentration of the first
dopant ions is smaller than that of the second dopant ions; the
first active layer is an n-type active layer, and the second active
layer is a p-type active layer.
20. The CMOS transistor of claim 19, wherein an etch stop layer is
formed between the first active layer and the first source and
drain electrodes and between the second active layer and the second
source and drain electrodes.
21. The CMOS transistor of claim 19, wherein the first active layer
and the second active layer are oxide material layer.
22. The CMOS transistor of claim 21, wherein the oxide material
layer is zinc oxide layer.
23. The CMOS transistor of claim 20, wherein a first via hole, a
second via hole, a third via hole and a fourth via hole are formed
in the etch stop layer, the first source electrode and the first
drain electrode are connected with the first active layer through
the first via hole and the second via hole, respectively, and the
second source electrode and the second drain electrode are
connected with the second active layer through the third via hole
and the fourth via hole, respectively.
24. The CMOS transistor of claim 19, wherein the first dopant ions
and the second dopant ions are both N ions.
25. A display device, comprising a display panel, the display panel
comprising CMOS transistors, the CMOS transistor comprising a first
region and a second region provided on a base substrate, the first
region comprising a first gate electrode, a first active layer, a
first source electrode and a first drain electrode, and the second
region comprising a second gate electrode, a second active layer, a
second source electrode and a second drain electrode, wherein first
dopant ions are formed in the first active layer, second dopant
ions are formed in the second active layer, and a concentration of
the first dopant ions is smaller than that of the second dopant
ions; the first active layer is an n-type active layer, and the
second active layer is a p-type active layer.
26. The display device of claim 25, wherein an etch stop layer is
formed between the first active layer and the first source and
drain electrodes and between the second active layer and the second
source and drain electrodes.
27. The display device of claim 25, wherein the first active layer
and the second active layer are oxide material layer.
28. The display device of claim 25, wherein the first dopant ions
and the second dopant ions are both N ions.
29. A method for fabricating a CMOS transistor, comprising steps
of: forming a first gate electrode, a second gate electrode, a
first active layer, a second active layer, a first source
electrode, a second source electrode, a first drain electrode and a
second drain electrode on a base substrate; and injecting first
dopant ions into the first active layer and injecting second dopant
ions into the second active layer by a doping process, wherein a
concentration of the first dopant ions is smaller than that of the
second dopant ions, the first active layer is an n-type active
layer, and the second active layer is a p-type active layer.
30. The method for fabricating the CMOS transistor of claim 29,
wherein the step of forming a first gate electrode, a second gate
electrode, a first active layer, a second active layer, a first
source electrode, a second source electrode, a first drain
electrode and a second drain electrode on a base substrate
comprises: forming the first gate electrode and the second gate
electrode on the base substrate by a patterning process; forming
the first active layer and the second active layer on the base
substrate on which the first gate electrode and the second gate
electrode are formed; and forming the first source electrode, the
second source electrode, the first drain electrode and the second
drain electrode on the first active layer and the second active
layer by a patterning process.
31. The method for fabricating the CMOS transistor of claim 29,
wherein a planarization layer is formed on the first source
electrode, the second source electrode, the first drain electrode
and the second drain electrode before injecting the dopant ions;
the step of injecting first dopant ions into the first active layer
and injecting second dopant ions into the second active layer by a
doping process comprises: forming a photoresist layer on the
planarization layer, the photoresist layer comprising a first
photoresist region and a second photoresist region, the first
photoresist region corresponding to the first active layer, and the
second photoresist region corresponding to the second active layer;
performing the doping process on the first active layer through the
first photoresist region to inject N ions into the first active
layer; performing the doping process on the second active layer
through the second photoresist region to inject N ions into the
second active layer; and removing the photoresist layer.
32. The method for fabricating the CMOS transistor of claim 31,
wherein the step of forming the photoresist layer on the
planarization layer comprises: applying photoresist on the
planarization layer; and performing mask plate masking and exposure
by using a half tone mask and performing development to form the
first photoresist region and the second photoresist region.
33. The method for fabricating the CMOS transistor of claim 32,
wherein a thickness of the first photoresist region is larger than
that of the second photoresist region.
34. The method for fabricating the CMOS transistor of claim 33,
wherein the thickness of the photoresist layer is equal to or
larger than 3 .mu.m, the thickness of the first photoresist region
is ranged from 1.7 .mu.m to 2.3 .mu.m, and the thickness of the
second photoresist region is ranged from 0.7 .mu.m to 1.3
.mu.m.
35. The method for fabricating the CMOS transistor of claim 29,
wherein the first active layer and the second active layer are made
of oxide material.
36. The method for fabricating the CMOS transistor of claim 35,
wherein the oxide material is zinc oxide.
37. The method for fabricating the CMOS transistor of claim 29,
wherein before forming the first source electrode, the second
source electrode, the first drain electrode and the second drain
electrode, an etch stop layer is formed on the first active layer
and the second active layer by a patterning process, and a first
via hole, a second via hole, a third via hole and a fourth via hole
are formed in the etch stop layer, so that the first source
electrode and the first drain electrode are connected with the
first active layer through the first via hole and the second via
hole, respectively, and the second source electrode and the second
drain electrode are connected with the second active layer through
the third via hole and the fourth via hole, respectively.
38. The method for fabricating the CMOS transistor of claim 29,
wherein the first dopant ions and the second dopant ions are both N
ions.
Description
FIELD OF THE INVENTION
[0001] The present invention relates to the field of touch panel
technology, and particularly to a CMOS transistor and a method for
fabricating the same, a display panel and a display device.
BACKGROUND OF THE INVENTION
[0002] Complementary metal oxide semiconductor (referred to as
CMOS) consists of positive channel metal oxide semiconductor
(referred to as PMOS) and negative channel metal oxide
semiconductor (referred to as NMOS). CMOS has a characteristic of
low power consumption and is widely used in integrated
circuits.
[0003] A bottom gate type thin film transistor formed by six mask
patterning processes in the prior art comprises a switching thin
film transistor and a driving thin film transistor formed
simultaneously on a base substrate, the switching thin film
transistor comprises a gate electrode, a gate insulation layer, an
active layer, an etch stop layer, source and drain electrodes, a
passivation layer, a first channel and a pixel electrode, and the
driving thin film transistor comprises a gate electrode, a
passivation layer, a second channel and a pixel electrode, so that
a jump layer connection between the switching thin film transistor
and the driving thin film transistor is implemented, but such a
structure may increase power consumption when applied to a display
panel.
SUMMARY OF THE INVENTION
[0004] The present invention provides a CMOS transistor and a
method for fabricating the same, a display panel and a display
device, which may reduce the power consumption of the display
panel.
[0005] To achieve the above objective, the present invention
provides a CMOS transistor comprising a first region and a second
region provided on a base substrate, the first region comprises a
first gate electrode, a first active layer, a first source
electrode and a first drain electrode, and the second region
comprises a second gate electrode, a second active layer, a second
source electrode and a second drain electrode, first dopant ions
are formed in the first active layer, second dopant ions are formed
in the second active layer, a concentration of the first dopant
ions is smaller than that of the second dopant ions, the first
active layer is an n-type active layer, and the second active layer
is a p-type active layer.
[0006] Optionally, an etch stop layer is further formed between the
first active layer and the first source electrode and the first
drain electrode and between the second active layer and the second
source electrode and the second drain electrode.
[0007] Optionally, the first active layer is oxide material layer,
and the second active layer is oxide material layer.
[0008] Optionally, the oxide material is zinc oxide.
[0009] Optionally, a first via hole, a second via hole, a third via
hole and a fourth via hole are formed in the etch stop layer, the
first source electrode and the first drain electrode are connected
with the first active layer through the first via hole and the
second via hole, respectively, and the second source electrode and
the second drain electrode are connected with the second active
layer through the third via hole and the fourth via hole,
respectively.
[0010] Optionally, the first dopant ions and the second dopant ions
are both N ions.
[0011] To achieve the above objective, the present invention
provides a display panel, comprising the above CMOS transistor.
[0012] To achieve the above objective, the present invention
provides a display device, comprising the above display panel. To
achieve the above objective, the present invention provides a
method for fabricating a CMOS transistor, comprising steps of:
forming a first gate electrode, a second gate electrode, a first
active layer, a second active layer, a first source electrode, a
second source electrode, a first drain electrode and a second drain
electrode on a base substrate; and injecting first dopant ions into
the first active layer and injecting second dopant ions into the
second active layer by a doping process, a concentration of the
first dopant ions is smaller than that of the second dopant ions,
the first active layer is an n-type active layer, and the second
active layer is a p-type active layer.
[0013] Optionally, the step of forming a first gate electrode, a
second gate electrode, a first active layer, a second active layer,
a first source electrode, a second source electrode, a first drain
electrode and a second drain electrode on a base substrate
comprises: forming the first gate electrode and the second gate
electrode on the base substrate by a patterning process; forming
the first active layer and the second active layer on the base
substrate on which the first gate electrode and the second gate
electrode are formed; and forming the first source electrode, the
second source electrode, the first drain electrode and the second
drain electrode on the first active layer and the second active
layer by a patterning process.
[0014] Optionally, a planarization layer is formed on the first
source electrode, the second source electrode, the first drain
electrode and the second drain electrode before injecting the
dopant ions; the step of injecting first dopant ions into the first
active layer and injecting second dopant ions into the second
active layer by a doping process comprises: forming a photoresist
layer on the planarization layer, the photoresist layer comprising
a first photoresist region and a second photoresist region, the
first photoresist region corresponding to the first active layer,
and the second photoresist region corresponding to the second
active layer; performing the doping process on the first active
layer through the first photoresist region to inject N ions into
the first active layer; performing the doping process on the second
active layer through the second photoresist region to inject N ions
into the second active layer; and removing the photoresist
layer.
[0015] Optionally, the step of forming the photoresist layer on the
planarization layer comprises: applying photoresist on the
planarization layer; and performing mask plate masking and exposure
by using a half tone mask and performing development to form the
first photoresist region and the second photoresist region.
[0016] Optionally, a thickness of the first photoresist region is
larger than that of the second photoresist region.
[0017] Optionally, the thickness of the photoresist layer is equal
to or larger than 3 .mu.m, the thickness of the first photoresist
region is ranged from 1.7 .mu.m to 2.3 .mu.m, and the thickness of
the second photoresist region is ranged from 0.7 .mu.m to 1.3
.mu.m.
[0018] Optionally, the first active layer and the second active
layer are made of oxide material.
[0019] Optionally, the oxide material is zinc oxide.
[0020] Optionally, before forming the first source electrode, the
second source electrode, the first drain electrode and the second
drain electrode, an etch stop layer is formed on the first active
layer and the second active layer by a patterning process, and a
first via hole, a second via hole, a third via hole and a fourth
via hole are formed in the etch stop layer, so that the first
source electrode and the first drain electrode are connected with
the first active layer through the first via hole and the second
via hole, respectively, and the second source electrode and the
second drain electrode are connected with the second active layer
through the third via hole and the fourth via hole,
respectively.
[0021] Optionally, the first dopant ions and the second dopant ions
are both N ions.
[0022] In the CMOS transistor and the method for fabricating the
same, the display panel and the display device, the concentration
of the first dopant ions is smaller than that of the second dopant
ions, and the first active layer is an n-type active layer and the
second active layer is a p-type active layer, which may reduce the
power consumption of the display panel.
BRIEF DESCRIPTION OF THE DRAWINGS
[0023] FIG. 1 is a schematic diagram of a structure of a CMOS
transistor according to a first embodiment of the present
invention;
[0024] FIG. 2 is a flow chart of a method for fabricating a CMOS
transistor, according to a second embodiment of the present
invention;
[0025] FIG. 3a is a schematic diagram illustrating forming a first
gate electrode, a second gate electrode, a first active layer, a
second active layer and a gate insulation layer in the method for
fabricating the CMOS transistor;
[0026] FIG. 3b is a schematic diagram illustrating forming a first
source electrode, a first drain electrode, a second source
electrode and a second drain electrode in the method for
fabricating the CMOS transistor;
[0027] FIG. 3c is a schematic diagram illustrating forming a
photoresist layer in the method for fabricating the CMOS
transistor;
[0028] FIG. 3d is a schematic diagram illustrating ion implantation
in the method for fabricating the CMOS transistor;
[0029] FIG. 3e is a schematic diagram illustrating removing the
photoresist layer in the method for fabricating the CMOS
transistor.
DESCRIPTION OF THE PREFERRED EMBODIMENT
[0030] To make those skilled in the art better understand the
technical solutions of the present invention, the CMOS transistor
and the method for fabricating the same, the display panel and the
display device provided by the present invention will be described
as below in details in conjunction with the accompanying
drawings.
[0031] FIG. 1 is a schematic diagram of a structure of a CMOS
transistor according to a first embodiment of the present
invention. As shown in FIG. 1, the CMOS transistor comprises a
first region and second region provided on a base substrate 1, the
first region comprises a first gate electrode 31, a first active
layer 41, a first source electrode 61 and a first drain electrode
71 provided on the base substrate 1, and the second region
comprises a second gate electrode 32, a second active layer 42, a
second source electrode 62 and a second drain electrode 72 provided
on the base substrate 1. In the transistor, first dopant ions are
formed in the first active layer 41, second dopant ions are formed
in the second active layer 42, and a concentration of the first
dopant ions is smaller than that of the second dopant ions. For
example, both of the first dopant ions and the second dopant ions
are N ions. In the transistor, the first active layer 41 is an
n-type active layer, the second active layer 42 is a p-type active
layer, the first region is a NMOS region, and the second region is
a PMOS region. The transistor according to the embodiment of the
present invention can reduce power consumption of a display
panel.
[0032] Preferably, an etch stop layer 5 is formed between the first
active layer 41 and the first source and drain electrodes 61, 71
and between the second active layer 42 and the second source and
drain electrodes 62, 72. The first active layer 41 is an oxide
material layer, and the second active layer 42 is an oxide material
layer. Further, the oxide material is zinc oxide. Since the first
active layer 41 and the second active layer 42 are both oxide
material layer and the oxide material has a disadvantage of
corrosion intolerance, the etch stop layer 5 is formed on the first
and second active layers 41, 42 for protection. In addition, in
practical application, since the active layer (oxide material
layer) is likely to be damaged during etching the source and drain
electrodes, the etch stop layer is required to be formed on the
active layer firstly and then the source and drain electrodes are
fabricated.
[0033] Preferably, a gate insulation layer 2 is formed between the
first gate electrode 31 and the first active layer 41 and between
the second gate electrode 32 and the second active layer 42, and
the first gate electrode 31 and the second gate electrode 32 are
formed on the base substrate 1.
[0034] Preferably, a first via hole, a second via hole, a third via
hole and a fourth via hole are formed in the etch stop layer 5. A
position of the first via hole corresponds to the first source
electrode 61 and the first active layer 41, a position of the
second via hole corresponds to the first drain electrode 71 and the
first active layer 41, a position of the third via hole corresponds
to the second source electrode 62 and the second active layer 42,
and a position of the fourth via hole corresponds to the second
drain electrode 72 and the second active layer 42, so that the
first source and drain electrodes 61, 71 are connected with the
first active layer 41 through the first and second via holes,
respectively, and the second source and drain electrodes 62, 72 are
connected with the second active layer 42 through the third and
fourth via holes, respectively. After the etch stop layer 5 is
fabricated on the first active layer 41 and the second active layer
42, the first via hole, the second via hole, the third via hole and
the fourth via hole are formed in the etch stop layer 5 by a dry
etching or other method, and then the first source electrode 61,
the second source electrode 62, the first drain electrode 71 and
the second drain electrode 72 are formed on the etch stop layer 5
by a patterning process.
[0035] In the embodiment, the structure of CMOS transistor includes
a bottom gate type structure and a top gate type structure. The
bottom gate type structure comprises a NMOS region 10 and a PMOS
region 11, the NMOS region 10 comprises the first gate electrode
31, the gate insulation layer 2, the first active layer 41, the
etch stop layer 5, the first source electrode 61 and the first
drain electrode 71 sequentially provided from a side of the base
substrate 1 for providing the CMOS transistor, and the PMOS region
11 comprises the second gate electrode 32, the gate insulation
layer 2, the second active layer 42, the etch stop layer 5, the
second source electrode 62 and the second drain electrode 72
sequentially provided from the side of the base substrate 1. The
top gate type structure comprises a NMOS region 10 and a PMOS
region 11, the NMOS region 10 comprises the first active layer 41,
the etch stop layer 5, the first source electrode 61 and the first
drain electrode 71, the gate insulation layer 2 and the first gate
electrode 31 sequentially provided from a side of the base
substrate 1 for providing the CMOS transistor, and the PMOS region
11 comprises the second active layer 42, the etch stop layer 5, the
second source electrode 62 and the second drain electrode 72, the
gate insulation layer 2 and the second gate electrode 32
sequentially provided from the side of the base substrate 1.
[0036] It should be noted that, the CMOS transistor in the
embodiment of the present invention is described by taking the
bottom gate type thin film transistor (i.e., the gate electrode is
provided below the pattern of active layer) as an example, and it
is merely an exemplary description, the scope of the present
invention is not limited thereto. The structure of the CMOS
transistor may be varied according to a requirement in practical
application, for example, the CMOS transistor in the technical
solution of the present invention may also utilize the top gate
type thin film transistor (i.e., the gate electrode is provided
above the active layer). In the case where the CMOS transistor in
the technical solution of the present invention is the top gate
type thin film transistor, the gate insulation layer 2 is formed
between the first gate electrode 31 and the first source and drain
electrodes 61, 71 and between the second gate electrode 32 and the
second source and drain electrodes 62, 72, and the first gate
electrode 31 and the second gate electrode 32 are both formed above
the gate insulation layer 2.
[0037] FIG. 2 is a flow chart of a method for fabricating a CMOS
transistor, according to a second embodiment of the present
invention. As shown in FIG. 2, the method comprises the following
steps.
[0038] In step S11, a first gate electrode, a second gate
electrode, a first active layer, a second active layer, a first
source electrode, a second source electrode, a first drain
electrode and a second drain electrode are formed on a base
substrate.
[0039] Specifically, by taking a bottom gate type thin film
transistor as an example, step S11 may comprise the following
steps.
[0040] In step S111, the first gate electrode and the second gate
electrode are formed on the base substrate by a patterning
process.
[0041] In step S112, the first active layer and the second active
layer are formed on the base substrate on which the first gate
electrode and the second gate electrode are formed, by a patterning
process.
[0042] Before step S112, the method further comprises forming a
gate insulation layer on the first gate electrode and the second
electrode. After the gate insulation layer is formed, the first
active layer and the second active layer are respectively formed on
the regions of the gate insulation layer corresponding to the first
gate electrode and the second gate electrode by a patterning
process.
[0043] FIG. 3a is a schematic diagram illustrating forming a first
gate electrode 31, a second gate electrode 32, a first active layer
41, a second active layer 42 and a gate insulation layer 2 in the
method for fabricating the CMOS transistor. As shown in FIG. 3a, a
gate metal material layer is deposited on two regions (a first
region and a second region) on a base substrate 1, and the first
gate electrode 31 and the second gate electrode 32 are formed by a
patterning process, respectively; the gate insulation layer 2 is
deposited on the first gate electrode 31 and the second gate
electrode 32; an active metal oxide material layer is deposited on
the regions of the gate insulation layer 2 corresponding to the
first gate electrode 31 and the second gate electrode 32, the
active metal oxide material is preferably zinc oxide, and the first
active layer 41 and the second active layer 42 are formed by a
patterning process, respectively.
[0044] In step S113, the first source electrode, the second source
electrode, the first drain electrode and the second drain electrode
are formed on the first active layer and the second active layer by
a patterning process.
[0045] FIG. 3b is a schematic diagram illustrating forming the
first source electrode 61, the first drain electrode 71, the second
source electrode 62 and the second drain electrode 72 in the method
for fabricating the CMOS transistor. As shown in FIG. 3b, a source
and drain metal material layer is deposited on the first active
layer 41 and the second active layer 42, and the first source
electrode 61, the first drain electrode 71, the second source
electrode 62 and the second drain electrode 72 are formed by a
patterning process, respectively. In the embodiment, the patterning
process may at least include photoresist coating, mask plate
masking, exposure, development and photoresist stripping.
[0046] Preferably, between step S112 and step S113, the method
further comprises forming an etch stop layer on the first active
layer and the second active layer by a patterning process. After
the etch stop layer is formed, the first source electrode, the
second source electrode, the first drain electrode and the second
drain electrode are formed on the etch stop layer by a patterning
process.
[0047] In step S12, first dopant ions are injected into the first
active layer and second dopant ions are injected into the second
active layer, by a doping process, a concentration of the first
dopant ions is smaller than that of the second dopant ions.
[0048] Specifically, the first active layer 41 and the second
active layer 42 are both zinc oxide material layer. The first
dopant ions and the second dopant ions are both N ions. During
injecting the first dopant ions into the first active layer 41 and
injecting the second dopant ions into the second active layer 42 by
the doping process, does and energy of ion implantation for the
first active layer 41 and the second active layer 42 are
respectively controlled according to concentrations of zinc oxide
in the first active layer 41 and the second active layer 42, so as
to obtain the first dopant ions and the second dopant ions with
different concentrations of dopant ions and allow the concentration
of the first dopant ions to be smaller than that of the second
dopant ions. After the doping process, the first active layer 41 is
an N type active layer, and the second active layer 42 is a P type
active layer.
[0049] Preferably, between step S11 and step S12, the method
further comprises forming a planarization layer 8 on the first
source electrode 61, the second source electrode 62, the first
drain electrode 71 and the second drain electrode 72, as shown in
FIG. 3b.
[0050] Specifically, step S12 may comprise the following steps.
[0051] In step S121, a photoresist layer is formed on the
planarization layer 8, the photoresist layer includes a first
photoresist region and a second photoresist region, the first
photoresist region corresponds to the first active layer, and the
second photoresist region corresponds to the second active
layer.
[0052] FIG. 3c is a schematic diagram illustrating forming a
photoresist layer in the method for fabricating the CMOS
transistor. As shown in FIG. 3c, specifically, forming the
photoresist layer on the planarization layer 8 comprises: applying
a photoresist layer on the planarization layer 8, a thickness of
the photoresist layer being equal to or larger than 3 .mu.m; and
performing mask plate masking and exposure on the photoresist layer
by using a half tone mask plate and performing development to form
the first photoresist region 91 and the second photoresist region
92. The thickness of the first photoresist region 91 is larger than
that of the second photoresist region 92, preferably, the thickness
of the first photoresist region is ranged from 1.7 .mu.m to 2.3
.mu.m, and the thickness of the second photoresist region is ranged
from 0.7 .mu.m to 1.3 .mu.m.
[0053] In step S122, the doping process is performed on the first
active layer through the first photoresist region, so that the N
ions are injected into the first active layer.
[0054] In step S123, the doping process is performed on the second
active layer through the second photoresist region, so that the N
ions are injected into the second active layer.
[0055] FIG. 3d is a schematic diagram illustrating ion implantation
in the method for fabricating the CMOS transistor. As shown in FIG.
3d, the first photoresist region 91 corresponds to the first active
layer 41, and the second photoresist layer 92 corresponds to the
second active layer 42. When performing the N ion injection through
the first photoresist region 91 and the second photoresist region
92, the first photoresist region 91 and the second photoresist
region 92 may block N ion injection to reduce the injection
concentration of N ion. Since the thickness of the first
photoresist region 91 is larger than that of the second photoresist
region 92, so that the concentration of N ions injected into the
first active layer 41 through the first photoresist region 91 is
smaller than that of N ions injected into the second active layer
42 through the second photoresist region 92.
[0056] In step S124, the photoresist layer is removed.
[0057] FIG. 3e is a schematic diagram illustrating removing the
photoresist layer in the method for fabricating the CMOS
transistor. As shown in FIG. 3e, the remaining photoresist layer is
removed to result in the CMOS transistor.
[0058] Preferably, the first active layer 41 and the second active
layer 42 are both made of oxide material. The oxide material is
zinc oxide.
[0059] Preferably, in the step of forming the etch stop layer
(i.e., between step S112 and step S113), the method further
comprises forming a first via hole, a second via hole, a third via
hole and a fourth via hole in the etch stop layer by a patterning
process, a position of the first via hole corresponds to the first
source electrode and the first active layer, a position of the
second via hole corresponds to the first drain electrode and the
first active layer, a position of the third via hole corresponds to
the second source electrode and the second active layer, and a
position of the fourth via hole corresponds to the second drain
electrode and the second active layer, so that the first source
electrode and the first drain electrode are connected with the
first active layer through the first via hole and second via hole,
respectively, and the second source electrode and the second drain
electrode are connected with the second active layer through the
third via hole and fourth via hole, respectively.
[0060] A third embodiment of the present invention provides a
display panel that comprises CMOS transistors.
[0061] The CMOS transistor in this embodiment utilizes the CMOS
transistor in the first embodiment, and the specific implementation
thereof refers to the first embodiment and will not be described in
detail herein.
[0062] A fourth embodiment of the present invention provides a
display device that comprises a display panel, and the display
panel comprises CMOS transistors.
[0063] The display device in this embodiment utilizes the CMOS
transistor in the first embodiment, and the specific implementation
thereof refers to the first embodiment and will not be described in
detail herein.
[0064] It should be understood that, the implementations described
above are merely exemplary implementations for describing the
principle of the present invention, but the present invention is
not limited thereto. For the persons skilled in the art, various
variations and improvements may be made without departing from the
spirit and essence of the present invention, and these variations
and improvements shall be deemed as falling within the protection
scope of the present invention.
* * * * *