U.S. patent application number 14/857167 was filed with the patent office on 2016-01-07 for motor drive controller and method for operating the same.
This patent application is currently assigned to Renesas Electronics Corporation. The applicant listed for this patent is Renesas Electronics Corporation. Invention is credited to Minoru KUROSAWA, Osamu YAMASHITA, Kenji YOSHIDA.
Application Number | 20160006386 14/857167 |
Document ID | / |
Family ID | 51207211 |
Filed Date | 2016-01-07 |
United States Patent
Application |
20160006386 |
Kind Code |
A1 |
KUROSAWA; Minoru ; et
al. |
January 7, 2016 |
MOTOR DRIVE CONTROLLER AND METHOD FOR OPERATING THE SAME
Abstract
A motor driver controller including a difference control
section; a driver output section; a drive current detection
amplifier; and a load short-circuit detection circuit. A motor and
sensing resistor is coupled in series and coupled to an output
terminal of the driver output section. The difference control
section generates a drive voltage command signal in response to a
drive current command value and a drive current detection signal.
The driver output section drives the motor and sensing resistor, in
response to the drive voltage command signal, and a drive current
detection amplifier generates a signal fed to the difference
control section, in response to a drive current of the sensing
resistor. The load short-circuit detection circuit detects an
abnormal oscillation waveform signal caused by a short-circuit
state between the both ends of the motor.
Inventors: |
KUROSAWA; Minoru; (Kanagawa,
JP) ; YOSHIDA; Kenji; (Kanagawa, JP) ;
YAMASHITA; Osamu; (Kanagawa, JP) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Renesas Electronics Corporation |
Tokyo |
|
JP |
|
|
Assignee: |
Renesas Electronics
Corporation
Tokyo
JP
|
Family ID: |
51207211 |
Appl. No.: |
14/857167 |
Filed: |
September 17, 2015 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
14087237 |
Nov 22, 2013 |
9178462 |
|
|
14857167 |
|
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Current U.S.
Class: |
318/565 |
Current CPC
Class: |
H02P 25/034 20160201;
H02P 25/028 20130101 |
International
Class: |
H02P 25/02 20060101
H02P025/02 |
Foreign Application Data
Date |
Code |
Application Number |
Jan 23, 2013 |
JP |
2013-010128 |
Claims
1. A controller, comprising: a driver output circuit configured to
receive a drive voltage command signal and generate a drive output
signal for driving a load and sensing resistor coupled in series
with the load based on the drive voltage command signal; a drive
current detection amplifier configured to generate a drive current
detection signal based on a drive current flowing through the
sensing resistor; and a load short-circuit detection circuit
configured to receive the drive current detection signal and
determine that an abnormal oscillation waveform signal is caused by
a short-circuit state between both ends of the motor.
2. The motor drive controller according to claim 1, wherein the
load short-circuit detection circuit comprises: a first comparator
configured to receive the abnormal oscillation waveform signal at a
first input terminal the first comparator, receive a first
threshold value information at a second input terminal of the first
comparator, and generate a first comparison output signal in
response to the abnormal oscillation waveform signal becoming a
value larger than the first threshold value information.
3. The motor drive controller according to claim 2, wherein the
load short-circuit detection circuit further comprises: a counter
configured to receive the first comparison output signal and
generate a count-up value by counting up in response to a pulse
signal of the first comparison output signal at a cycle of the
abnormal oscillation waveform signal.
4. The motor drive controller according to claim 3, wherein the
load short-circuit detection circuit further comprises: a second
comparator configured to receive the count-up value at a first
input terminal of the second comparator, receive a second threshold
value information at a second input terminal of the second
comparator, and generate a second comparison output signal in
response to the count-up value becoming a value larger than the
second threshold value information, wherein the load short-circuit
detection circuit is configured to output, as a load short-circuit
detection signal, the second comparison output signal generated by
the second comparator.
5. A method of operating a controller, comprising: receiving a
drive voltage command signal and generate a drive output signal for
driving a load and sensing resistor coupled in series with the load
based on the drive voltage command signal; generating a drive
current detection signal based on a drive current flowing through
the sensing resistor; receiving the drive current detection signal;
and determining that an abnormal oscillation waveform signal is
caused by a short-circuit state between both ends of the motor.
6. The method of claim 5, wherein the operation of determining that
an abnormal oscillation waveform signal is caused by a
short-circuit state between both ends of the motor further
comprising: receiving the abnormal oscillation waveform signal at a
first input terminal a first comparator; receiving a first
threshold value information at a second input terminal of the first
comparator; and generating a first comparison output signal in
response to the abnormal oscillation waveform signal becoming a
value larger than the first threshold value information.
7. The motor drive controller according to claim 2, wherein the
operation of determining that an abnormal oscillation waveform
signal is caused by a short-circuit state between both ends of the
motor further comprising: receiving the first comparison output
signal; and generating a count-up value by counting up in response
to a pulse signal of the first comparison output signal at a cycle
of the abnormal oscillation waveform signal.
8. The motor drive controller according to claim 3, wherein the
operation of determining that an abnormal oscillation waveform
signal is caused by a short-circuit state between both ends of the
motor further comprising: receiving the count-up value at a first
input terminal of a second comparator; receiving a second threshold
value information at a second input terminal of the second
comparator; generating a second comparison output signal in
response to the count-up value becoming a value larger than the
second threshold value information; and outputting, as a load
short-circuit detection signal, the second comparison output signal
generated by the second comparator.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application is a continuation of U.S. application Ser.
No. 14/087,237 filed Nov. 22, 2013, which is based upon and claims
the benefit of priority from Japanese Patent Application No.
2013-010128 filed on Jan. 23, 2013, the disclosures of which are
incorporated herein in their entirety by reference.
BACKGROUND
[0002] The present invention relates to a motor drive controller
for driving a voice coil motor (VCM) or the like which moves a
magnetic head of a hard disk drive unit and a method for operating
the same, and in particular relates to a technique effective in
enabling the detection of a short-circuit between both ends of the
motor and an abnormal oscillation due to the short-circuit between
the both ends.
[0003] In a hard disk drive unit (HDD), a load/unload system is
adopted, in which, when not performing reading and writing of data,
a magnetic head is retracted to a ramp mechanism outside an outer
periphery of a magnetic disk and stopped there. The magnetic head
is moved from a retract position of the ramp mechanism to a
disk-medium surface by a loading operation in accordance with an
instruction from a host, thereby performing a read/write operation,
and after the end of the read/write operation, the magnetic head is
contrarily moved from the disk-medium surface to the retract
position of the ramp mechanism by an unloading operation in
accordance with an instruction from the host.
[0004] Furthermore, in a hard disk drive unit (HDD), a magnetic
disk is rotated at high speed by a spindle motor, and then the
magnetic head for read/write is brought close to a medium surface
of the rotating magnetic disk, and the magnetic head is moved to a
radial direction of the magnetic disk by a voice coil motor (VCM),
thereby writing/reading information of the magnetic disk.
[0005] Japanese Patent Laid-Open No. 2005-304095 (Patent Document
1) and Japanese Patent Laid-Open No. 2005-304096 (Patent Document
2) describe that in a voice coil motor drive circuit of a hard disk
drive unit (HDD), a seek operation and a track follow operation of
a magnetic head are performed by PWM driving, thereby resolving the
problems, such as a design load and the scale of a circuit, in both
a PWM drive system during seeking and a linear drive system during
track follow. Note that, as well known, the seek operation is the
operation for moving a magnetic head to a desired storage track,
and the track follow operation is the operation for causing the
magnetic head to follow a desired storage track for
reading/writing. Furthermore, Patent Document 1 and Patent Document
2 describe that a control circuit for feedback-controlling the
drive current of a coil of a voice coil motor of a hard disk drive
unit (HDD) is constituted by a digital circuit.
[0006] Japanese Patent Laid-Open No. 2002-184137 (Patent Document
3) describes that during tracking, in order to achieve an increase
in precision of a magnetic head positioning control and a reduction
of the seek time, a linear drive mode for analogically-controlling
the drive current of a voice coil motor is performed when an amount
of drive for moving a magnetic head is small, whereas when the
amount of drive for moving the magnetic head is large, a pulse
drive mode (PWM) for digitally-controlling the drive current of the
voice coil is performed. In the linear drive mode, a voice coil
motor drive circuit outputs a drive current corresponding to a
detection output of an error detection circuit that detects a
difference between a control command value and a current detection
voltage obtained by converting, into a voltage, the drive current
of the voice coil motor. In contrast, in the pulse drive mode, the
output current of the voice coil motor drive circuit is
PWM-controlled by a PWM circuit that generates a pulse whose pulse
width varies in accordance with the detection output of the error
detection circuit. Selection between these two drive modes is
achieved by a mode switching switch, a first input terminal and a
second input terminal of which are coupled to a non-inverting input
terminal and an output terminal of a PMW comparator of the PWM
circuit, respectively. Because the mode switching switch selects
the output terminal of the PMW comparator, which is the second
input terminal, in response to a drive mode switching signal of a
low level, the pulse drive mode (PWM) under PWM control with a
varying pulse width is performed. The mode switching switch selects
the non-inverting input terminal of the PMW comparator, which is
the first input terminal, in response to the drive mode switching
signal of a high level, and thus there is performed the linear
drive mode in which a voice coil motor drive current is
continuously feedback-controlled.
[0007] Japanese Patent Laid-Open No. 2011-100499 (Patent Document
4) describes that, in order to detect a ground short of an output
line of a VCM driver for driving a voice coil motor (VCM), a
gate-to-source voltage and a drain-to-source voltage of an N
channel MOS transistor for controlling the current supply to the
voice coil motor (VCM) are supplied to an abnormality monitoring
circuit. When the ground short of the output line of the VCM driver
is generated, the abnormality monitoring circuit determines that a
short-circuit is generated because the gate-to-source voltage and
drain-to-source voltage of the N channel MOS transistor exceed a
certain voltage, respectively.
[0008] Publication of Examined Patent Application No. 07-44399
(Patent Document 5) describes that in a BTL push-pull amplifier
used for an audio amplifier, in which an output terminal of one
push-pull amplifier and an output terminal of other push-pull
amplifier are coupled to one end and other end of a load, there is
coupled a protection circuit that prevents destruction of an output
transistor when one end and other end of the load are
short-circuited (load short-circuited). Japanese Patent Laid-Open
No. 07-44399 states that the protection circuit can reduce the
maximum value of an emitter current of the output transistor when
the load is short-circuited, and thus the BTL push-pull amplifier
whose output transistor is unlikely to be destroyed can be
realized.
[0009] Japanese Patent Laid-Open No. 64-39285 (Patent Document 6)
describes that an overcurrent sensing circuit and a power supply
shut-down/opening and closing circuit are coupled to a servo
amplifier that drives a voice coil motor (VCM) of a magnetic disk
unit, and when the overcurrent sensing circuit detects an
overcurrent of the voice coil motor (VCM), the power supply
shut-down/opening and closing circuit shuts down electric power
supplied to the servo amplifier and stops the current supply to the
voice coil motor (VCM).
SUMMARY
[0010] The present inventors engaged in the development of a
semiconductor integrated circuit, so called a voice coil motor
driver, for driving a voice coil motor (VCM) that moves a magnetic
head in a hard disk drive unit (HDD), prior to the present
invention. Specifically, this driver is a highly-integrated
semiconductor integrated circuit, called a combo (COMBO) driver,
having a spindle motor driver for driving a spindle motor that
rotates a magnetic disk at a high speed and a voice coil motor
driver for driving the voice coil motor integrated therein.
[0011] The present inventors, prior to the present invention, have
found a problem that, by short-circuiting of both ends of a voice
coil motor (VCM), a voice coil motor driver becomes an extremely
light load state and a phase margin becomes insufficient in
feedback-controlling the drive current of a coil of the voice coil
motor, and thus an abnormal oscillation occurs. In a normal state
where both ends of the voice coil motor (VCM) are not
short-circuited, the phase margin in the feedback control is
sufficient, and thus in a tracking operation or a seek operation,
the feedback control is executed so that the difference between a
control command value and a current detection voltage obtained by
converting the drive current of the voice coil motor into a voltage
becomes substantially zero.
[0012] Moreover, the short-circuit between both ends of the voice
coil motor (VCM) occurs due to a damage on a flexible wiring, or
due to adhesion of dirt or a conductive material, such as a metal,
between the both ends of the flexible wiring. Once an abnormal
oscillation occurs, a voice coil motor driver cannot drive a
magnetic head for read/write in a hard disk drive unit (HDD). As a
result, once an abnormal oscillation occurs, it becomes impossible
to move a magnetic head from a retract position of a ramp mechanism
to a disk-medium surface by a loading operation in accordance with
an instruction from a host. Furthermore, not only the loading
operation but also the tracking operation and seek operation become
impossible.
[0013] In contrast, in order to detect the ground short of the
output line of the VCM driver, the abnormality monitoring circuit
described in Patent Document 4 monitors the gate-to-source voltage
and drain-to-source voltage of an N channel MOS transistor, which
controls the current supply to a voice coil motor (VCM), and thus
cannot detect the short-circuit between the both ends of the voice
coil motor (VCM). Accordingly, with the control method described in
Patent Document 4, when both ends of the voice coil motor (VCM) are
in a short-circuit state, it is impossible to prevent smoke
generation or firing of the voice coil motor driver for driving the
voice coil motor (VCM).
[0014] Furthermore, the protection circuit described in Patent
Document 5 detects a short-circuit between one end and other end of
the load of the BTL push-pull amplifier and prevents the
destruction of an output transistor, but cannot detect an abnormal
oscillation due to the short-circuit between the both ends of the
voice coil motor (VCM). Accordingly, with the control method
described in Patent Document 5, when both ends of the voice coil
motor (VCM) are in a short-circuit state, it is impossible to
prevent smoke generation or firing of the voice coil motor driver
for driving the voice coil motor (VCM).
[0015] Moreover, the overcurrent sensing circuit and power supply
shut-down/opening and closing circuit described in Patent Document
6 detect an overcurrent of a voice coil of the voice coil motor
(VCM) and prevent the destruction of a transistor by shutting down
the power supply, but cannot detect a short-circuit between the
both ends of the voice coil motor (VCM) and cannot detect an
abnormal oscillation due to the short-circuit. Accordingly, with
the control method described in Patent Document 6, when both ends
of the voice coil motor (VCM) are in a short-circuit state, it is
impossible to prevent smoke generation or firing of the voice coil
motor driver for driving the voice coil motor (VCM).
[0016] While the means for solving the above-described problems are
described below, the other problems and the new feature will become
clear from the description of the present specification and the
accompanying drawings.
[0017] The following explains briefly the outline of a typical
embodiment disclosed in the present application.
[0018] That is, a motor drive controller according to a typical
embodiment includes a difference control section (100), a driver
output section (102), a drive current detection amplifier (103),
and a load short-circuit detection circuit (108).
[0019] A motor (VCM) and sensing resistor (Rs) coupled in series
are coupled to an output terminal of the driver output section
(102), the difference control section (100) generates a driver
voltage command signal in response to a drive current command value
and a drive current detection signal, to thereby supply the same to
an input terminal of the driver output section (102), and the
driver output section (102) drives the motor (VCM) and sensing
resistor (Rs) coupled in series in response to the driver voltage
command signal.
[0020] The drive current detection amplifier (103) generates a
drive current detection signal fed back to the difference control
section (100), in response to a drive current of the sensing
resistor, an input terminal of the load short-circuit detection
circuit (108) is coupled to one of circuit nodes in a feedback loop
including the difference control section (100), the driver output
section (102), the motor (VCM) and sensing resistor (Rs) coupled in
series, and the drive current detection amplifier (103).
[0021] The load short-circuit detection circuit (108) detects an
abnormal oscillation waveform signal generated in the one of
circuit nodes due to a short-circuit state between both ends of the
motor (VCM) (see FIG. 1).
[0022] The following explains briefly the effect obtained by the
typical embodiment among the embodiments disclosed in the present
application.
[0023] That is, with the motor drive controller, the detection of a
short-circuit between both ends of a motor and the detection of an
abnormal oscillation due to the short-circuit between the both ends
are enabled.
BRIEF DESCRIPTION OF THE DRAWINGS
[0024] FIG. 1 is a view showing the configuration of a
semiconductor integrated circuit IC according to a first
embodiment, called a voice coil motor driver, for driving a voice
coil motor (VCM) that moves a magnetic head of a hard disk drive
unit (HDD);
[0025] FIGS. 2A-2D are views showing the characteristics in a
normal operation state where both ends of the voice coil motor
(VCM) are in a non-short-circuit state when the semiconductor
integrated circuit IC according to the first embodiment shown in
FIG. 1 performs an operation for feedback-controlling the current
value of a drive current Ivcm of a coil of the voice coil motor
(VCM);
[0026] FIGS. 3A-3D are views showing the characteristics in an
abnormal operation state where both ends of the voice coil motor
(VCM) are in a short-circuit state when the semiconductor
integrated circuit IC according to the first embodiment shown in
FIG. 1 performs an operation for feedback-controlling the current
value of the drive current Ivcm of a coil of the voice coil motor
(VCM);
[0027] FIG. 4 is a view showing the waveforms in an abnormal
oscillation caused by both ends of the voice coil motor (VCM)
becoming in an abnormal operation state, i.e., in a short-circuit
state, when the semiconductor integrated circuit IC according to
the first embodiment shown in FIG. 1 performs an operation for
feedback-controlling the current value of the drive current Ivcm of
a coil of the voice coil motor (VCM);
[0028] FIG. 5 is a view showing the configuration of a
semiconductor integrated circuit IC, called a voice coil motor
drive, for driving the voice coil motor (VCM) that moves a magnetic
head of the hard disk drive unit (HDD), according to a second
embodiment;
[0029] FIG. 6 is a view showing the configuration of a
semiconductor integrated circuit IC, called a voice coil motor
drive, for driving the voice coil motor (VCM) that moves a magnetic
head of the hard disk drive unit (HDD), according to a third
embodiment;
[0030] FIG. 7 is a view showing the configuration of a
semiconductor integrated circuit IC, called a voice coil motor
drive, for driving the voice coil motor (VCM) that moves a magnetic
head of the hard disk drive unit (HDD), according to a fourth
embodiment; and
[0031] FIG. 8 is a view showing the configuration of a
semiconductor integrated circuit IC, called a voice coil motor
drive, for driving the voice coil motor (VCM) that moves a magnetic
head of the hard disk drive unit (HDD), according to a fifth
embodiment.
DETAILED DESCRIPTION
1. Overview of Embodiments
[0032] First, the overview of a typical embodiment disclosed in the
present application will be described. In the overview description
of the typical embodiment, a symbol referred to with parentheses in
the accompanying drawings simply illustrates those included in the
concept of a component with the symbol attached thereto.
[0033] [1] A motor drive controller according to a typical
embodiment includes a difference control section (100), a driver
output section (102), a drive current detection amplifier (103),
and a load short-circuit detection circuit (108).
[0034] A motor (VCM) and sensing resistor (Rs) coupled in series
can be coupled to an output terminal of the driver output section
(102).
[0035] The difference control section (100) generates a driver
voltage command signal (DDRV, ADRV) in response to a drive current
command value (VCMCRNT) and a drive current detection signal
(DIVCM), and supplies the same to an input terminal of the driver
output section (102).
[0036] The driver output section (102) generates a drive output
signal for driving the motor (VCM) and sensing resistor (Rs)
coupled in series, in response to the driver voltage command signal
(DDRV, ADRV) generated from the difference control section
(100).
[0037] The drive current detection amplifier (103) generates the
drive current detection signal (DIVCM) fed back to the difference
control section (100), in response to a drive current (Ivcm)
flowing through the sensing resistor (Rs).
[0038] An input terminal of the load short-circuit detection
circuit (108) is coupled to the one of circuit nodes in a feedback
loop including the difference control section (100), the driver
output section (102), the motor (VCM) and sensing resistor (Rs)
coupled in series, and the drive current detection amplifier
(103).
[0039] The load short-circuit detection circuit (108) detects an
abnormal oscillation waveform signal generated at the one of
circuit nodes due to a short-circuit state between both ends of the
motor (VCM) (see FIG. 1).
[0040] According to the embodiment, the detection of a
short-circuit between both ends of a motor and the detection of an
abnormal oscillation due to the short-circuit between the both ends
are enabled.
[0041] In a preferred embodiment, the load short-circuit detection
circuit (108) includes a first comparator (1081), to one input
terminal of which the abnormal oscillation waveform signal
generated at the one of circuit nodes is supplied and to other
input terminal of which first threshold value information (ITH) is
supplied.
[0042] In response to the abnormal oscillation waveform signal
becoming a value larger than the first threshold value information
(ITH), a first comparison output signal obtained by detecting the
abnormal oscillation waveform signal is generated from an output
terminal of the first comparator (1081) (see FIG. 1).
[0043] According to another preferred embodiment, the load
short-circuit detection circuit (108) further includes a counter
(1082), to a count input terminal of which the first comparison
output signal generated from the output terminal of the first
comparator (1081) is supplied.
[0044] The counter (1082) generates a count-up value by counting up
in response to a pulse signal of the first comparison output
signal, which is generated from the output terminal of the first
comparator (1081) at a cycle of the abnormal oscillation waveform
signal (see FIG. 1).
[0045] According to yet another preferred embodiment, the load
short-circuit detection circuit (108) further includes a second
comparator (1083), to one input terminal of which the count-up
value generated by the counter (1082) is supplied and to other
input terminal of which second threshold value information (NTH) is
supplied.
[0046] In response to the count-up value becoming a value larger
than the second threshold value information (NTH), a second
comparison output signal, which is obtained by detecting the
abnormal oscillation waveform signal from an output terminal of the
second comparator (1083), is generated.
[0047] The load short-circuit detection circuit (108) outputs the
second comparison output signal generated from the output terminal
of the second comparator (1083), as a load short-circuit detection
signal (STH_DET) (see FIG. 1).
[0048] A motor drive controller according to a further preferred
embodiment further includes an external interface (107), a
digital-to-analog converter (101), and an analog-to-digital
converter (104).
[0049] The external interface (107) supplies the drive current
command value (VCMCRNT), which is digital information supplied from
the outside, to a command input terminal of the difference control
section (100).
[0050] The digital-to-analog converter (101) generates an analog
drive voltage command signal (ADRV) in response to the driver
voltage command signal (DDRV) that is a digital signal supplied
from the difference control section (100), and supplies the analog
drive voltage command signal (ADRV) to the input terminal of the
driver output section (102).
[0051] The drive current detection amplifier (103) generates a
drive current analog amplification signal in response to the drive
current (Ivcm) flowing through the sensing resistor (Rs).
[0052] The analog-to-digital converter (104) generates the drive
current detection signal (DIVCM) which is a digital detection
signal fed back to the feedback terminal of the difference control
section (100), in response to the drive current analog
amplification signal generated from the drive current detection
amplifier (103) (see FIG. 1).
[0053] According to another further preferred embodiment, the
driver output section (102) includes a pre-driver (1021), a first
driver output amplifier (1025), and a second driver output
amplifier (1026).
[0054] The analog drive voltage command signal (ADRV) generated
from the digital-to-analog converter (101) is supplied to an input
terminal of the pre-driver (1021).
[0055] An output terminal of the pre-driver (1021) is coupled to an
input terminal of the first driver output amplifier (1025) and an
input terminal of the second driver output amplifier (1026), and an
output terminal of the first driver output amplifier (1025) and an
output terminal of the second driver output amplifier (1026) can be
coupled to one end and other end of the motor (VCM) and sensing
resistor (Rs) coupled in series, respectively.
[0056] In a pulse drive operation mode, the first driver output
amplifier (1025) and the second driver output amplifier (1026)
generate a drive pulse having a pulse width proportional to a
voltage level of the output terminal of the pre-driver (1021).
[0057] In a linear drive mode different from the pulse drive
operation mode, the first driver output amplifier (1025) and the
second driver output amplifier (1026) generate an amplified output
signal proportional to a voltage level of the output terminal of
the pre-driver (1021) (see FIG. 1).
[0058] According to yet a further preferred embodiment, in the
pulse drive operation mode, a predetermined bias voltage is
supplied to each transistor of the first driver output amplifier
(1025) and the second driver output amplifier (1026) so that the
first driver output amplifier (1025) and the second driver output
amplifier (1026) execute a class-D amplification operation.
[0059] In the linear drive mode, a bias voltage larger than the
predetermined bias voltage is supplied to the each transistor of
the first driver output amplifier (1025) and the second driver
output amplifier (1026) so that the first driver output amplifier
(1025) and the second driver output amplifier (1026) execute a
class-AB amplification operation (see FIG. 1).
[0060] According to another further preferred embodiment, the
digital-to-analog converter (101) is a .SIGMA..DELTA.
digital-to-analog converter (see FIG. 1).
[0061] According to yet another further preferred embodiment, the
analog-to-digital converter (104) is an oversampling .SIGMA..DELTA.
analog-to-digital converter (see FIG. 1).
[0062] The motor controller according to a specific embodiment
further includes a decimation filter (105) coupled between an
output terminal of the oversampling .SIGMA..DELTA.
analog-to-digital converter (104) and the feedback terminal of the
difference control section (100).
[0063] The decimation filter (105) executes decimation processing
of a conversion output signal of the oversampling .SIGMA..DELTA.
analog-to-digital converter and low pass filtering processing for
suppressing quantization noises in a high frequency region of the
oversampling .SIGMA..DELTA. analog-to-digital converter (see FIG.
1).
[0064] The motor controller according to another specific
embodiment further includes an offset calibration section (106)
coupled between an output terminal of the decimation filter (105)
and the feedback terminal of the difference control section
(100).
[0065] The offset calibration section (106) includes a calibration
register (1061) and an offset digital subtractor (1062).
[0066] In a state where the drive current (Ivcm) of the sensing
resistor (Rs) is set to substantially zero, error information about
the drive current detection amplifier (103), the analog-to-digital
converter (104), and the decimation filter (105) is stored into the
calibration register (1061).
[0067] In the normal operation, the offset digital subtractor
(1062) subtracts the error information stored in the calibration
register (1061) from the output signal of the decimation filter
(105), thereby generating the drive current detection signal
(DIVCM) that is the digital detection signal fed back to the
feedback terminal of the difference control section (100) (see FIG.
1).
[0068] According to a more specific embodiment, the motor is a
voice coil motor (VCM) that moves a magnetic head of a hard disk
drive unit (HDD) (see FIG. 1).
[0069] According to another more specific embodiment, the
difference control section (100) includes a digital subtractor
(1002) that performs digital subtraction between the drive current
command value (VCMCRNT) supplied to the command input terminal of
the difference control section (100) and the drive current
detection signal (DIVCM) fed back to the feedback terminal of the
difference control section (100).
[0070] From an output terminal of the digital subtractor (1002),
the drive voltage command signal (DDRV) that is the digital signal
supplied to the digital-to-analog converter (101) is generated (see
FIG. 1).
[0071] According to another more specific embodiment, the one of
circuit nodes, to which the one input terminal of the first
comparator of the load short-circuit detection circuit is coupled,
is any of output terminals of the digital subtractor of the
difference control section, the first driver output amplifier, the
second driver output amplifier, the digital-to-analog converter,
and the drive current detection amplifier.
[0072] According to the most specific embodiment, the difference
control section, the digital-to-analog converter, the driver output
section, the drive current detection amplifier, the
analog-to-digital converter, the decimation filter, and the offset
calibration section are integrated into a semiconductor chip of a
semiconductor integrated circuit (see FIG. 1).
[0073] [2] A typical embodiment from another aspect is a method for
operating a motor drive controller including a difference control
section (100), a driver output section (102), a drive current
detection amplifier (103), and a load short-circuit detection
circuit (108).
[0074] A motor (VCM) and sensing resistor (Rs) coupled in series
can be coupled to an output terminal of the driver output section
(102).
[0075] The difference control section (100) generates a driver
voltage command signal (DDRV, ADRV) in response to a drive current
command value (VCMCRNT) and a drive current detection signal
(DIVCM), and supplies the same to an input terminal of the driver
output section (102).
[0076] The driver output section (102) generates a drive output
signal for driving the motor (VCM) and sensing resistor (Rs)
coupled in series, in response to the driver voltage command signal
(DDRV, ADRV) generated from the difference control section
(100).
[0077] The drive current detection amplifier (103) generates the
drive current detection signal (DIVCM), which is fed back to the
difference control section (100), in response to a drive current
(Ivcm) flowing through the sensing resistor (Rs).
[0078] An input terminal of the load short-circuit detection
circuit (108) is coupled to the one of circuit nodes in a feedback
loop including the difference control section (100), the driver
output section (102), the motor (VCM) and sensing resistor (Rs)
coupled in series, and the drive current detection amplifier
(103).
[0079] The load short-circuit detection circuit (108) detects an
abnormal oscillation waveform signal generated at the one of
circuit nodes due to a short-circuit state between both ends of the
motor (VCM) (see FIG. 1).
[0080] According to the embodiment, the detection of a
short-circuit between both ends of a motor and the detection of an
abnormal oscillation due to the short-circuit between the both ends
are enabled.
2. Details of Embodiments
[0081] Next, the embodiments will be described in more detail. Note
that, in all the drawings for explaining the preferred embodiments
for implementing the present invention, the same symbol is attached
to a component having the same function as that of the preceding
drawing to omit repeating the explanation thereof.
First Embodiment
Configuration Overview of Semiconductor Integrated Circuit
[0082] FIG. 1 is a view showing the configuration of a
semiconductor integrated circuit IC, called a voice coil motor
driver, for driving a voice coil motor (VCM) that moves a magnetic
head of a hard disk drive unit (HDD), according to a first
embodiment. Note that, the semiconductor integrated circuit IC
constitutes a motor drive controller.
[0083] Specifically, the semiconductor integrated circuit IC
(driver IC) shown in FIG. 1 is a highly-integrated semiconductor
integrated circuit, called a combo (COMBO) driver, having
integrated therein a voice coil motor driver for driving a spindle
motor that rotates a magnetic disk at a high speed and a spindle
motor driver for driving the voice coil motor.
[0084] In the semiconductor chip of the semiconductor integrated
circuit IC shown in FIG. 1, there are integrated a digital
difference generation/phase compensation control section 100, a
digital-to-analog converter 101, a driver output section 102, a
drive current detection amplifier 103, an analog-to-digital
converter 104, a decimation filter 105, an offset calibration
section 106, a serial input/output interface 107, and a load
short-circuit detection circuit 108.
[0085] For the semiconductor integrated circuit IC according to the
first embodiment shown in FIG. 1, a voice coil motor (VCM) having a
coil L and a parasitic resistor R.sub.L and a current sensing
resistor Rs are coupled between first and second VCM driver output
terminals VCMP and VCMN of the driver output section 102.
[0086] <<Detailed Configuration of Semiconductor Integrated
Circuit>>
[0087] Hereinafter, the detailed configuration of the semiconductor
integrated circuit IC according to the first embodiment shown in
FIG. 1 will be described.
[0088] <<Digital Difference Generation/Phase Compensation
Control Section>>
[0089] The digital difference generation/phase compensation control
section 100 includes a digital amplifier 1001 constituted by a
digital multiplier, a digital subtractor 1002, two digital
multipliers 1003 and 1004, a digital integrator 1005, and a digital
adder 1006.
[0090] The digital difference generation/phase compensation control
section 100 generates current difference information IERR between
command information of a digital drive current command value
VCMCRNT supplied from a controller and feedback information of a
digital drive current detection signal DIVCM generated from voice
coil motor drive current information of the drive current detection
amplifier 103, and generates the drive voltage command signals DDRV
and ADRV supplied to an input of the driver output section 102.
[0091] The digital amplifier 1001 constituted by a digital
multiplier digitally amplifies a digital drive current command
value VCMCRNT supplied from a controller such as an external
microcomputer, via the serial input/output interface 107. The
digital drive current command value VCMCRNT digitally amplified by
the digital amplifier 1001 is supplied to one input terminal of the
digital subtractor 1002, and the digital drive current detection
signal DIVCM generated from the digital amplifier 1063 of the
offset calibration section 106 is supplied to other input terminal
of the digital subtractor 1002. As a result, the digital difference
drive current information IERR generated from the output terminal
of the digital subtractor 1002 is supplied to one input terminal of
the digital multiplier 1003 and one input terminal of the digital
multiplier 1004.
[0092] In two control registers of the serial input/output
interface 107, integration gain information IGAIN and proportional
gain information PGAIN are stored in advance from a controller,
such as an external microcomputer. Accordingly, the integration
gain information IGAIN and the proportional gain information PGAIN
are supplied to other input terminal of the digital multiplier 1003
and other input terminal of the digital multiplier 1004 from the
serial input/output interface 107, respectively. As a result, the
digital multiplier 1003 performs multiplication of the digital
difference drive current information IERR of the digital subtractor
1002 and the integration gain information IGAIN of the serial
input/output interface 107, and supplies this multiplication result
to an input terminal of the digital integrator 1005. Furthermore,
the digital multiplier 1004 performs multiplication of the digital
difference drive current information IERR of the digital subtractor
1002 and the proportional gain information PGAIN of the serial
input/output interface 107, and supplies this multiplication result
to one input terminal of the digital adder 1006. Moreover, the
digital difference drive current integration information is
supplied to other input terminal of the digital adder 1006 from the
output terminal of the digital integrator 1005, and the digital
difference drive current proportion information is supplied to one
input terminal of the digital adder 1006 from the output terminal
of the digital multiplier 1004. Accordingly, digital difference
drive current proportional integral information (proportional
integral information) as the digital drive voltage command signal
DDRV generated from the output terminal of the digital adder 1006
of the digital difference generation/phase compensation control
section 100 is supplied to the input terminal of the
digital-to-analog converter 101.
[0093] <<Digital-to-Analog Converter>>
[0094] In the semiconductor integrated circuit IC according to the
first embodiment shown in FIG. 1, the digital drive voltage command
signal DDRV generated from the output terminal of the digital adder
1006 of the digital difference generation/phase compensation
control section 100 is converted to the analog drive voltage
command signal ADRV by the digital-to-analog converter 101, and the
analog drive voltage command signal ADRV is supplied to the input
terminal of the driver output section 102.
[0095] As the digital-to-analog converter 101, a .SIGMA..DELTA.
digital-to-analog converter capable of high speed and high
resolution D/A conversion is used. Because most part of the
configuration circuit of the .SIGMA..DELTA. digital-to-analog
converter is a digital circuit, a reduction in power consumption
and an increase in speed can be achieved by a fine semiconductor
manufacturing process of the semiconductor integrated circuit IC.
Furthermore, in the .SIGMA..DELTA. digital-to-analog converter,
.SIGMA..DELTA. modulation generates a difference between a
conversion output signal and an input signal, and this difference
is integrated, and feedback processing is performed so that this
integrated value becomes the minimum. As a result, as called a
noise shaping effect, the quantization noises included in the
output of the comparator of the .SIGMA..DELTA. digital-to-analog
converter shift to a high frequency side, and thus a high S/N ratio
can be achieved.
[0096] <<Driver Output Section>>
[0097] In the semiconductor integrated circuit IC according to the
first embodiment shown in FIG. 1, in response to the analog drive
voltage command signal ADRV from the digital-to-analog converter
101, the driver output section 102 drives the current sensing
resistor Rs and the voice coil motor (VCM) coupled between the
first VCM driver output terminal VCMP and the second VCM driver
output terminal VCMN. Note that the voice coil motor (VCM)
includes, in series, the coil L and the parasitic resistor
R.sub.L.
[0098] As shown in FIG. 1, the driver output section 102 is
constituted by a pre-driver 1021, a feedback capacitor 1022, a
feedback resistor 1023, a PWM modulator 1024, a first VCM driver
output amplifier 1025, a second VCM driver output amplifier 1026,
and a feedback amplifier 1027.
[0099] The analog drive voltage command signal ADRV from the
digital-to-analog converter 101 is supplied to a non-inverting
input terminal(+) of the pre-driver 1021, and a feedback output
signal of the feedback amplifier 1027 is supplied to an inverting
input terminal(-) of the pre-driver 1021 via the feedback capacitor
1022 and the feedback resistor 1023. An output signal of the
pre-driver 1021 is coupled to an input terminal of the PWM
modulator 1024, and an output terminal of the PWM modulator 1024 is
coupled to a first input terminal In1 of the first VCM driver
output amplifier 1025 and a first input terminal In1 of the second
VCM driver output amplifier 1026. Furthermore, the output signal of
the pre-driver 1021 is supplied to a second input terminal In2 of
the first VCM driver output amplifier 1025 and a second input
terminal In2 of the second VCM driver output amplifier 1026.
[0100] Moreover, an output terminal of the first VCM driver output
amplifier 1025 is coupled to the first VCM driver output terminal
VCMP and an inverting input terminal(-) of the feedback amplifier
1027, and an output terminal of the second VCM driver output
amplifier 1026 is coupled to the second VCM driver output terminal
VCMN and a non-inverting input terminal(+) of the feedback
amplifier 1027.
[0101] Furthermore, to the first VCM driver output amplifier 1025
and the second VCM driver output amplifier 1026, a PWM enable
signal PWMENA is supplied from a controller such as an external
microcomputer, via the serial input/output interface 107.
[0102] When the PWM enable signal PWMENA of a high level is
supplied, the first VCM driver output amplifier 1025 and the second
VCM driver output amplifier 1026 respond to a triangular waveform
PWM carrier signal supplied to the first input terminal In1 from
the PWM modulator 1024 and a pre-driver output signal supplied to
the second input terminal In2 from the pre-driver 1021.
Accordingly, the first VCM driver output amplifier 1025 and the
second VCM driver output amplifier 1026 generate a drive pulse
output signal with a pulse width proportional to a voltage level of
the pre-driver output signal of the pre-driver 1021. At this time,
a small bias voltage is supplied to an amplification transistor of
the first VCM driver output amplifier 1025 and the second VCM
driver output amplifier 1026 in response to the PWM enable signal
PWMENA of a high level, and thus the amplification transistor can
perform the class-D amplification operation and the power
consumption of the amplification transistor can be reduced.
[0103] Note that, anti-phase drive pulse output signals are
generated from the first VCM driver output amplifier 1025 and the
second VCM driver output amplifier 1026, and the both terminals of
the voice coil motor (VCM) are driven by these anti-phase drive
pulse output signals. The pulse drive mode under this PWM control
with varying drive pulse width is preferred when the amount of
drive for moving the magnetic head, for example, in the seek
operation or the like is large.
[0104] When the PWM enable signal PWMENA of a low level is
supplied, the first VCM driver output amplifier 1025 and the second
VCM driver output amplifier 1026 execute the linear drive mode in
which an amplified output signal proportional to the voltage level
of the pre-driver output signal of the pre-driver 1021 is
generated. Accordingly, in this case, the first VCM driver output
amplifier 1025 and the second VCM driver output amplifier 1026 do
not respond to the triangular waveform PWM carrier signal supplied
to the first input terminal In1 from the PWM modulator 1024. At
this time, a large bias voltage is supplied to the amplification
transistor of the first VCM driver output amplifier 1025 and the
second VCM driver output amplifier 1026 in response to the PWM
enable signal PWMENA of a low level, and thus the amplification
transistor can execute the class-AB amplification operation and the
distortion of the amplified signal of the amplification transistor
can be reduced.
[0105] Note that, anti-phase linear amplification output signals
are generated from the first VCM driver output amplifier 1025 and
the second VCM driver output amplifier 1026, and the both terminals
of the voice coil motor (VCM) are driven by these anti-phase linear
amplification output signals. The linear drive mode under the
analog control with a varying amplification amplitude is preferred
when the amount of drive for moving the magnetic head, for example,
in the track follow operation or the like is small.
[0106] The pre-driver 1021, the feedback capacitor 1022, the
feedback resistor 1023, and the feedback amplifier 1027 included in
the driver output section 102 shown in FIG. 1 function as a
negative feedback loop for improving the amplification accuracy of
the driver output section 102. When the first VCM driver output
amplifier 1025 and the second VCM driver output amplifier 1026
operate also in both; the pulse drive mode and the linear drive
mode, this negative feedback loop functions. That is, the feedback
amplifier 1027 detects an interterminal amplified voltage between
the output terminal of the first VCM driver output amplifier 1025
and the output terminal of the second VCM driver output amplifier
1026, and supplies the detected interterminal amplified voltage to
the inverting input terminal(-) of the pre-driver 1021. Because the
analog drive voltage command signal ADRV from the digital-to-analog
converter 101 is supplied to the non-inverting input terminal(+) of
the pre-driver 1021, the negative feedback loop functions so that
voltage information about the inverting input terminal(-) of the
pre-driver 1021 coincides with the voltage information about the
non-inverting input terminal(+) of the pre-driver 1021.
Accordingly, the analog drive voltage command signal ADRV of the
non-inverting input terminal(+) of the pre-driver 1021 coincides
with an amplified voltage between the both output terminals of the
first and second VCM driver output amplifier 1025 and 1026
transmitted to the inverting input terminal(-) of the pre-driver
1021. Note that the feedback capacitor 1022 and the feedback
resistor 1023 function as a phase compensation circuit for
improving the stability of the negative feedback loop and also
function as a filter for smoothing a pulse waveform output signal
of the feedback amplifier 1027 during PWM operation.
[0107] <<Drive Current Detection Amplifier>>
[0108] In the semiconductor integrated circuit IC according to the
first embodiment shown in FIG. 1, a voltage between the both
terminals of the current sensing resistor Rs is supplied to
differential input terminals of the drive current detection
amplifier 103 via two current detection terminals; RSINP and RSINN.
One current detection terminal RSINP is coupled to a non-inverting
input terminal(+) of the differential amplifier 1031 of the drive
current detection amplifier 103 via a resistor 1032, and a
reference voltage V.sub.REF is supplied to the non-inverting input
terminal(+) via a resistor 1033. Other current detection terminal
RSINN is coupled to an inverting input terminal(-) of the
differential amplifier 1031 of the drive current detection
amplifier 103 via a resistor 1034, and this inverting input
terminal(-) is coupled to an output terminal of the differential
amplifier 1031 via a resistor 1035.
[0109] Accordingly, the drive current detection amplifier 103
detects the current value of a coil drive current Ivcm flowing
through the current sensing resistor Rs coupled in series to the
voice coil motor (VCM). The drive current information about the
voice coil motor (VCM) is used as feedback information of the
digital drive current detection signal DIVCM supplied to the
digital difference generation/phase compensation control section
100.
[0110] <<Analog-to-Digital Converter>>
[0111] In the semiconductor integrated circuit IC according to the
first embodiment shown in FIG. 1, an analog amplification output
signal from the output terminal of the drive current detection
amplifier 103 is converted to a digital current detection signal by
the analog-to-digital converter 104, and the resulting digital
current detection signal is supplied to an input terminal of the
decimation filter 105.
[0112] As the analog-to-digital converter 104, an oversampling
.SIGMA..DELTA. analog-to-digital converter capable of reducing
aliasing noises and quantization noises and furthermore having a
small scale of the circuit is used. This .SIGMA..DELTA.
analog-to-digital converter can be constituted by an analog
subtractor, an analog integrator, a comparator, a delay circuit,
and a one-bit local digital-to-analog converter, and thus can
reduce the scale of the circuit. Furthermore, even with the
.SIGMA..DELTA. analog-to-digital converter, the difference
generation, difference integration, and an integrated value
feedback processing are executed, and thus high S/N ratio can be
achieved by the noise shaping effect.
[0113] <<Decimation Filter>>
[0114] The decimation filter 105 of the semiconductor integrated
circuit IC according to the first embodiment shown in FIG. 1
executes decimation processing in order to reduce the sampling rate
which is increased by the above-described oversampling
.SIGMA..DELTA. analog-to-digital converter 104, down to an
appropriate sampling rate. Moreover, the decimation filter 105
functions as a low pass filter for suppressing the quantization
noise in the high frequency region which is increased by the amount
of a decrease in the quantization noise in the low frequency region
because of the noise shaping effect by the .SIGMA..DELTA.
analog-to-digital converter 104. Accordingly, the decimation filter
105 is constituted by a digital filter, and is particularly
constituted by a low pass filter and a decimation circuit.
[0115] <<Offset Calibration Section>>
[0116] The offset calibration section 106 of the semiconductor
integrated circuit IC according to the first embodiment shown in
FIG. 1, prior to the feedback control by the above-described
digital difference generation/phase compensation control section
100, executes a calibration operation for reducing errors of the
drive current detection amplifier 103, the analog-to-digital
converter 104, and the decimation filter 105. In order to execute
this operation, the current value of the drive current Ivcm of the
voice coil motor (VCM) is controlled to be zero, and the voltage
between the both terminals of the current sensing resistor Rs is
supplied to the differential input terminals of the drive current
detection amplifier 103 via two current detection terminals RSINP
and RSINN. In this state, total error information of an error of
the drive current detection amplifier 103, an error of the
analog-to-digital converter 104, and an error of the decimation
filter 105 is stored into a calibration register 1061 of the offset
calibration section 106. In response to a calibration enable signal
CALENA, the above-described total error information is stored from
the decimation filter 105 to the calibration register 1061 of the
offset calibration section 106, and is held there.
[0117] In the subsequent drive current detection operation, the
error information held in the calibration register 1061 of the
offset calibration section 106 is supplied to the digital
subtractor 1062, and in the digital subtractor 1062, the error
information in the calibration register 1061 is subtracted from
whole normal detection information. The whole normal detection
information includes all of a normal output signal of the drive
current detection amplifier 103, a normal conversion signal of the
analog-to-digital converter 104, and a normal output signal of the
decimation filter 105. A subtraction output signal of the digital
subtractor 1062 of the offset calibration section 106 is digitally
amplified by the digital amplifier 1063 constituted by a digital
multiplier, and thus the digital drive current detection signal
DIVCM is generated from the output of the digital amplifier 1063.
Accordingly, an error component included in the digital drive
current detection signal DIVCM generated from the output of the
digital amplifier 1063 of the offset calibration section 106 can be
sufficiently reduced.
[0118] <<Load Short-Circuit Detection Circuit>>
[0119] The load short-circuit detection circuit 108 included in the
semiconductor integrated circuit IC according to the first
embodiment shown in FIG. 1 includes a first comparator 1081, a
counter 1082, and a second comparator 1083.
[0120] To a non-inverting input terminal(+) and an inverting input
terminal(-) of the first comparator 1081 constituted as a digital
comparator, the digital difference drive current information IERR
generated from the digital subtractor 1002 and a digital current
threshold value ITH generated from the serial input/output
interface 107 are supplied, respectively. A comparison output
signal of the first comparator 1081 constituted as a digital
comparator is supplied to a count input terminal of the counter
1082, and a shut-down enable signal SHTD_ENA of a high level is
supplied to a reset input terminal rstn of the counter 1082 at a
substantially constant time interval. To a non-inverting input
terminal(+) and an inverting input terminal(-) of the second
comparator 1083 constituted as a digital comparator, a count output
signal of the counter 1082 and a digital count threshold value NTH
generated from the serial input/output interface 107 are supplied,
respectively. Furthermore, from an output terminal of the second
comparator 1083 constituted as a digital comparator, a shutdown
detection signal SHT_DET as a load short-circuit detection signal
is generated.
[0121] <<Operation of Load Short-Circuit Detection Circuit in
Normal Operation State>>
[0122] Next, hereinafter, there will be described the operation of
the load short-circuit detection circuit 108 included in the
semiconductor integrated circuit IC according to the first
embodiment shown in FIG. 1, in a normal operation state where the
both ends of the voice coil motor (VCM) are in a non-short-circuit
state.
[0123] Assume a case where the both ends of the voice coil motor
(VCM) are not short-circuited in both cases of the seek operation
of the magnetic head (when the PWM enable signal PWMENA is at a
high level) and the track follow operation (when the PWM enable
signal PWMENA is at a low level). In this case, due to the
operation of the digital difference generation/phase compensation
control section 100 that feedback-controls the drive current Ivcm
of the coil of the voice coil motor (VCM) of the hard disk drive
unit (HDD), the current difference information IERR between the
digital drive current command value VCMCRNT and the digital drive
current detection signal DIVCM becomes substantially zero. That is,
due to the operation of the digital difference generation/phase
compensation control section 100, the current difference
information IERR between the command information of the digital
drive current command value VCMCRNT supplied from a controller and
the feedback information of the digital drive current detection
signal DIVCM generated from the voice coil motor drive current
information of the drive current detection amplifier 103 is
feedback-controlled so as to be substantially zero. As a result,
such a feedback operation of the digital difference
generation/phase compensation control section 100 sets the current
value of the drive current Ivcm of the coil of the voice coil motor
(VCM).
[0124] As described above, in the normal operation state where the
both ends of the voice coil motor (VCM) are in a non-short-circuit
state, the current difference information IERR generated from the
digital subtractor 1002 of the digital difference generation/phase
compensation control section 100 becomes substantially zero.
Accordingly, the digital value of the digital difference drive
current information IERR supplied to the non-inverting input
terminal(+) of the first comparator 1081 of the load short-circuit
detection circuit 108 becomes a value smaller than the digital
current threshold value ITH supplied to the inverting input
terminal(-) of the first comparator 1081 of the load short-circuit
detection circuit 108. As a result, the counter 1082, without
counting up, is maintained at the value of zero that is a count
initial value, in response to the shut-down enable signal of a high
level that is supplied to the reset input terminal rstn at a
substantially constant time interval. Accordingly, the value of
zero that is the count initial value of an output of the counter
1082 supplied to the non-inverting input terminal(+) of the second
comparator 1083 of the load short-circuit detection circuit 108
becomes a value smaller than the digital count threshold value NTH
supplied to the inverting input terminal(-) of the second
comparator 1083. Accordingly, the shutdown detection signal SHT_DET
as the load short-circuit detection signal generated from the
output terminal of the second comparator 1083 of the load
short-circuit detection circuit 108 becomes at a low level. As a
result, a controller, such as a microcomputer, externally coupled
to the serial input/output interface 107 of the semiconductor
integrated circuit IC shown in FIG. 1 recognizes, from the shutdown
detection signal SHT_DET of a low level, that the both ends of the
voice coil motor (VCM) are in a non-short-circuit state and in the
normal operation state, and continues the feedback control
operation of the drive current Ivcm of the coil of the voice coil
motor (VCM).
[0125] <<Operation of Load Short-Circuit Detection Circuit in
Abnormal Operation State>>
[0126] Next, hereinafter, there will be described the operation of
the load short-circuit detection circuit 108 included in the
semiconductor integrated circuit IC according to the first
embodiment shown in FIG. 1, in an abnormal operation state where
the both ends of the voice coil motor (VCM) are in a short-circuit
state.
[0127] Assume that the both ends of the voice coil motor (VCM) are
in a short-circuit state in both cases of the seek operation of the
magnetic head (when the PWM enable signal PWMENA is at a high
level) and the track follow operation (when the PWM enable signal
PWMENA is at a low level). In this case, short-circuiting of the
both ends of the voice coil motor (VCM) puts the voice coil motor
driver into an extremely light load state, and thus the phase
margin becomes insufficient in feedback-controlling the drive
current of the coil of the voice coil motor and an abnormal
oscillation is generated. Due to this abnormal oscillation, an
abnormal oscillation waveform signal having a relatively large
amplitude is generated at the one of circuit nodes in a feedback
loop from the output terminal of the digital subtractor 1002 of the
digital difference generation/phase compensation control section
100 to one input terminal of the digital subtractor 1002.
[0128] In a state where this abnormal oscillation is generated,
even with the operation of the digital difference generation/phase
compensation control section 100 that feedback-controls the drive
current Ivcm of the coil of the voice coil motor (VCM), it becomes
impossible to control the current difference information IERR
between the digital drive current command value VCMCRNT and the
digital drive current detection signal DIVCM, to be substantially
zero. That is, even if the digital difference generation/phase
compensation control section 100 operates, it becomes impossible to
execute the feedback control so that the current difference
information IERR between the command information of the digital
drive current command value VCMCRNT supplied from a controller and
the feedback information of the digital drive current detection
signal DIVCM generated from the voice coil motor drive current
information of the drive current detection amplifier 103 becomes
substantially zero.
[0129] As described above, in an abnormal operation state where the
both ends of the voice coil motor (VCM) are in a short-circuit
state, the current difference information IERR generated from the
digital subtractor 1002 of the digital difference generation/phase
compensation control section 100 does not become substantially
zero. Accordingly, a digital value of the digital difference drive
current information IERR supplied to the non-inverting input
terminal(+) of the first comparator 1081 of the load short-circuit
detection circuit 108 becomes an instantaneous value larger than
the digital current threshold value ITH supplied to the inverting
input terminal(-) of the first comparator 1081 of the load
short-circuit detection circuit 108, at an abnormal oscillation
cycle determined by an abnormal oscillation frequency. As a result,
from the output terminal of the first comparator 1081 of the load
short-circuit detection circuit 108, a comparison output pulse
signal of a high level is generated at the above-described abnormal
oscillation cycle. Therefore, in response to the comparison output
pulse signal of a high level generated at the abnormal oscillation
cycle, the counter 1082 counts up and the count-up value of the
counter 1082 increases from the zero value of a count initial
value. Thus, the count-up value of the counter 1082 supplied to the
non-inverting input terminal(+) of the second comparator 1083 of
the load short-circuit detection circuit 108 becomes a value larger
than the digital count threshold value NTH supplied to the
inverting input terminal(-) of the second comparator 1083.
Accordingly, the shutdown detection signal SHT_DET as the load
short-circuit detection signal generated from the output terminal
of the second comparator 1083 of the load short-circuit detection
circuit 108 becomes a high level. As a result, a controller such as
a microcomputer, externally coupled to the serial input/output
interface 107 of the semiconductor integrated circuit IC shown in
FIG. 1 recognizes, from the shutdown detection signal SHT_DET of a
high level, that the both ends of the voice coil motor (VCM) are in
a short-circuit state and in an abnormal operation state, and
terminates the feedback control operation of the drive current Ivcm
of the coil of the voice coil motor (VCM). For example, a
controller such as a microcomputer, stops the operation of the
driver output section 102 in response to the shutdown detection
signal SHT_DET of a high level. Thereby, the feedback control
operation of the current value of the drive current Ivcm of the
coil of the voice coil motor (VCM) is terminated.
[0130] With the above-described semiconductor integrated circuit IC
according to the first embodiment shown in FIG. 1, in an abnormal
operation state where the both ends of the voice coil motor (VCM)
are in a short-circuit state, the feedback control operation of the
current value of the drive current Ivcm of the coil of the voice
coil motor (VCM) can be terminated. Accordingly, with the
semiconductor integrated circuit IC according to the first
embodiment shown in FIG. 1, when both ends of the voice coil motor
(VCM) are in a short-circuit state, smoke generation or firing of
the voice coil motor driver for driving the voice coil motor (VCM)
can be prevented.
[0131] Furthermore, in the semiconductor integrated circuit IC
according to the first embodiment shown in FIG. 1, a load
short-circuit detection operation of whether or not the both ends
of the voice coil motor (VCM) (VCM) are in a short-circuit state is
executed before the magnetic head is moved to the disk-medium
surface from the retract position of the ramp mechanism by a
loading operation in accordance with an instruction from a host in
order to perform read/write operations in the hard disk drive unit
(HDD). In other method, the load short-circuit detection operation
of whether or not the both ends of the voice coil motor (VCM) are
in a short-circuit state is executed after the above-described
loading operation and prior to the seek operation in which the
amount of drive for moving the magnetic head is large.
[0132] <<Characteristics in Normal Operation
State>>
[0133] FIG. 2 is a view showing the characteristics in the normal
operation state where both ends of the voice coil motor (VCM) are
in a non-short-circuit state when the semiconductor integrated
circuit IC according to the first embodiment shown in FIG. 1
executes an operation for feedback-controlling the current value of
the drive current Ivcm of a coil of the voice coil motor (VCM).
[0134] FIG. 2A shows the frequency characteristics of the load of
the voice coil motor (VCM) driven by the semiconductor integrated
circuit IC according to the first embodiment shown in FIG. 1, in
the normal operation state where the both ends of the voice coil
motor (VCM) are in a non-short-circuit state.
[0135] As shown in FIG. 2A, in a frequency band sufficiently lower
than a pole frequency fp=R.sub.L/(2.pi.L) determined by the coil L
and the parasitic resistor R.sub.L of the voice coil motor (VCM),
the gain of the voice coil motor (VCM) is determined by the current
sensing resistor Rs and the parasitic resistor R.sub.L as
Gain=1/(Rs/R.sub.L). In a frequency band sufficiently higher than
this pole frequency fp=R.sub.L/(2.pi.L), the gain Gain of the voice
coil motor (VCM) decreases in response to an increase in the
frequency in accordance with a first-order integration
characteristics. Note that, at the frequency equal to the pole
frequency fp=R.sub.L/(2.pi.L), the denominator of a transfer
function determining the gain Gain of the voice coil motor (VCM)
becomes substantially zero, and this frequency is called a
pole.
[0136] FIG. 2B shows a frequency characteristics of the digital
difference generation/phase compensation control section 100 of the
semiconductor integrated circuit IC according to the first
embodiment shown in FIG. 1, in the normal operation state where the
both ends of the voice coil motor (VCM) are in a non-short-circuit
state.
[0137] As shown in FIG. 2B, the gain Gain of the digital difference
generation/phase compensation control section 100 decreases in
accordance with an increase in the frequency, and a frequency at
which the numerator of the transfer function determining the gain
Gain of the digital difference generation/phase compensation
control section 100 becomes substantially zero is called a zero
point. In particular, a zero point frequency fz of the digital
difference generation/phase compensation control section 100 is set
substantially equal to the pole frequency fp=R.sub.L/(2.pi.L) of
the gain Gain of the voice coil motor (VCM) shown in FIG. 2A.
Accordingly, as shown in FIG. 2B, in the frequency band
sufficiently lower than the zero point frequency fz (the pole
frequency fp), the gain Gain of the digital difference
generation/phase compensation control section 100 decreases in
response to an increase in the frequency in accordance with the
first-order integral characteristics depending on the integration
gain information IGAIN of the digital integrator 1005. Moreover, in
the frequency band sufficiently higher than this zero point
frequency fz (the pole frequency fp), the gain Gain of the digital
difference generation/phase compensation control section 100 is
maintained at a value substantially independent of a change in the
frequency in accordance with the proportional gain information
PGAIN of the digital multiplier 1004.
[0138] FIG. 2C shows a combined frequency characteristics of the
other circuit portions of the semiconductor integrated circuit IC
according to the first embodiment shown in FIG. 1, in the normal
operation state where the both ends of the voice coil motor (VCM)
are in a non-short-circuit state. Note that, the other circuit
portions of the semiconductor integrated circuit IC according to
the first embodiment shown in FIG. 1 include the digital-to-analog
converter 101, the driver output section 102, the drive current
detection amplifier 103, the analog-to-digital converter 104, the
decimation filter 105, and the offset calibration section 106.
[0139] As shown in FIG. 2C, the gain Gain of the other circuit
portions is maintained at a value substantially independent of a
change in the frequency until the frequency reaches a frequency
band considerably higher than the pole frequency
fp=R.sub.L/(2.pi.L) determined by the coil L and the parasitic
resistor R.sub.L of the voice coil motor (VCM). However, in a
frequency band further higher than the considerably high frequency
band, the gain Gain of the other circuit portions abruptly
decreases in response to an increase in the frequency in accordance
with a high-order integral characteristics.
[0140] FIG. 2D shows an overall frequency characteristics of the
semiconductor integrated circuit IC according to the first
embodiment shown in FIG. 1, in the normal operation state where the
both ends of the voice coil motor (VCM) are in a non-short-circuit
state. Note that, the overall frequency characteristics of the
semiconductor integrated circuit IC according to the first
embodiment shown in FIG. 2D is the frequency characteristics
obtained by overlapping with the frequency characteristics of the
load of the voice coil motor (VCM) shown in FIG. 2A, the frequency
characteristics of the digital difference generation/phase
compensation control section 100 shown in FIG. 2B, and the combined
frequency characteristics of the other circuit portions shown in
FIG. 2C.
[0141] As shown in FIG. 2D, in the overall frequency
characteristics of the semiconductor integrated circuit IC
according to the first embodiment shown in FIG. 1, the pole of the
gain Gain of the voice coil motor (VCM) shown in FIG. 2A and the
zero point of the gain Gain of the digital difference
generation/phase compensation control section 100 shown in FIG. 2B
are cancelled out. As a result, the overall frequency
characteristics of the semiconductor integrated circuit IC shown in
FIG. 2D becomes a first-order integral characteristics from the low
frequency band to a cut-off frequency f0 at which the gain Gain
becomes 0 dB, and the phase at the cut-off frequency f0 at which
the gain Gain becomes 0 dB has a sufficient phase margin with
respect to -180.degree., and thus the closed loop characteristics
become stable.
[0142] <<Characteristics in Abnormal Operation
State>>
[0143] FIG. 3 is a view showing the characteristics in an abnormal
operation state where both ends of the voice coil motor (VCM) are
in a short-circuit state when the semiconductor integrated circuit
IC according to the first embodiment shown in FIG. 1 executes an
operation for feedback-controlling the current value of the drive
current Ivcm of a coil of the voice coil motor (VCM).
[0144] FIG. 3A shows the frequency characteristics of the load of
the voice coil motor (VCM) driven by the semiconductor integrated
circuit IC according to the first embodiment shown in FIG. 1, in an
abnormal operation state where the both ends of the voice coil
motor (VCM) are in a short-circuit state.
[0145] As shown in FIG. 3A, the coil L and the parasitic resistor
R.sub.L become substantially zero, respectively, due to the short
circuit between the both ends of the voice coil motor (VCM), and
thus the voice coil motor characteristics become a large gain
Gain=1/(Rs), and also the pole disappears in the gain frequency
characteristics, and the large gain Gain=1/(Rs) is maintained until
the frequency reaches an extremely high frequency.
[0146] FIG. 3B shows the frequency characteristics of the digital
difference generation/phase compensation control section 100 of the
semiconductor integrated circuit IC according to the first
embodiment shown in FIG. 1, in the abnormal operation state where
the both ends of the voice coil motor (VCM) are in a short-circuit
state.
[0147] The gain Gain of the digital difference generation/phase
compensation control section 100 in an abnormal operation state of
a short-circuit state shown in FIG. 3B decreases in accordance with
an increase in the frequency, as with the gain Gain in the normal
operation state of the non-short-circuit state shown in FIG. 2B.
That is, as shown in FIG. 3B, in a frequency band sufficiently
lower than the zero point frequency fz, the gain Gain of the
digital difference generation/phase compensation control section
100, in the normal operation state of a non-short-circuit state
decreases in response to an increase in the frequency in accordance
with the first-order integral characteristics depending on the
integration gain information IGAIN of the digital integrator 1005.
Moreover, in a frequency band sufficiently higher than this zero
point frequency fz, the gain Gain of the digital difference
generation/phase compensation control section 100 in the normal
operation state of a non-short-circuit state is maintained at a
value substantially independent of a change in the frequency in
accordance with the proportional gain information PGAIN of the
digital multiplier 1004.
[0148] FIG. 3C shows the combined frequency characteristics of the
other circuit portions of the semiconductor integrated circuit IC
according to the first embodiment shown in FIG. 1, in the abnormal
operation state where the both ends of the voice coil motor (VCM)
are in a short-circuit state. Note that, the other circuit portions
of the semiconductor integrated circuit IC according to the first
embodiment shown in FIG. 1 include the digital-to-analog converter
101, the driver output section 102, a drive current detection
amplifier 103, the analog-to-digital converter 104, a decimation
filter 105, and the offset calibration section 106.
[0149] As shown in FIG. 3C, until the frequency reaches a frequency
band considerably higher than the zero point frequency fz, the gain
Gain of the other circuit portions in the abnormal operation state
of a short-circuit state is maintained at a value substantially
independent of a change in the frequency. However, in a frequency
band further higher than the considerably high frequency band, the
gain Gain of the other circuit portions in the abnormal operation
state of a short-circuit state abruptly decreases in response to an
increase in the frequency in accordance with high-order integral
characteristics.
[0150] FIG. 3D shows the overall frequency characteristics of the
semiconductor integrated circuit IC according to the first
embodiment shown in FIG. 1, in the abnormal operation state where
the both ends of the voice coil motor (VCM) are in a short-circuit
state. Note that the overall frequency characteristics of the
semiconductor integrated circuit IC according to the first
embodiment shown in FIG. 3D are the frequency characteristics
obtained by overlapping the frequency characteristics of the load
of the voice coil motor (VCM) shown in FIG. 3A, the frequency
characteristics of the digital difference generation/phase
compensation control section 100 shown in FIG. 3B, and the combined
frequency characteristics of the other circuit portions shown in
FIG. 3C.
[0151] As shown in FIG. 3D, the overall frequency characteristics
in the abnormal operation state of a short-circuit state of the
semiconductor integrated circuit IC according to the first
embodiment shown in FIG. 1 have a relatively large gain Gain
between the zero point frequency fz and a cut-off frequency f0' of
a frequency higher than the cut-off frequency f0 shown in FIG. 2D.
As a result, the phase at the cut-off frequency f0' of a high
frequency, at which the gain Gain becomes 0 dB, does not have a
sufficient phase margin with respect to -180.degree., and thus the
closed loop characteristics become unstable and an abnormal
oscillation is generated.
[0152] <<Abnormal Oscillation Waveform in Abnormal Operation
State>>
[0153] FIG. 4 is a view showing the waveforms in an abnormal
oscillation caused by both ends of the voice coil motor (VCM)
becoming in an abnormal operation state, i.e., in a short-circuit
state, when the semiconductor integrated circuit IC according to
the first embodiment shown in FIG. 1 executes an operation for
feedback-controlling the current value of the drive current Ivcm of
a coil of the voice coil motor (VCM).
[0154] The upper part of FIG. 4 shows the voltage waveforms of the
first VCM driver output terminal voltage VCMP and the second VCM
driver output terminal voltage VCMN of the driver output section
102, and the lower part of FIG. 4 shows the current waveform of the
coil drive current Ivcm flowing through the current sensing
resistor Rs coupled in series to the voice coil motor (VCM).
[0155] A period T_open shown in FIG. 4 on the left indicates the
normal operation state where the both ends of the voice coil motor
(VCM) are in a non-short-circuit state (an open state), and the
first VCM driver output terminal voltage VCMP and the second VCM
driver output terminal voltage VCMN of the driver output section
102 are maintained at a stable voltage and the coil drive current
Ivcm is maintained at a stable current.
[0156] A period T_short in the center and on the right shown in
FIG. 4 indicates the abnormal operation state where the both ends
of the voice coil motor (VCM) are in a short-circuit state (a short
state), in which the first VCM driver output terminal voltage VCMP
and the second VCM driver output terminal voltage VCMN of the
driver output section 102 vary at an oscillation voltage of a large
amplitude and the coil drive current Ivcm varies at an oscillation
current of a large amplitude.
[0157] The shutdown detection signal SHT_DET as the load
short-circuit detection signal, which is generated from the output
terminal of the second comparator 1083 of the load short-circuit
detection circuit 108 of the semiconductor integrated circuit IC
according to the first embodiment shown in FIG. 1 in response to an
abnormal oscillation generated in this manner in the period T_short
shown in FIG. 4, becomes a high level. As a result, a controller,
such as a microcomputer, externally coupled to the serial
input/output interface 107 of the semiconductor integrated circuit
IC shown in FIG. 1 recognizes, from the shutdown detection signal
SHT_DET of a high level, that the both ends of the voice coil motor
(VCM) are in a short-circuit state and in an abnormal operation
state, and terminates the feedback control operation of the drive
current Ivcm of the coil of the voice coil motor (VCM). For
example, the controller stops the operation of the driver output
section 102 in response to the shutdown detection signal SHT_DET of
a high level. Thereby, the feedback control operation of the
current value of the drive current Ivcm of the coil of the voice
coil motor (VCM) is terminated. Accordingly, with the semiconductor
integrated circuit IC according to the first embodiment shown in
FIG. 1, when the both ends of the voice coil motor (VCM) are in a
short-circuit state, it is possible to prevent smoke generation or
firing of the voice coil motor driver for driving the voice coil
motor (VCM).
Second Embodiment
[0158] FIG. 5 is a view showing the configuration of a
semiconductor integrated circuit IC, called a voice coil motor
drive, for driving the voice coil motor (VCM) that moves a magnetic
head of the hard disk drive unit (HDD), according to a second
embodiment.
[0159] The semiconductor integrated circuit IC according to the
second embodiment shown in FIG. 5 differs from the semiconductor
integrated circuit IC according to the first embodiment shown in
FIG. 1, in the following points.
[0160] That is, the load short-circuit detection circuit 108 of the
semiconductor integrated circuit IC according to the second
embodiment shown in FIG. 5 includes the first comparator 1081, the
counter 1082, and the second comparator 1083.
[0161] To the non-inverting input terminal(+) and the inverting
input terminal(-) of the first comparator 1081 constituted as an
analog comparator, the second VCM driver output terminal voltage
VCMN of the driver output section 102 and an analog voltage
threshold value V.sub.TH are supplied, respectively. The comparison
output signal of the first comparator 1081 constituted as an analog
comparator is supplied to the count input terminal of the counter
1082, and the shut-down enable signal SHTD_ENA of a high level is
supplied to the reset input terminal rstn of the counter 1082, at a
substantially constant time interval.
[0162] The count output signal of the counter 1082 and the digital
count threshold value NTH generated from the serial input/output
interface 107 are supplied to the non-inverting input terminal(+)
and the inverting input terminal(-) of the second comparator 1083
constituted as a digital comparator, respectively. Furthermore,
from the output terminal of the second comparator 1083 constituted
as a digital comparator, the shutdown detection signal SHT_DET as
the load short-circuit detection signal is generated.
[0163] <<Operation of Load Short-Circuit Detection Circuit in
Abnormal Operation State>>
[0164] Next, hereinafter, there will be described the operation of
the load short-circuit detection circuit 108 included in the
semiconductor integrated circuit IC according to the second
embodiment shown in FIG. 5, in an abnormal operation state where
the both ends of the voice coil motor (VCM) are in a short-circuit
state.
[0165] Assume the case where the both ends of the voice coil motor
(VCM) are in a short-circuit state in the case of the track follow
operation of the magnetic head (when the PWM enable signal PWMENA
is at a low level). In this case, short-circuiting of the both ends
of the voice coil motor (VCM) puts the voice coil motor driver into
an extremely light load state, and thus the phase margin becomes
insufficient in feedback-controlling the drive current of a coil of
the voice coil motor and an abnormal oscillation is generated. Due
to this abnormal oscillation, an abnormal oscillation waveform
signal having a relatively large amplitude is generated at one of
the circuit nodes in a feedback loop, from the output terminal of
the digital subtractor 1002 of the digital difference
generation/phase compensation control section 100 to one input
terminal of the digital subtractor 1002.
[0166] In the state where this abnormal oscillation is generated,
as described in FIG. 4, the first VCM driver output terminal
voltage VCMP and the second VCM driver output terminal voltage VCMN
of the driver output section 102 vary at an oscillating voltage of
a large amplitude.
[0167] Accordingly, the analog voltage of the second VCM driver
output terminal voltage VCMN of the driver output section 102
supplied to the non-inverting input terminal(+) of the first
comparator 1081 of the load short-circuit detection circuit 108
has, at an abnormal oscillation cycle determined by an abnormal
oscillation frequency, an instantaneous value larger than the
analog voltage threshold value V.sub.TH supplied to the inverting
input terminal(-) of the first comparator 1081 of the load
short-circuit detection circuit 108. As a result, from the output
terminal of the first comparator 1081 of the load short-circuit
detection circuit 108, the comparison output pulse signal of a high
level is generated at the above-described abnormal oscillation
cycle.
[0168] Accordingly, in response to the comparison output pulse
signal of a high level generated at the abnormal oscillation cycle,
the counter 1082 counts up and the count-up value of the counter
1082 increases from the zero value of a count initial value.
Therefore, the count-up value of the counter 1082 supplied to the
non-inverting input terminal(+) of the second comparator 1083 of
the load short-circuit detection circuit 108 becomes a value larger
than the digital count threshold value NTH supplied to the
inverting input terminal(-) of the second comparator 1083.
Accordingly, the shutdown detection signal SHT_DET as the load
short-circuit detection signal generated from the output terminal
of the second comparator 1083 of the load short-circuit detection
circuit 108 becomes a high level. As a result, a controller such as
a microcomputer externally coupled to the serial input/output
interface 107 of the semiconductor integrated circuit IC shown in
FIG. 5 recognizes, from the shutdown detection signal SHT_DET of a
high level, that the both ends of the voice coil motor (VCM) are in
a short-circuit state and in an abnormal operation state, and
terminates the feedback control operation of the drive current Ivcm
of the coil of the voice coil motor (VCM). For example, a
controller such as a microcomputer sets the digital value of the
command information of the digital drive current command value
VCMCRNT to a zero value in response to the shutdown detection
signal SHT_DET of a high level. Thereby, the feedback control
operation of the current value of the drive current Ivcm of the
coil of the voice coil motor (VCM) is terminated.
[0169] Note that, as other operation termination method, in
response to the shutdown detection signal SHT_DET of a high level
of the load short-circuit detection circuit 108, the operation of
the digital difference generation/phase compensation control
section 100 can be stopped, or the operation of the
digital-to-analog converter 101 can be stopped, or the operation of
the driver output section 102 can be stopped. Furthermore, in the
semiconductor integrated circuit IC according to the second
embodiment shown in FIG. 5, the first VCM driver output terminal
voltage VCMP of the driver output section 102 can be supplied to
the non-inverting input terminal(+) of the first comparator 1081
constituted as an analog comparator.
[0170] With the above-described semiconductor integrated circuit IC
according to the second embodiment shown in FIG. 5, in an abnormal
operation state where the both ends of the voice coil motor (VCM)
are in a short-circuit state, the feedback control operation of the
current value of the drive current Ivcm of the coil of the voice
coil motor (VCM) can be terminated. Accordingly, with the
semiconductor integrated circuit IC according to the fourth
embodiment shown in FIG. 7, smoke generation or firing of the voice
coil motor driver for driving the voice coil motor (VCM) can be
prevented in a state where both ends of the voice coil motor (VCM)
are short-circuited. Note that, in the case of the seek operation
(when the PWM enable signal PWMENA is at a high level), the output
terminal voltage VCMN itself of the second VCM driver output
amplifier 1026, in the normal state, performs a large amplitude
operation by the PWM operation. Accordingly, the load short-circuit
detection circuit 108 included in the semiconductor integrated
circuit IC according to the second embodiment is difficult to
detect the short-circuit in the seek operation.
Third Embodiment
[0171] FIG. 6 is a view showing the configuration of a
semiconductor integrated circuit IC, called a voice coil motor
drive, for driving the voice coil motor (VCM) that moves a magnetic
head of the hard disk drive unit (HDD), according to a fourth
embodiment.
[0172] The semiconductor integrated circuit IC according to the
third embodiment shown in FIG. 6 differs from the semiconductor
integrated circuit IC according to the first embodiment shown in
FIG. 1, in the following points.
[0173] That is, the load short-circuit detection circuit 108 of the
semiconductor integrated circuit IC according to the third
embodiment shown in FIG. 6 includes the first comparator 1081, the
counter 1082, and the second comparator 1083.
[0174] The analog drive voltage command signal ADRV that is a
conversion output signal of the digital-to-analog converter 101 and
an analog voltage threshold value V.sub.TH are supplied to the
non-inverting input terminal(+) and the inverting input terminal(-)
of the first comparator 1081 constituted as an analog comparator,
respectively. The comparison output signal of the first comparator
1081 constituted as an analog comparator is supplied to the count
input terminal of the counter 1082, and the shut-down enable signal
SHTD_ENA of a high level is supplied to the reset input terminal
rstn of the counter 1082, at a substantially constant time
interval.
[0175] The count output signal of the counter 1082 and the digital
count threshold value NTH generated from the serial input/output
interface 107 are supplied to the non-inverting input terminal(+)
and the inverting input terminal(-) of the second comparator 1083
constituted as a digital comparator, respectively. Furthermore,
from the output terminal of the second comparator 1083 constituted
as a digital comparator, the shutdown detection signal SHT_DET as
the load short-circuit detection signal is generated.
[0176] <<Operation of Load Short-Circuit Detection Circuit in
Abnormal Operation State>>
[0177] Next, hereinafter, there will be described the operation of
the load short-circuit detection circuit 108 included in the
semiconductor integrated circuit IC according to the third
embodiment shown in FIG. 6, in an abnormal operation state where
the both ends of the voice coil motor (VCM) are in a short-circuit
state.
[0178] Assume that the both ends of the voice coil motor (VCM) are
in a short-circuit state in both cases of the seek operation of the
magnetic head (when the PWM enable signal PWMENA is at a high
level) and of the track follow operation (when the PWM enable
signal PWMENA is at a low level). In this case, short-circuiting of
the both ends of the voice coil motor (VCM) puts the voice coil
motor driver into an extremely light load state, and thus the phase
margin becomes insufficient in feedback-controlling the drive
current of the coil of the voice coil motor and an abnormal
oscillation is generated. Due to this abnormal oscillation, an
abnormal oscillation waveform signal having a relatively large
amplitude is generated at one of the circuit nodes in a feedback
loop, from the output terminal of the digital subtractor 1002 of
the digital difference generation/phase compensation control
section 100 to one input terminal of the digital subtractor
1002.
[0179] In this state where an abnormal oscillation is generated,
the analog drive voltage command signal ADRV that is a conversion
output signal of the digital-to-analog converter 101 varies at an
oscillating voltage of a large amplitude.
[0180] Accordingly, the analog voltage of the analog drive voltage
command signal ADRV of the digital-to-analog converter 101 supplied
to the non-inverting input terminal(+) of the first comparator 1081
of the load short-circuit detection circuit 108 has, at an abnormal
oscillation cycle determined by an abnormal oscillation frequency,
an instantaneous value larger than the analog voltage threshold
value V.sub.TH supplied to the inverting input terminal(-) of the
first comparator 1081 of the load short-circuit detection circuit
108. As a result, from the output terminal of the first comparator
1081 of the load short-circuit detection circuit 108, the
comparison output pulse signal of a high level is generated at the
above-described abnormal oscillation cycle. Accordingly, in
response to the comparison output pulse signal of a high level
generated at the abnormal oscillation cycle, the counter 1082
counts up and the count-up value of the counter 1082 increases from
the zero value of a count initial value. Therefore, the count-up
value of the counter 1082 supplied to the non-inverting input
terminal(+) of the second comparator 1083 of the load short-circuit
detection circuit 108 becomes a value larger than the digital count
threshold value NTH supplied to the inverting input terminal(-) of
the second comparator 1083. Accordingly, the shutdown detection
signal SHT_DET as the load short-circuit detection signal generated
from the output terminal of the second comparator 1083 of the load
short-circuit detection circuit 108 becomes a high level. As a
result, a controller such as a microcomputer externally coupled to
the serial input/output interface 107 of the semiconductor
integrated circuit IC shown in FIG. 6 recognizes, from the shutdown
detection signal SHT_DET of a high level, that the both ends of the
voice coil motor (VCM) are in a short-circuit state and in an
abnormal operation state, and terminates the feedback control
operation of the drive current Ivcm of the coil of the voice coil
motor (VCM). For example, a controller such as a microcomputer sets
the digital value of the command information of the digital drive
current command value VCMCRNT to a zero value in response to the
shutdown detection signal SHT_DET of a high level. Thereby, the
feedback control operation of the current value of the drive
current Ivcm of the coil of the voice coil motor (VCM) is
terminated.
[0181] Note that, as other operation termination method, in
response to the shutdown detection signal SHT_DET of a high level
of the load short-circuit detection circuit 108, the operation of
the digital difference generation/phase compensation control
section 100 can be stopped, or the operation of the
digital-to-analog converter 101 can be stopped, or the operation of
the driver output section 102 can be stopped.
[0182] With the above-described semiconductor integrated circuit IC
according to the third embodiment shown in FIG. 6, in an abnormal
operation state where the both ends of the voice coil motor (VCM)
are in a short-circuit state, the feedback control operation of the
current value of the drive current Ivcm of the coil of the voice
coil motor (VCM) can be terminated. Accordingly, with the
semiconductor integrated circuit IC according to the third
embodiment shown in FIG. 6, smoke generation or firing of the voice
coil motor driver for driving the voice coil motor (VCM) can be
prevented in a state where both ends of the voice coil motor (VCM)
are short-circuited.
Fourth Embodiment
[0183] FIG. 7 is a view showing the configuration of a
semiconductor integrated circuit IC, called a voice coil motor
drive, for driving the voice coil motor (VCM) that moves a magnetic
head of the hard disk drive unit (HDD), according to a fourth
embodiment.
[0184] The semiconductor integrated circuit IC according to the
fourth embodiment shown in FIG. 7 differs from the semiconductor
integrated circuit IC according to the first embodiment shown in
FIG. 1, in the following points.
[0185] That is, the load short-circuit detection circuit 108 of the
semiconductor integrated circuit IC according to the fourth
embodiment shown in FIG. 7 includes the first comparator 1081, the
counter 1082, and the second comparator 1083.
[0186] The amplified output voltage as the voice coil motor drive
current information from the drive current detection amplifier 103
and the analog voltage threshold value V.sub.TH are supplied to the
non-inverting input terminal(+) and the inverting input terminal(-)
of the first comparator 1081 constituted as an analog comparator,
respectively. The comparison output signal of the first comparator
1081 constituted as an analog comparator is supplied to the count
input terminal of the counter 1082, and the shut-down enable signal
SHTD_ENA of a high level is supplied to the reset input terminal
rstn of the counter 1082, at a substantially constant time
interval.
[0187] The count output signal of the counter 1082 and the digital
count threshold value NTH generated from the serial input/output
interface 107 are supplied to the non-inverting input terminal(+)
and the inverting input terminal(-) of the second comparator 1083
constituted as a digital comparator, respectively. Furthermore,
from the output terminal of the second comparator 1083 constituted
as a digital comparator, the shutdown detection signal SHT_DET as
the load short-circuit detection signal is generated.
[0188] <<Operation of Load Short-Circuit Detection Circuit in
Abnormal Operation State>>
[0189] Next, hereinafter, there will be described the operation of
the load short-circuit detection circuit 108 included in the
semiconductor integrated circuit IC according to the fourth
embodiment shown in FIG. 7, in an abnormal operation state where
the both ends of the voice coil motor (VCM) are in a short-circuit
state.
[0190] Assume that the both ends of the voice coil motor (VCM) are
in a short-circuit state in both cases of the seek operation of the
magnetic head (when the PWM enable signal PWMENA is at a high
level) and of the track follow operation (when the PWM enable
signal PWMENA is at a low level). In this case, short-circuiting of
the both ends of the voice coil motor (VCM) puts the voice coil
motor driver into an extremely light load state, and thus the phase
margin becomes insufficient in feedback-controlling the drive
current of the coil of the voice coil motor and an abnormal
oscillation is generated. Due to this abnormal oscillation, an
abnormal oscillation waveform signal having a relatively large
amplitude is generated at the one of circuit nodes in a feedback
loop, from the output terminal of the digital subtractor 1002 of
the digital difference generation/phase compensation control
section 100 to one input terminal of the digital subtractor
1002.
[0191] In the state where this abnormal oscillation is generated,
the amplified output voltage as the voice coil motor drive current
information from the drive current detection amplifier 103 varies
at an oscillating voltage of a large amplitude.
[0192] Accordingly, the analog amplification output voltage of the
voice coil motor drive current information from the drive current
detection amplifier 103 supplied to the non-inverting input
terminal(+) of the first comparator 1081 of the load short-circuit
detection circuit 108 has, at an abnormal oscillation cycle
determined by an abnormal oscillation frequency, an instantaneous
value larger than the analog voltage threshold value V.sub.TH
supplied to the inverting input terminal(-) of the first comparator
1081 of the load short-circuit detection circuit 108. As a result,
from the output terminal of the first comparator 1081 of the load
short-circuit detection circuit 108, the comparison output pulse
signal of a high level is generated at the above-described abnormal
oscillation cycle. Accordingly, in response to the comparison
output pulse signal of a high level generated at the abnormal
oscillation cycle, the counter 1082 counts up and the count-up
value of the counter 1082 increases from the zero value of a count
initial value. Therefore, the count-up value of the counter 1082
supplied to the non-inverting input terminal(+) of the second
comparator 1083 of the load short-circuit detection circuit 108
becomes a value larger than the digital count threshold value NTH
supplied to the inverting input terminal(-) of the second
comparator 1083. Accordingly, the shutdown detection signal SHT_DET
as the load short-circuit detection signal generated from the
output terminal of the second comparator 1083 of the load
short-circuit detection circuit 108 becomes a high level. As a
result, a controller such as a microcomputer externally coupled to
the serial input/output interface 107 of the semiconductor
integrated circuit IC shown in FIG. 7 recognizes, from the shutdown
detection signal SHT_DET of a high level, that the both ends of the
voice coil motor (VCM) are in a short-circuit state and in an
abnormal operation state, and terminates the feedback control
operation of the drive current Ivcm of the coil of the voice coil
motor (VCM). For example, a controller such as a microcomputer sets
the digital value of the command information of the digital drive
current command value VCMCRNT to a zero value in response to the
shutdown detection signal SHT_DET of a high level. Thereby, the
feedback control operation of the current value of the drive
current Ivcm of the coil of the voice coil motor (VCM) is
terminated.
[0193] Note that, as other operation termination method, in
response to the shutdown detection signal SHT_DET of a high level
of the load short-circuit detection circuit 108, the operation of
the digital difference generation/phase compensation control
section 100 can be stopped, or the operation of the
digital-to-analog converter 101 can be stopped, or the operation of
the driver output section 102 can be stopped.
[0194] With the above-described semiconductor integrated circuit IC
according to the fourth embodiment shown in FIG. 7, in an abnormal
operation state where the both ends of the voice coil motor (VCM)
are in a short-circuit state, the feedback control operation of the
current value of the drive current Ivcm of the coil of the voice
coil motor (VCM) can be terminated. Accordingly, with the
semiconductor integrated circuit IC according to the fourth
embodiment shown in FIG. 7, smoke generation or firing of the voice
coil motor driver for driving the voice coil motor (VCM) can be
prevented in a state where both ends of the voice coil motor (VCM)
are short-circuited.
Fifth Embodiment
[0195] FIG. 8 is a view showing the configuration of a
semiconductor integrated circuit IC, called a voice coil motor
drive, for driving the voice coil motor (VCM) that moves a magnetic
head of the hard disk drive unit (HDD), according to a fifth
embodiment.
[0196] The semiconductor integrated circuit IC according to the
fifth embodiment shown in FIG. 8 differs from the semiconductor
integrated circuit IC according to the fourth embodiment shown in
FIG. 7, in the following points.
[0197] That is, in the semiconductor integrated circuit IC
according to the fifth embodiment shown in FIG. 8, the digital
difference generation/phase compensation control section 100 of the
semiconductor integrated circuit IC according to the fourth
embodiment shown in FIG. 7 is replaced with an analog difference
generation/phase compensation control section 109. From this
reason, the digital-to-analog converter 101 is coupled between the
serial input/output interface 107 and the analog difference
generation/phase compensation control section 109, and the command
information of the digital drive current command value VCMCRNT
supplied to the serial input/output interface 107 from a controller
is supplied to the digital-to-analog converter 101. The analog
drive current command value of the output of the digital-to-analog
converter 101 is supplied to one end of a resistor 1092 of the
analog difference generation/phase compensation control section
109.
[0198] Furthermore, the drive current detection amplifier 103 of
the semiconductor integrated circuit IC according to the fifth
embodiment shown in FIG. 8 has a circuit connection different from
the drive current detection amplifier 103 of the semiconductor
integrated circuit IC according to the fourth embodiment shown in
FIG. 7.
[0199] That is, in the drive current detection amplifier 103 shown
in FIG. 8, one current detection terminal RSINP is coupled to the
inverting input terminal(-) of the differential amplifier 1031 of
the drive current detection amplifier 103 via the resistor 1032,
and this inverting input terminal(-) is coupled to the output
terminal of the differential amplifier 1031 via the resistor 1033.
The other current detection terminal RSINN is coupled to the
non-inverting input terminal(+) of the differential amplifier 1031
of the drive current detection amplifier 103 via the resistor 1034,
and the reference voltage V.sub.REF is supplied to this inverting
input terminal(+) via the resistor 1035. Accordingly, the drive
current detection amplifier 103 shown in FIG. 8 generates an
inverted amplified voltage in response to the coil drive current
Ivcm flowing through the current sensing resistor Rs coupled in
series to the voice coil motor (VCM). The information about a drive
current inverted amplified voltage of the voice coil motor (VCM) of
the drive current detection amplifier 103 shown in FIG. 8 is
supplied to one end of a resistor 1093 of the analog difference
generation/phase compensation control section 109.
[0200] Accordingly, the resistor 1092 and the resistor 1093 of the
analog difference generation/phase compensation control section 109
of the semiconductor integrated circuit IC according to the fifth
embodiment shown in FIG. 8 executes an analog summation of the
analog drive current command value of the output of the
digital-to-analog converter 101 and the drive current inverted
amplified voltage of the voice coil motor (VCM) of the drive
current detection amplifier 103. That is, the resistors 1092 and
1093 executes analog subtraction AIERR of the analog drive current
command value of the output of the digital-to-analog converter 101
and a drive current non-inverting amplified voltage of the voice
coil motor (VCM) of the drive current detection amplifier 103.
[0201] In the analog difference generation/phase compensation
control section 109 of the semiconductor integrated circuit IC
according to the fifth embodiment shown in FIG. 8, other end of the
resistor 1092 and other end of the resistor 1093 are coupled to a
non-inverting input terminal(+) of a conductance amplifier 1091,
and the reference voltage V.sub.ref is supplied to an inverting
input terminal(-) of the conductance amplifier 1091. Furthermore,
between an output terminal of the conductance amplifier 1091 and
the reference voltage V.sub.ref, an integral resistor 1094 and an
integral capacitance 1095 constituted by an external component of
the semiconductor integrated circuit IC are coupled in series.
[0202] As a result, the conductance amplifier 1091 generates an
output current in response to the analog subtraction voltage AIERR
performed by two resistors 1092 and 1093, and therefore this output
current flows through the integral resistor 1094 and integral
capacitor 1095 coupled in series, and an analog subtraction
integrated voltage is generated from the output terminal of the
conductance amplifier 1091. Accordingly, the analog difference
generation/phase compensation control section 109 of the
semiconductor integrated circuit IC according to the fifth
embodiment shown in FIG. 8 executes analog signal processing
equivalent to the digital signal processing of the digital
difference generation/phase compensation control section 100 of the
semiconductor integrated circuit IC according to the fourth
embodiment shown in FIG. 7.
[0203] In contrast, the load short-circuit detection circuit 108 of
the semiconductor integrated circuit IC according to the fifth
embodiment shown in FIG. 8 includes the first comparator 1081, the
counter 1082, and the second comparator 1083.
[0204] To the non-inverting input terminal(+) and the inverting
input terminal(-) of the first comparator 1081 constituted as an
analog comparator, the analog subtraction voltage AIERR of two
resistors 1092 and 1093 of the analog difference generation/phase
compensation control section 109 and the analog voltage threshold
value V.sub.TH are supplied, respectively. The comparison output
signal of the first comparator 1081 constituted as an analog
comparator is supplied to the count input terminal of the counter
1082, and the shut-down enable signal SHTD_ENA of a high level is
supplied to the reset input terminal rstn of the counter 1082 at a
substantially constant time interval.
[0205] To a non-inverting input terminal(+) and an inverting input
terminal(-) of the second comparator 1083 constituted as a digital
comparator, a count output signal of the counter 1082 and a digital
count threshold value NTH generated from the serial input/output
interface 107 are supplied, respectively. Furthermore, from the
output terminal of the second comparator 1083 constituted as a
digital comparator, the shutdown detection signal SHT_DET as the
load short-circuit detection signal is generated.
[0206] <<Operation of Load Short-Circuit Detection Circuit in
Abnormal Operation State>>
[0207] Next, hereinafter, there will be described the operation of
the load short-circuit detection circuit 108 included in the
semiconductor integrated circuit IC according to the fifth
embodiment shown in FIG. 8, in an abnormal operation state where
the both ends of the voice coil motor (VCM) are in a short-circuit
state.
[0208] Assume that the both ends of the voice coil motor (VCM) are
in a short-circuit state in both cases of the seek operation of the
magnetic head (when the PWM enable signal PWMENA is at a high
level) and the track follow operation (when the PWM enable signal
PWMENA is at a low level). In this case, short-circuiting of the
both ends of the voice coil motor (VCM) puts the voice coil motor
driver into an extremely light load state, and thus the phase
margin becomes insufficient in feedback-controlling the drive
current of the coil of the voice coil motor and an abnormal
oscillation is generated. Due to this abnormal oscillation, an
abnormal oscillation waveform signal having a relatively large
amplitude is generated at the one of circuit nodes in a feedback
loop from the output terminal of the conductance amplifier 1091 of
the analog difference generation/phase compensation control section
109 to the non-inverting input terminal(+) of the conductance
amplifier 1091.
[0209] As described above, in an abnormal operation state where the
both ends of the voice coil motor (VCM) are in a short-circuit
state, the analog subtraction voltage AIERR of two resistors 1092
and 1093 of the analog difference generation/phase compensation
control section 109 does not become substantially zero.
Accordingly, the analog subtraction voltage AIERR of the analog
difference generation/phase compensation control section 109
supplied to the non-inverting input terminal(+) of the first
comparator 1081 of the load short-circuit detection circuit 108
has, at an abnormal oscillation cycle determined by an abnormal
oscillation frequency, an instantaneous value larger than the
analog voltage threshold value V.sub.TH supplied to the inverting
input terminal(-) of the first comparator 1081 of the load
short-circuit detection circuit 108. As a result, from the output
terminal of the first comparator 1081 of the load short-circuit
detection circuit 108, the comparison output pulse signal of a high
level is generated at the above-described abnormal oscillation
cycle. Accordingly, in response to the comparison output pulse
signal of a high level generated at the abnormal oscillation cycle,
the counter 1082 counts up and the count-up value of the counter
1082 increases from the zero value of a count initial value. As a
result, the count-up value of the counter 1082 supplied to the
non-inverting input terminal(+) of the second comparator 1083 of
the load short-circuit detection circuit 108 becomes a value larger
than the digital count threshold value NTH supplied to the
inverting input terminal(-) of the second comparator 1083.
Accordingly, the shutdown detection signal SHT_DET as the load
short-circuit detection signal generated from the output terminal
of the second comparator 1083 of the load short-circuit detection
circuit 108 becomes a high level. As a result, a controller, such
as a microcomputer, externally coupled to the serial input/output
interface 107 of the semiconductor integrated circuit IC shown in
FIG. 8 recognizes, from the shutdown detection signal SHT_DET of a
high level, that the both ends of the voice coil motor (VCM) are in
a short-circuit state and in an abnormal operation state, and
terminates the feedback control operation of the drive current Ivcm
of the coil of the voice coil motor (VCM). For example, a
controller, such as a microcomputer, sets the digital value of the
command information of the digital drive current command value
VCMCRNT to a zero value in response to the shutdown detection
signal SHT_DET of a high level.
[0210] Thereby, the feedback control operation of the current value
of the drive current Ivcm of the coil of the voice coil motor (VCM)
is terminated.
[0211] Note that, as other operation termination method, the
operation of the digital-to-analog converter 101 can be stopped or
the operation of the driver output section 102 can be stopped in
response to the shutdown detection signal SHT_DET of a high level
of the load short-circuit detection circuit 108.
[0212] With the above-described semiconductor integrated circuit IC
according to the fifth embodiment shown in FIG. 8, in an abnormal
operation state where the both ends of the voice coil motor (VCM)
are in a short-circuit state, the feedback control operation of the
current value of the drive current Ivcm of the coil of the voice
coil motor (VCM) can be terminated. Accordingly, with the
semiconductor integrated circuit IC according to the fifth
embodiment shown in FIG. 8, smoke generation or firing of the voice
coil motor driver for driving the voice coil motor (VCM) can be
prevented in the state where both ends of the voice coil motor
(VCM) are short-circuited.
[0213] As described above, although the invention made by the
present inventor has been described specifically on the basis of
the various embodiments, it is needless to say that the present
invention is not limited thereto and various modifications are
possible without departing from the gist of the invention.
[0214] For example, in the semiconductor integrated circuit IC
according to each of the second embodiment of FIG. 5, the third
embodiment of FIG. 6, and the fourth embodiment of FIG. 7, the
digital difference generation/phase compensation control section
100 can be replaced with the analog difference generation/phase
compensation control section 109, as with semiconductor integrated
circuit IC according to the fifth embodiment shown in FIG. 8. In
such a case, the circuit connection of the drive current detection
amplifier 103 of the semiconductor integrated circuit IC according
to each of the second embodiment of FIG. 5, the third embodiment of
FIG. 6, and the fourth embodiment of FIG. 7 is changed to the
circuit connection of the drive current detection amplifier 103 of
semiconductor integrated circuit IC according to the fifth
embodiment shown in FIG. 8.
[0215] Furthermore, the motor drive controller according to the
present invention is not limited only to the voice coil motor
driver for driving the voice coil motor (VCM) used in the hard disk
drive unit (HDD). For example, the present invention can be applied
also to a motor driver for driving an arm of an industrial robot
for performing ultra-precision machining works.
* * * * *