U.S. patent application number 14/856155 was filed with the patent office on 2016-01-07 for semiconductor device and method for manufacturing same.
This patent application is currently assigned to KABUSHIKI KAISHA TOSHIBA. The applicant listed for this patent is KABUSHIKI KAISHA TOSHIBA. Invention is credited to Johji Nishio, Chiharu OTA, Takashi Shinohe, Kazuto Takao.
Application Number | 20160005808 14/856155 |
Document ID | / |
Family ID | 50024606 |
Filed Date | 2016-01-07 |
United States Patent
Application |
20160005808 |
Kind Code |
A1 |
OTA; Chiharu ; et
al. |
January 7, 2016 |
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
Abstract
According to one embodiment, a semiconductor device, includes: a
first semiconductor region of a first conductivity type; a second
semiconductor region provided on the first semiconductor region, an
impurity concentration of the second semiconductor region being
lower than an impurity concentration of the first semiconductor
region; a third semiconductor region of a second conductivity type
provided on the second semiconductor region; and a fourth
semiconductor region provided on the third semiconductor region or
in a portion of the third semiconductor region. A lattice strain of
the fourth semiconductor region is greater than a lattice strain of
the third semiconductor region.
Inventors: |
OTA; Chiharu; (Kanagawa-ken,
JP) ; Nishio; Johji; (Tokyo, JP) ; Takao;
Kazuto; (Ibaraki-ken, JP) ; Shinohe; Takashi;
(Kanagawa-ken, JP) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
KABUSHIKI KAISHA TOSHIBA |
Tokyo |
|
JP |
|
|
Assignee: |
KABUSHIKI KAISHA TOSHIBA
Tokyo
JP
|
Family ID: |
50024606 |
Appl. No.: |
14/856155 |
Filed: |
September 16, 2015 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
13790282 |
Mar 8, 2013 |
9184229 |
|
|
14856155 |
|
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Current U.S.
Class: |
257/77 |
Current CPC
Class: |
H01L 29/8613 20130101;
H01L 29/872 20130101; H01L 29/1608 20130101; H01L 29/7395 20130101;
H01L 29/167 20130101; H01L 29/165 20130101; H01L 29/7802 20130101;
H01L 29/0615 20130101; H01L 29/161 20130101; H01L 29/6606 20130101;
H01L 21/0257 20130101; H01L 29/0638 20130101 |
International
Class: |
H01L 29/06 20060101
H01L029/06; H01L 29/16 20060101 H01L029/16 |
Foreign Application Data
Date |
Code |
Application Number |
Jul 31, 2012 |
JP |
2012-170278 |
Claims
1. (canceled)
2. A semiconductor device, comprising: a first electrode; a first
semiconductor region of a first conductivity type, the first
semiconductor region being provided on the first electrode and
electrically connected with the first electrode; a second
semiconductor region provided on the first semiconductor region, an
impurity concentration of the second semiconductor region being
lower than an impurity concentration of the first semiconductor
region, the second semiconductor region including a first pat
region and a second part region, the second part region being
arranged with the first part region in a first direction crossing a
second direction from the first electrode toward the first
semiconductor region; a third semiconductor region of a second
conductivity type provided on the first part region, the third
semiconductor region including a third part region and a fourth
part region, the fourth part region being arranged with the third
part region in a third direction crossing the second direction, the
fourth part region being located between the third part region and
the second part region; a fourth semiconductor region of the first
conductivity type, the fourth semiconductor region being provided
on the third part region, a fifth semiconductor region provided on
the fourth part region, a lattice strain of the fifth semiconductor
region being greater than a lattice strain of the third part
region, and greater than a lattice strain of the fourth part
region; a second electrode provided on the second part region; an
insulating film provided between the second electrode and the
second part region.
3. The device according to claim 2, wherein the fifth semiconductor
region includes an impurity different from an impurity included in
the third semiconductor region.
4. The device according to claim 3, wherein the impurity included
in the fifth semiconductor region includes an inert element.
5. The device according to claim 4, wherein the impurity is at
least one selected from Ar, Si, and C.
6. The device according to claim 2, wherein an impurity
concentration of the fifth semiconductor region is higher than an
impurity concentration of the third semiconductor region.
7. The device according to claim 2, wherein the first semiconductor
region, the second semiconductor region, the third semiconductor
region, the fourth semiconductor region and the fifth semiconductor
region include silicon carbide.
8. The device according to claim 2, wherein the first semiconductor
region is a substrate having a first surface and including
hexagonal silicon carbide, and the first surface of the substrate
is tilted more than 0 degrees and not more than 8 degrees with
respect to a basal plane of the silicon carbide.
9. The device according to claim 8, wherein the substrate includes
4H-SiC.
10. The device according to claim 2, wherein the fourth
semiconductor region includes an impurity different from an
impurity included in the third semiconductor region.
11. The device according to claim 10, wherein the impurity included
in the fourth semiconductor region includes an inert element.
12. The device according to claim 11, wherein the impurity is at
least one selected from Ar, Si, and C.
13. The device according to claim 2, wherein an impurity
concentration of the fourth semiconductor region is higher than an
impurity concentration of the third semiconductor region.
14. The device according to claim 2, wherein the impurity
concentration of the second semiconductor region is not less than
8.times.10.sup.14 cm.sup.-3 and not more than 1.times.10.sup.17
cm.sup.-3, an impurity concentration of the third semiconductor
region is not less than 1.times.10.sup.16 cm.sup.-3 and not more
than 5.times.10.sup.19 cm.sup.-3, and an impurity concentration of
the fourth semiconductor region is not less than 5.times.10.sup.17
cm.sup.-3 and not more than 1.times.10.sup.21 cm.sup.-3.
15. The device according to claim 2, wherein the first
semiconductor region, the second semiconductor region, the third
semiconductor region, and the fourth semiconductor region include
silicon carbide.
16. The device according to claim 2, wherein the first
semiconductor region is a substrate having a first surface and
including hexagonal silicon carbide, and the first surface of the
substrate is tilted more than 0 degrees and not more than 8 degrees
with respect to a basal plane of the silicon carbide.
17. The device according to claim 16, wherein the substrate
includes 4H-SiC.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is a divisional application of U.S.
application Ser. No. 13/790,282 filed Mar. 8, 2013, which is based
upon and claims the benefit of priority from the prior Japanese
Patent Application No. 2012-170278, filed on Jul. 31, 2012; the
entire contents of each are incorporated herein by reference.
FIELD
[0002] Embodiments described herein relate generally to a
semiconductor device and a method for manufacturing same.
BACKGROUND
[0003] Device structures and device materials to realize low-loss
semiconductor devices are desirable. By using, for example, silicon
carbide (SiC) as the material, it is possible to design with a
lower on-resistance and a higher breakdown voltage than when
silicon (Si) is used. There are cases where dislocations called
basal plane dislocations (BPDs) exist inside the semiconductor
substrate. It is known that the dislocations extend during the
device operation particularly in a bipolar mode; characteristic
fluctuation of the device occurs; and the loss increases. Because
the extension of the dislocations reduces the long-term reliability
of the device, it is necessary to suppress the characteristic
fluctuation of the semiconductor device recited above.
BRIEF DESCRIPTION OF THE DRAWINGS
[0004] FIG. 1 is a schematic cross-sectional view showing a
configuration of a semiconductor device according to a first
embodiment;
[0005] FIG. 2 shows a current-voltage characteristic of the
semiconductor device;
[0006] FIG. 3 is a flowchart showing a method for manufacturing the
semiconductor device according to the embodiment;
[0007] FIG. 4A is a schematic cross-sectional view showing the
method for manufacturing the semiconductor device according to the
embodiment;
[0008] FIG. 4B is a schematic cross-sectional view showing the
method for manufacturing the semiconductor device according to the
embodiment;
[0009] FIG. 4C is a schematic cross-sectional view showing the
method for manufacturing the semiconductor device according to the
embodiment;
[0010] FIG. 5A is a schematic cross-sectional view showing the
method for manufacturing the semiconductor device according to the
embodiment;
[0011] FIG. 5B is a schematic cross-sectional view showing the
method for manufacturing the semiconductor device according to the
embodiment;
[0012] FIG. 5C is a schematic cross-sectional view showing the
method for manufacturing the semiconductor device according to the
embodiment;
[0013] FIG. 6 is a schematic cross-sectional view showing a
configuration of a semiconductor device according to a third
embodiment;
[0014] FIG. 7 is a schematic cross-sectional view showing a
configuration of a semiconductor device according to a fourth
embodiment; and
[0015] FIG. 8 is a schematic cross-sectional view showing a
configuration of a semiconductor device according to a fifth
embodiment.
DETAILED DESCRIPTION
[0016] In general, according to one embodiment, a semiconductor
device includes: a first semiconductor region of a first
conductivity type; a second semiconductor region provided on the
first semiconductor region, an impurity concentration of the second
semiconductor region being lower than an impurity concentration of
the first semiconductor region; a third semiconductor region of a
second conductivity type provided on the second semiconductor
region; and a fourth semiconductor region provided on the third
semiconductor region or in a portion of the third semiconductor
region, a lattice strain of the fourth semiconductor region being
greater than a lattice strain of the third semiconductor
region.
[0017] In general, according to another embodiment, a method for
manufacturing a semiconductor device is provided. The method
includes: forming a second semiconductor region on a first
semiconductor region of a first conductivity type, an impurity
concentration of the second semiconductor region being lower than
an impurity concentration of the first semiconductor region;
forming a third semiconductor region of a second conductivity type
on the second semiconductor region; and forming a fourth
semiconductor region by performing ion implantation into the third
semiconductor region, a lattice strain of the fourth semiconductor
region being greater than a lattice strain of the third
semiconductor region.
[0018] Embodiments of the invention will now be described based on
the drawings.
[0019] The drawings are schematic or conceptual; and the
relationships between the thicknesses and the widths of portions,
the proportions of sizes between portions, etc., are not
necessarily the same as the actual values thereof. Further, the
dimensions and/or the proportions may be illustrated differently
between the drawings, even for identical portions.
[0020] In the drawings and the specification of the application,
components similar to those described in regard to a drawing
thereinabove are marked with like reference numerals, and a
detailed description is omitted as appropriate.
[0021] In the description hereinbelow, specific examples are
illustrated in which the first conductivity type is an n type and
the second conductivity type is a p type.
[0022] In the description hereinbelow, the notations of n.sup.+, n,
n.sup.-, p.sup.+, p, and p indicate relative degrees of the
impurity concentration of each of the conductivity types. In other
words, n.sup.+ is an n-type impurity concentration relatively
higher than n; and n.sup.- is an n-type impurity concentration
relatively lower than n. Also, p.sup.+ is a p-type impurity
concentration relatively higher than p; and p.sup.- is a p-type
impurity concentration relatively lower than p.
First Embodiment
[0023] FIG. 1 is a schematic cross-sectional view showing the
configuration of the semiconductor device according to the first
embodiment.
[0024] As shown in FIG. 1, the semiconductor device 110 according
to the first embodiment includes a substrate 10 which is a first
semiconductor region, a first epitaxial layer 20 which is a second
semiconductor region, a second epitaxial layer 30 which is a third
semiconductor region, and a defect suppression layer 40 which is a
fourth semiconductor region. The semiconductor device 110 further
includes a cathode electrode 70 which is a first electrode and an
anode electrode 80 which is a second electrode.
[0025] Such a semiconductor device 110 is, for example, a PiN
diode.
[0026] The substrate 10 is an n.sup.+-type semiconductor region.
The substrate 10 includes, for example, n.sup.+-type SiC. In the
embodiment, hexagonal SiC (e.g., 4H-SiC) is included in the
substrate 10. The substrate 10 is, for example, a SiC bulk
substrate made by sublimation.
[0027] The substrate 10 has a first surface 10a. The first surface
10a of the substrate 10 is the front surface of a wafer including
SiC. The first surface 10a also is an interface between the
substrate 10 and the first epitaxial layer 20. In the embodiment,
the first surface 10a of the substrate 10 is tilted more than 0
degrees and not more than 8 degrees with respect to the (0001)
plane which is the hexagonal SiC surface. For example, the
substrate 10 is a misoriented substrate such as a 2 degree
misoriented substrate, a 4 degree misoriented substrate, an 8
degree misoriented substrate, etc. Here, the front surface of the
substrate 10 of SiC may be a Si surface or a C surface. Basal plane
dislocations, which exist inside the basal plane of the substrate
10, exist in the interior of the substrate 10 that is the
misoriented substrate.
[0028] An n-type impurity is doped into the substrate 10; and the
impurity concentration of the n-type impurity is, for example, not
less than 1.times.10.sup.18 cm.sup.-3 and not more than
1.times.10.sup.20 cm.sup.-3. In the embodiment, the impurity
concentration is about 5.times.10.sup.18 cm.sup.-3.
[0029] The first epitaxial layer 20 is an n.sup.--type
semiconductor region. The first epitaxial layer 20 is a
semiconductor region that includes n.sup.--type SiC. The first
epitaxial layer 20 is formed on the first surface 10a of the
substrate 10 and has a crystal structure that is equivalent to that
of the substrate.
[0030] The thickness of the first epitaxial layer 20 is determined
by the design of the breakdown voltage characteristic and other
characteristics of the semiconductor device 110 and is, for
example, not more than about 200 micrometers (.mu.m). An n-type
impurity is doped into the first epitaxial layer 20; and the
impurity concentration of the n-type impurity is lower than the
impurity concentration of the substrate 10. The impurity
concentration of the first epitaxial layer 20 is, for example, not
less than 8.times.10.sup.14 cm.sup.-3 and not more than
1.times.10.sup.17 cm.sup.-3.
[0031] The second epitaxial layer 30 is a p.sup.+-type
semiconductor region. The second epitaxial layer 30 is a
semiconductor region made of p.sup.+-type SiC. The second epitaxial
layer 30 is formed on the first epitaxial layer 20.
[0032] The thickness of the second epitaxial layer 30 is, for
example, about several .mu.m. A p-type impurity is doped into the
second epitaxial layer 30; and the impurity concentration of the
p-type impurity is, for example, not less than 1.times.10.sup.16
cm.sup.-3 and not more than 5.times.10.sup.19 cm.sup.-3.
[0033] The impurity concentration of the second epitaxial layer 30
may change in the thickness direction. For example, the impurity
concentration of the front surface (the surface of the second
epitaxial layer 30 on the side opposite to the first epitaxial
layer 20) portion of the second epitaxial layer 30 may be highest;
and the impurity concentration of the portion of the surface of the
second epitaxial layer 30 on the first epitaxial layer 20 side may
be lowest.
[0034] For example, the impurity concentration of the front surface
portion of the second epitaxial layer 30 is set to be not less than
1.times.10.sup.15 cm.sup.-3 and not more than 2.times.10.sup.19
cm.sup.-3; and the impurity concentration of the portion of the
surface of the second epitaxial layer 30 on the first epitaxial
layer 20 side is set to be not less than 1.times.10.sup.18
cm.sup.-3 and not more than 1.times.10.sup.21 cm.sup.-3. The change
of the impurity concentration may be in stages or continuous.
Providing such a change of the impurity concentration achieves both
a higher breakdown voltage in the reverse direction due to the
enlargement of the spreading portion of the depletion layer and a
low contact resistance at the ohmic connection between the second
epitaxial layer 30 and the anode electrode 80.
[0035] The second epitaxial layer 30 is provided, for example, on a
portion of the first epitaxial layer 20. In other words, the second
epitaxial layer 30 is formed in a mesa shape.
[0036] The impurity concentration of the first epitaxial layer 20
on the second epitaxial layer 30 side (the pn junction interface
side) may be set to be higher than the impurity concentration on
the substrate 10 side. Thereby, the electric field when applying
the reverse voltage is concentrated not at the peripheral portion
but at the element central portion (the active region portion); and
the local electric field concentration due to the unbalance of the
structure at the peripheral portion is relaxed. As a result, the
reliability of the device increases.
[0037] The defect suppression layer 40 is provided on the second
epitaxial layer 30. The defect suppression layer 40 is a p-type
semiconductor region and may be provided in a portion of the second
epitaxial layer 30. The defect suppression layer 40 has a lattice
strain that is greater than the lattice strain of the second
epitaxial layer 30. The defect suppression layer 40 includes an
impurity that is different from the impurity included in the second
epitaxial layer 30. The impurity included in the defect suppression
layer 40 may include not only a conductive impurity but also an
inert element. In the case where the host semiconductor of the
defect suppression layer 40 is SiC, the impurity included in the
defect suppression layer 40 is, for example, argon (Ar), silicon
(Si), carbon (C), etc.
[0038] The defect suppression layer 40 is formed by, for example,
performing ion implantation into the front surface portion of the
second epitaxial layer 30. In the case where ion implantation into
the front surface portion of the second epitaxial layer 30 is
performed, lattice strain occurs in the crystal of the second
epitaxial layer 30. The lattice strain is the strain that occurs
due to the tensile stress occurring due to many atoms entering the
crystal. The portion where the lattice strain occurs is used as the
defect suppression layer 40. In other words, the lattice strain of
the defect suppression layer 40 is greater than the lattice strain
of the second epitaxial layer 30.
[0039] Here, the lattice strain is measured by, for example, Raman
spectroscopy and/or a TEM (Transmission Electron Microscope).
[0040] Thus, because the defect suppression layer 40 is a region
formed by performing ion implantation into at least the second
epitaxial layer 30, the impurity concentration of the defect
suppression layer 40 is higher than the impurity concentration (in
the case where multiple impurities are included, the total impurity
concentration) of the second epitaxial layer 30. For example, the
impurity concentration of the defect suppression layer 40 is higher
than the impurity concentration of the second epitaxial layer 30 by
a factor of 1000 or more. For example, although the impurity
concentration of the second epitaxial layer 30 is not less than
about 1.times.10.sup.16 cm.sup.-3 and not more than about
5.times.10.sup.19 cm.sup.-3, the impurity concentration of the
defect suppression layer 40 is not less than about
5.times.10.sup.17 cm.sup.-3 and not more than about
1.times.10.sup.21 cm.sup.-3.
[0041] The defect suppression layer 40 may be provided from the
region on the second epitaxial layer 30 to a region on the first
epitaxial layer 20. The reliability of the semiconductor device 110
increases further by the defect suppression layer 40 being provided
from the region on the second epitaxial layer 30 to a region on the
first epitaxial layer 20. For example, the number of the basal
planes appearing at the pn junction interface decreases as the off
angle of the misoriented substrate decreases. However, even in the
case where the basal plane is not exposed at the surface of the pn
junction, the basal plane dislocations existing in the portion
under the pn junction interface extend; and characteristic
degradation occurs. Therefore, the extension of the basal plane
dislocations is sufficiently suppressed even in the case where the
off angle is small by providing the defect suppression layer 40
from the region on the second epitaxial layer 30 to a region on the
first epitaxial layer 20 in a region that is as wide as
possible.
[0042] A terminal structure region 51 is provided on the first
epitaxial layer 20 around the second epitaxial layer 30 which is
formed in the mesa shape. The terminal structure region 51 is
provided, for example, to be continuous around the second epitaxial
layer 30. A channel stopper layer 53 is provided on the first
epitaxial layer 20 around the terminal structure region 51 to be
separated from the terminal structure region 51. For example, the
channel stopper layer 53 is provided around the terminal structure
region 51.
[0043] The terminal structure region 51 is, for example, a
p.sup.--type semiconductor region. The terminal structure region 51
is, for example, a JTE (Junction Termination Extension). Other than
a JTE, the terminal structure region 51 may be a RESURF layer, a
FLR (Field Limiting Ring), or a FP (field plate). The terminal
structure region 51 increases the breakdown voltage by relaxing the
electric field concentration at the terminal portion during a
reverse bias.
[0044] The cathode electrode 70 which is the first electrode is
provided at a second major surface 10b on the side of the substrate
10 opposite to the first surface 10a. The cathode electrode 70 is
electrically connected to the substrate 10. The cathode electrode
70 has an ohmic connection with the substrate 10. The anode
electrode 80 which is the second electrode is provided on the
defect suppression layer 40. The anode electrode 80 is electrically
connected to the second epitaxial layer 30. The anode electrode 80
has ohmic connections with the defect suppression layer 40 and the
second epitaxial layer 30.
[0045] In such a semiconductor device 110, the substrate 10 is the
N (the n-type semiconductor region) of the PiN diode. The first
epitaxial layer 20 is the i (the intrinsic semiconductor region) of
the PiN diode. The second epitaxial layer 30 and the defect
suppression layer 40 are the P (the p-type semiconductor region) of
the PiN diode.
[0046] Operations of the semiconductor device 110 will now be
described.
[0047] First, an operation of the semiconductor device 110 will be
described in the case where a voltage (a forward voltage) is
applied such that the anode electrode 80 is positive with respect
to the cathode electrode 70. In the case where the forward voltage
is applied, electrons and holes that exceed the built-in potential
flow via the pn junction surface existing at the interface between
the p.sup.+-type second epitaxial layer 30 and the n.sup.--type
first epitaxial layer 20. Thereby, the current flows in the
semiconductor device 110 (the forward operation).
[0048] An operation of the semiconductor device 110 will now be
described in the case where a voltage (a reverse voltage) is
applied such that the anode electrode 80 is negative with respect
to the cathode electrode 70. In the case where the reverse voltage
is applied, the depletion layer spreads mainly on the i layer side
of the pn junction surface; and a current substantially does not
flow in the semiconductor device 110 (the reverse operation).
[0049] An operation will now be described in the case where the
application of the forward voltage in the forward operation of the
semiconductor device 110 is continued further. In the semiconductor
device 110, the defect suppression layer 40 is provided on the
second epitaxial layer 30. A region having lattice strain is
included in the crystal interior of the defect suppression layer
40. By the defect suppression layer 40 having such a lattice
strain, stress acts due to the lattice strain inside the crystal
basal plane. Thereby, in the case where the application of the
forward voltage is continued, the occurrence of stacking faults
having starting points at the basal plane dislocations existing in
the crystal basal plane (in the case of a hexagonal crystal, the
(0001) plane for the Si surface and the (000-1) plane for the C
surface, and in the case of a cubic crystal, the (111 plane)) is
suppressed.
[0050] In the semiconductor device 110, the breakdown electric
field strength and the increase of the on-voltage that occur in the
case where the stacking faults occur is suppressed. Accordingly, in
the semiconductor device 110, the increase of the on-voltage and
the degradation of the breakdown voltage are suppressed over a long
period of time.
[0051] FIG. 2 shows the current-voltage characteristic of the
semiconductor device.
[0052] FIG. 2 shows the current (I)-voltage (V) characteristic of
the semiconductor device 110 according to the embodiment and the
I-V characteristic of a semiconductor device 190 according to a
reference example.
[0053] The semiconductor device 190 according to the reference
example does not include the defect suppression layer 40 of the
semiconductor device 110 according to the embodiment. Otherwise,
the configuration of the semiconductor device 190 is similar to
that of the semiconductor device 110.
[0054] As shown in FIG. 2, the necessary voltage value to cause the
current to flow can be lower for the semiconductor device 110
according to the embodiment than for the semiconductor device 190
according to the reference example. That is, the on-voltage is
lower for the semiconductor device 110 than for the semiconductor
device 190.
[0055] Dislocations called basal plane dislocations exist in the
substrate 10 of the semiconductor devices 110 and 190. The
dislocations extend during the device operation. This causes an
increase of the on-voltage and/or degradation of the breakdown
voltage.
[0056] It may be conjectured that this is due to the following
mechanism. Crystal defects called basal plane dislocations that
exist in the (0001) plane exist inside the substrate 10 in the case
where a hexagonal crystal is used as the substrate 10 of SiC. In
the case where epitaxial growth of SiC is performed on the
substrate 10 of SiC, generally, the cut surface of the crystal is
tilted several degrees from the (0001) plane; and step-flow growth
is performed.
[0057] In such a case, the basal plane dislocations propagate from
the first surface 10a of the substrate 10 of SiC into the epitaxial
layers (the first epitaxial layer 20 and the second epitaxial layer
30) of the SiC. Further, when current stress is applied, the basal
plane dislocations extend; and stacking faults occur. The stacking
faults that occur become high-resistance regions and cause the
forward characteristics of the element to degrade.
[0058] Particularly in the case of a high breakdown voltage device,
the region where the stacking faults occur may easily become large
because the layer that is epitaxial grown on the first surface 10a
of the substrate 10 is thick. That is, it is considered that
degradation of the forward characteristics markedly occurs in the
high breakdown voltage device.
[0059] As in the embodiment, in the case where the defect
suppression layer 40 is provided in the semiconductor device 110,
the stress due to the lattice strain provided in the defect
suppression layer 40 acts in the basal plane. Thereby, in the case
where the application of the forward voltage is continued, the
occurrence of the stacking faults having the basal plane
dislocations existing in the crystal basal plane as starting points
is suppressed. Accordingly, compared to the semiconductor device
190 which does not include the defect suppression layer 40, the
occurrence of the stacking faults is suppressed and the on-voltage
is reduced in the semiconductor device 110 which includes the
defect suppression layer 40.
[0060] Because the defect suppression layer 40 suppresses the
occurrence of the stacking faults having the basal plane
dislocations as starting points, the defect suppression layer 40
may be provided at positions as necessary according to the
positions and/or the density of the basal plane dislocations. For
example, the defect suppression layer 40 may be provided at a
portion, at the entirety, or at multiple locations of the first
epitaxial layer 20 and the second epitaxial layer 30. Thereby,
unnecessary ion implantation is avoided; and unnecessary
degradation of characteristics is prevented.
[0061] Here, because the defect suppression layer 40 of the
semiconductor device 110 has lattice strain, there is a possibility
that the properties of an ideal semiconductor material without
lattice strain cannot be maintained. However, the junction
interface of the semiconductor device 110 is the pn junction
interface of the element interior. Therefore, it is considered that
the relationship between the lattice strain provided in the defect
suppression layer 40 which is the front surface portion of the
semiconductor device 110 and the device characteristics such as the
static characteristics, the dynamic characteristics, etc., is
exceedingly weak. Accordingly, according to the structure of the
semiconductor device 110, the on-voltage and the breakdown voltage
are maintained for a long period of time without degradation of
other characteristics.
Second Embodiment
[0062] A method for manufacturing a semiconductor device according
to a second embodiment will now be described.
[0063] In the embodiment, a method for manufacturing a bipolar
diode (a PiN diode) that uses SiC will be described.
[0064] FIG. 3 is a flowchart showing the method for manufacturing
the semiconductor device according to the embodiment.
[0065] FIG. 4A to FIG. 5C are schematic cross-sectional views
showing the method for manufacturing the semiconductor device
according to the embodiment.
[0066] As shown in FIG. 3, the method for manufacturing the
semiconductor device according to the embodiment includes forming a
first epitaxial layer (step S101), forming a second epitaxial layer
(step S102), and forming a defect suppression layer (step
S103).
[0067] A specific example of the method for manufacturing the
semiconductor device shown in FIG. 3 will now be described with
reference to FIG. 4A to FIG. 5C.
[0068] First, as shown in FIG. 4A, the SiC bulk substrate 10 made
by sublimation, etc., is prepared. The doping concentration inside
the substrate 10 is not less than about 1.times.10.sup.18 cm.sup.-3
and not more than about 1.times.10.sup.20 cm.sup.-3. In the
embodiment, the case where the doping concentration of the
substrate 10 is 5.times.10.sup.18 cm.sup.-3 is used as an example.
The substrate 10 is an n.sup.+ type.
[0069] Then, the n.sup.--type first epitaxial layer 20 is formed on
the first surface 10a of the substrate 10. The first epitaxial
layer 20 is formed on the first surface 10a by, for example,
epitaxial growth. The doping concentration and thickness of the
n.sup.--type first epitaxial layer 20 are designed according to the
breakdown voltage and other characteristics of the element. For
example, the doping concentration is not less than about
8.times.10.sup.14 cm.sup.-3 and not more than about
1.times.10.sup.17 cm.sup.-3; and the thickness is not less than
about 5 .mu.m and not more than about 200 .mu.m. According to the
doping concentration and thickness of the first epitaxial layer 20,
a buffer layer (not shown) of the n conductivity type may be formed
between the substrate 10 and the first epitaxial layer 20. The
doping concentration of the buffer layer may be, for example, not
less than about 5.times.10.sup.17 cm.sup.-3 and not more than about
5.times.10.sup.18 cm.sup.-3; and the thickness of the buffer layer
may be from about several .mu.m to about several tens of .mu.m. The
buffer layer may be formed on the first surface 10a of the
substrate 10 by epitaxial growth.
[0070] Then, the p.sup.+-type second epitaxial layer 30 is formed
on the first epitaxial layer 20. The second epitaxial layer 30 is
formed on the first epitaxial layer 20 by, for example, epitaxial
growth. The second epitaxial layer 30 is formed using growth
conditions matched to the target characteristics that control the
spread of the depletion layer of the pn junction portion and reduce
the contact resistance of the front surface portion. The doping
concentration of the second epitaxial layer 30 is, for example, not
less than 1.times.10.sup.16 cm.sup.-3 and not more than
5.times.10.sup.19 cm.sup.-3; and the thickness of the second
epitaxial layer 30 is about several .mu.m.
[0071] The doping concentration of the second epitaxial layer 30
may change in the thickness direction (the direction connecting the
substrate 10 to the first epitaxial layer 20). For example, the
doping concentration may be changed deliberately in the thickness
direction by changing the conditions of the impurity concentration
for the second epitaxial layer 30. In such a case, the doping
concentration of the front surface portion (the shallow portion) of
the second epitaxial layer 30 may be set to be high; and the doping
concentration of the deep portion may be set to be low. By changing
the doping concentration, the change of the impurity concentration
of the second epitaxial layer 30 in the thickness direction may be
in stages or continuous.
[0072] Then, as shown in FIG. 4B, an etching mask (not shown) is
made at the central portion of the second epitaxial layer 30; and
the second epitaxial layer 30 is patterned into a mesa shape. Ionic
etching such as RIE (Reactive Ion Etching), etc., is applied to the
patterning. In the RIE, for example, etching using a fluorine (F)
or chlorine (Cl) gas is performed. The entire thickness of the
second epitaxial layer 30 is etched at the portion of the second
epitaxial layer 30 to be etched. Thereby, the n.sup.--type first
epitaxial layer 20 is exposed at the peripheral portion of the
second epitaxial layer 30 that remains without being etched.
[0073] In the case where the second epitaxial layer 30 is patterned
into the mesa shape, the patterning is not limited to a mesa shape
having one level; and the patterning conditions may be such that
the second epitaxial layer 30 is patterned into multiple
levels.
[0074] Then, as shown in FIG. 4C, ion implantation is performed for
the entire front surface of the second epitaxial layer 30 and the
first epitaxial layer 20. The ion species that is implanted may
include, for example, inert ions. Ar, Si, C, etc., may be used as
the ion species in the case where the second epitaxial layer 30 and
the first epitaxial layer 20 are SiC. From the aspect of providing
strain in the crystal, the implantation concentration is set to be
a concentration that is higher than the host concentration by a
factor of 1000 or more. The temperature when performing the ion
implantation may be higher than room temperature. The depth of the
ion implantation may be not less than 0.1 .mu.m and not more than
0.5 .mu.m.
[0075] From the aspect of providing the strain in the crystal,
phosphorus (P) and aluminum (Al) which have relatively large atomic
radii may be used as the ion species recited above. In such a case,
considering the effects of the device characteristics due to the
doping type and concentration, it is desirable to perform, for
example, counter implantation. Thereby, both the formation of the
strain and the adjustment of the carrier concentration can be
realized by the high number of ions.
[0076] The ion species that is implanted may be singular or
multiple. For example, an ion species that causes a large strain in
the crystal may be implanted into the second epitaxial layer 30
that is patterned into the mesa shape; and an ion species that
causes a small strain in the crystal may be implanted at the
peripheral portion of the second epitaxial layer 30. In the case
where there is a risk of autodoping, the defect suppression layer
40 may be formed after forming the JTE described below.
[0077] An ion implantation region 40A is formed at least on the
second epitaxial layer 30 by the ion implantation. The ion
implantation region 40A is the region that becomes the defect
suppression layer 40 by subsequent activation annealing. As in the
embodiment, the ion implantation region 40A is formed from the
region on the second epitaxial layer 30 to a region on the first
epitaxial layer 20 by performing ion implantation into the entire
front surface of the second epitaxial layer 30 and the first
epitaxial layer 20.
[0078] Then, as shown in FIG. 5A, the terminal structure region 51
is formed. For example, a p.sup.--type JTE, a RESURF layer, or a
guard ring layer may be used as the terminal structure region 51.
In the embodiment, the p.sup.--type JTE is formed. To form the
terminal structure region 51, first, a mask M1 is formed of an
insulating material or an organic material such as a resist, etc.,
that has openings; and ion implantation is performed via the
openings. Here, the JTE is formed by ion implantation with, for
example, an impurity concentration not less than 5.times.10.sup.16
cm.sup.-3 and not more than 5.times.10.sup.18 cm.sup.-3 and a
thickness not less than about 0.3 .mu.m and not more than about 0.5
.mu.m. It is desirable for the JTE to be formed to be deeper than
the thickness of the ion implantation region 40A formed previously.
Thereby, the electric field concentration during the reverse
voltage application does not occur easily.
[0079] Continuing as shown in FIG. 5B, the channel stopper layer 53
is formed as a portion that prevents the spread of the potential to
the end surface of the pn junction portion. Similarly to the
formation of the terminal structure region 51, the channel stopper
layer 53 is formed by forming a mask M2 having openings and
performing ion implantation via the openings. Thereby, the channel
stopper layer 53 is formed at the periphery of the terminal
structure region 51. The channel stopper layer 53 is formed to be
separated from the terminal structure region 51.
[0080] If necessary, ion implantation into the upper portion of the
second epitaxial layer 30 may be performed to reduce the contact
resistance. Then, after all of the ion implantation ends,
activation annealing is performed. In such a case, the strain of
the lattice positioned where the ion species is implanted also
spreads to the periphery due to the particle arrangement that
occurs for the large amount of the inert implantation species
introduced to the front surface of the first epitaxial layer 20 and
the second epitaxial layer 30. Thereby, a structure (the defect
suppression layer 40) is formed such that stress is applied inside
the basal plane.
[0081] Then, as shown in FIG. 5C, the cathode electrode 70 is
formed on the second major surface 10b of the substrate 10. Heat
treatment of the cathode electrode 70 is performed if necessary.
Subsequently, the anode electrode 80 is formed on the second
epitaxial layer 30. Heat treatment of the anode electrode 80 is
performed if necessary. Materials that can have low-resistance
ohmic junctions with the semiconductor regions that contact the
cathode electrode 70 and the anode electrode 80 are suitable as the
material of the cathode electrode 70 and the material of the anode
electrode 80.
[0082] If the semiconductor regions contacting the cathode
electrode 70 and the anode electrode 80 are SiC and if there are no
problems related to the heat treatment temperature of the cathode
electrode 70 and the heat treatment temperature of the anode
electrode 80, the cathode electrode 70 may be formed after the
anode electrode 80 is formed. If necessary, an insulating film, an
organic film, etc., may be formed around the substrate 10, the
first epitaxial layer 20, the second epitaxial layer 30, the defect
suppression layer 40, the terminal structure region 51, and the
channel stopper layer 53 to perform the role of preventing
discharge. Thereby, the semiconductor device 110 which includes the
defect suppression layer 40 is completed.
Third Embodiment
[0083] A third embodiment will now be described.
[0084] FIG. 6 is a schematic cross-sectional view showing the
configuration of a semiconductor device according to the third
embodiment.
[0085] As shown in FIG. 6, the semiconductor device 120 according
to the third embodiment includes the substrate 10 which is the
first semiconductor region, the first epitaxial layer which is the
second semiconductor region, the second epitaxial layer 30 which is
the third semiconductor region, the defect suppression layer 40
which is the fourth semiconductor region, a source region 35 which
is a fifth semiconductor region, a gate insulating film 60, a gate
electrode G, a drain electrode 71 which is a first electrode, and a
source electrode 81 which is a second electrode.
[0086] In other words, the semiconductor device 120 is a MOSFET
(Metal Oxide Semiconductor Field Effect Transistor).
[0087] The substrate 10 is, for example, an n.sup.+-type SiC bulk
substrate. Similarly to the semiconductor device 110 according to
the first embodiment, the substrate 10 is a misoriented substrate.
The first epitaxial layer 20 is a semiconductor region including
n.sup.--type SiC. The first epitaxial layer 20 has a prescribed
crystal structure formed on the first surface 10a of the substrate
10.
[0088] The second epitaxial layer 30 is a semiconductor region
including p-type SiC. The second epitaxial layer 30 has a
prescribed crystal structure formed on a portion of the first
epitaxial layer 20. Multiple second epitaxial layers 30 are
provided in the semiconductor device 120. The multiple second
epitaxial layers 30 are disposed to be separated from each other on
the first epitaxial layer 20.
[0089] The source region 35 is a semiconductor region including
n.sup.+-type SiC. The source region 35 is formed on a portion of
the second epitaxial layer 30. The source region 35 is formed by,
for example, ion implantation into the second epitaxial layer 30.
The region of the second epitaxial layer 30 between the source
region 35 and the first epitaxial layer 20 on a front surface 30a
side of the second epitaxial layer 30 is the region where a channel
is formed in the on-operation. Multiple source regions 35 are
provided in the semiconductor device 120. The multiple source
regions 35 are provided respectively in the multiple second
epitaxial layers 30.
[0090] The defect suppression layer 40 is provided at least on or
in a portion of the second epitaxial layer 30. In the embodiment,
the defect suppression layer 40 is provided in the portion of the
second epitaxial layer 30 that contacts the source electrode 81.
The defect suppression layer 40 may be further provided on or in a
portion of the source region 35.
[0091] The gate insulating film 60 is provided at least on the
front surface 30a of the second epitaxial layer 30. The gate
electrode G is provided on the gate insulating film 60. An
insulating film 61 is provided between the gate electrode G and the
source electrode 81.
[0092] The source electrode 81 contacts the source region 35. The
source electrode 81 has an ohmic contact with the source region 35.
In the embodiment, the source electrode 81 also contacts the second
epitaxial layer 30. Thereby, the source electrode 81 functions as a
common electrode of the source region 35 and the second epitaxial
layer 30 of the MOSFET.
[0093] The drain electrode 71 contacts the second major surface 10b
of the substrate 10. The drain electrode 71 has an ohmic connection
with the substrate 10.
[0094] Operations of the semiconductor device 120 will now be
described.
[0095] An inversion layer (a channel) is formed in the second
epitaxial layer 30 proximally to the interface between the second
epitaxial layer 30 and the gate insulating film 60 when a voltage
equal to or greater than the threshold is applied to the gate
electrode G in the state in which a voltage that is positive with
respect to the source electrode 81 is applied to the drain
electrode 71. Thereby, the semiconductor device 120 is switched to
the on-state; and a current flows from the drain electrode 71 into
the source electrode 81.
[0096] On the other hand, the channel vanishes when the voltage
applied to the gate electrode G is less than the threshold.
Thereby, the semiconductor device 120 is switched to the off-state;
and the current flowing from the drain electrode 71 into the source
electrode 81 is broken.
[0097] In the semiconductor device 120 which is a MOSFET, a pn
junction interface is formed between the first epitaxial layer 20
and the second epitaxial layer 30. The pn junction interface
functions as the body diode of the MOSFET.
[0098] By providing the defect suppression layer 40 to a prescribed
depth from the front surface 30a of the second epitaxial layer 30
in the semiconductor device 120, similarly to the semiconductor
device 110 according to the first embodiment, the on-voltage and
the breakdown voltage are maintained for a long period of time
without degradation of other characteristics.
[0099] In the MOSFET, it is desirable to design the formation
position of the defect suppression layer 40 by considering that the
characteristics are affected by the impurities proximal to the gate
insulating film 60 and particularly in the region where the channel
is formed. For example, the defect suppression layer 40 is not
provided in the region where the channel is formed.
Fourth Embodiment
[0100] A fourth embodiment will now be described.
[0101] FIG. 7 is a schematic cross-sectional view showing the
configuration of a semiconductor device according to the fourth
embodiment.
[0102] As shown in FIG. 7, the semiconductor device 130 according
to the fourth embodiment includes the substrate 10 which is the
first semiconductor region, the first epitaxial layer 20 which is
the second semiconductor region, the second epitaxial layer 30
which is the third semiconductor region, the defect suppression
layer 40 which is the fourth semiconductor region, an emitter
region 36 which is the fifth semiconductor region, the gate
insulating film 60, the gate electrode G, a collector electrode 72
which is the first electrode, and an emitter electrode 82 which is
the second electrode.
[0103] In other words, the semiconductor device 130 is an IGBT
(Insulated Gate Bipolar Transistor).
[0104] The semiconductor device 130 differs from the semiconductor
device 120 in that the conductivity type of the substrate 10 is the
p.sup.+-type. In the semiconductor device 130, the substrate 10 is,
for example, a p.sup.+-type SiC bulk substrate. In the
semiconductor device 130, the first epitaxial layer 20 is a
semiconductor region including n.sup.--type SiC. The first
epitaxial layer 20 is used as the drift layer of the IGBT.
[0105] In the semiconductor device 130, the second epitaxial layer
30 is a semiconductor region including p.sup.--type SiC. The second
epitaxial layer 30 has a prescribed crystal structure formed on a
portion of the first epitaxial layer 20. The second epitaxial layer
30 is used as the base region of the IGBT. Multiple second
epitaxial layers 30 are provided in the semiconductor device 130.
The multiple second epitaxial layers 30 are disposed to be
separated from each other on the first epitaxial layer 20.
[0106] The emitter region 36 is a semiconductor region including
n.sup.+-type SiC. The emitter region 36 corresponds to the source
region 35 of the semiconductor device 120. Multiple emitter regions
36 are provided in the semiconductor device 130. The multiple
emitter regions 36 are provided respectively in the multiple second
epitaxial layers 30.
[0107] The defect suppression layer 40 is provided at least on or
in a portion of the second epitaxial layer 30. In the embodiment,
the defect suppression layer 40 is provided in a portion of the
second epitaxial layer 30 that contacts the source electrode 81.
The defect suppression layer 40 may be further provided on or in a
portion of the emitter region 36.
[0108] The gate insulating film 60 is provided at least on the
front surface 30a of the second epitaxial layers 30. The gate
electrode G is provided on the gate insulating film 60. The gate
electrode G is provided on two mutually-adjacent second epitaxial
layers 30 with the gate insulating film 60 interposed. The
insulating film 61 is provided between the gate electrode G and the
emitter electrode 82.
[0109] The emitter electrode 82 contacts the emitter region 36. The
emitter electrode 82 has an ohmic connection with the emitter
region 36. In the embodiment, the emitter electrode 82 also
contacts the second epitaxial layer 30. Thereby, the emitter
electrode 82 functions as a common electrode of the emitter region
36 and the second epitaxial layer 30 of the IGBT.
[0110] The collector electrode 72 contacts the second major surface
10b of the substrate 10. The collector electrode 72 has an ohmic
connection with the substrate 10.
[0111] Operations of the semiconductor device 130 will now be
described.
[0112] When a voltage equal to or greater than the threshold is
applied to the gate electrode G in the state in which a voltage
that is positive with respect to the emitter electrode 82 is
applied to the collector electrode 72, an inversion layer (a
channel) is formed in the second epitaxial layer 30 which is the
base region proximally to the interface between the second
epitaxial layer 30 and the gate insulating film 60. Thereby,
electrons are injected from the emitter region 36 into the second
epitaxial layer 30 (the base region) via the channel; and the state
is switched to the on-state. Also at this time, holes are injected
from the collector electrode 72 into the first epitaxial layer 20
(the drift region). The holes injected into the drift region flow
through the base region into the emitter electrode 82. In the
on-state of the semiconductor device 130, the holes from the
collector electrode 72 are injected into the drift region;
conductivity modulation occurs; and the resistance of the drift
region decreases.
[0113] On the other hand, the channel vanishes when the voltage
applied to the gate electrode G is less than the threshold.
Thereby, the semiconductor device 130 is switched to the off-state;
and the current flowing from the collector electrode 72 into the
emitter electrode 82 is broken.
[0114] Because the operation of the semiconductor device 130 which
is an IGBT has a bipolar mode, similarly to the semiconductor
device 110 according to the first embodiment, the occurrence of the
stacking faults having the basal plane dislocations as starting
points is suppressed. Accordingly, the occurrence of the stacking
faults in the semiconductor device 130 which includes the defect
suppression layer 40 is suppressed; and the on-voltage and the
breakdown voltage are maintained for a long period of time without
degradation of other characteristics.
[0115] In the IGBT as well, similarly to the MOSFET, it is
desirable to design the formation position of the defect
suppression layer 40 by considering that the characteristics are
affected by the impurities proximal to the gate insulating film 60
and particularly in the region where the channel is formed. For
example, the defect suppression layer 40 is not provided in the
region where the channel is formed.
Fifth Embodiment
[0116] A fifth embodiment will now be described.
[0117] FIG. 8 is a schematic cross-sectional view showing the
configuration of a semiconductor device according to the fifth
embodiment.
[0118] As shown in FIG. 8, the semiconductor device 140 according
to the fifth embodiment includes the substrate 10 which is the
first semiconductor region, the first epitaxial layer which is the
second semiconductor region, the second epitaxial layer 30 which is
the third semiconductor region, the defect suppression layer 40
which is the fourth semiconductor region, the cathode electrode 70
which is the first electrode, and the anode electrode 80 which is
the second electrode.
[0119] In other words, the semiconductor device 140 is a MPS
(Merged PiN Schottky) diode.
[0120] The substrate 10 is, for example, an n.sup.+-type SiC bulk
substrate. Similarly to the semiconductor device 110 according to
the first embodiment, the substrate 10 is a misoriented substrate.
The first epitaxial layer 20 is a semiconductor region including
n.sup.--type SiC. The first epitaxial layer 20 has a prescribed
crystal structure formed on the first surface 10a of the substrate
10.
[0121] The second epitaxial layer 30 is a semiconductor region
including p-type SiC. The second epitaxial layer 30 has a
prescribed crystal structure formed on a portion of the first
epitaxial layer 20. The second epitaxial layer 30 is multiply
provided on a front surface 20a side of the first epitaxial layer
20 at a prescribed spacing.
[0122] The anode electrode 80 includes ohmic electrodes 85 and a
Schottky electrode 86. The ohmic electrodes 85 are provided on the
second epitaxial layers 30. The ohmic electrodes 85 have ohmic
connections with the second epitaxial layers 30.
[0123] The Schottky electrode 86 is provided on the ohmic
electrodes 85 and covers the front surface 20a of the first
epitaxial layer 20. The Schottky electrode 86 has a Schottky
contact with the first epitaxial layer 20.
[0124] The cathode electrode 70 contacts the second major surface
10b of the substrate 10. The cathode electrode 70 has an ohmic
connection with the substrate 10.
[0125] The defect suppression layer 40 is provided at least on or
in a portion of the second epitaxial layers 30. In the embodiment,
the defect suppression layer 40 is provided in portions of the
second epitaxial layer 30 that contact the ohmic electrodes 85. The
defect suppression layer 40 may be provided from the portions of
the second epitaxial layers 30 contacting the ohmic electrodes 85
to a region on the front surface 20a of the first epitaxial layer
20 if there are no problems relating to the characteristics.
[0126] Operations of the semiconductor device 140 will now be
described.
[0127] First, an operation of the semiconductor device 140 will be
described in the case where a voltage (a forward voltage) is
applied such that the anode electrode 80 is positive with respect
to the cathode electrode 70. In the case where the forward voltage
is applied, electrons that exceed the energy barrier flow from the
first epitaxial layer 20 into the Schottky electrode 86 (the anode
electrode 80). The electrons and the holes that exceed the built-in
potential flow via the pn junction surfaces existing at the
interface between the p.sup.+-type second epitaxial layers 30 and
the n.sup.--type first epitaxial layer 20. Thereby, the current
flows in the semiconductor device 140 (the forward operation).
[0128] An operation of the semiconductor device 140 will now be
described in the case where a voltage (a reverse voltage) is
applied such that the anode electrode 80 is negative with respect
to the cathode electrode 70. In the case where the reverse voltage
is applied, a depletion layer spreads on the first epitaxial layer
20 side of the interface between the Schottky electrode 86 and the
first epitaxial layer 20. The depletion layer spreads mainly on the
i layer side of the pn junction surface. Thereby, substantially no
current flows in the semiconductor device 140 (the reverse
operation).
[0129] The semiconductor device 140 which is a MPS diode has both
the characteristics of a Schottky barrier diode and the
characteristics of a PiN diode. Namely, the semiconductor device
140 has a low on-voltage and excellent recovery
characteristics.
[0130] Because the operation of the semiconductor device 130 which
is a MPS diode has a bipolar mode, similarly to the semiconductor
device 110 according to the first embodiment, the occurrence of the
stacking faults having the basal plane dislocations as starting
points is suppressed. Accordingly, the occurrence of the stacking
faults in the semiconductor device 140 which includes the defect
suppression layer 40 is suppressed; and the on-voltage and the
breakdown voltage are maintained for a long period of time without
degradation of other characteristics.
[0131] As described above, according to the semiconductor device
and the method for manufacturing the semiconductor device according
to the embodiments, the long-term reliability of the semiconductor
device can be increased.
[0132] Although the embodiments and modifications thereof are
described above, the invention is not limited to these examples.
For example, additions, deletions, or design modifications of
components or appropriate combinations of the features of the
embodiments appropriately made by one skilled in the art in regard
to the embodiments and modifications thereof described above are
within the scope of the invention to the extent that the spirit of
the invention is included.
[0133] For example, although the first conductivity type is the n
type and the second conductivity type is the p type in the
description of the embodiments and modifications thereof described
above, the invention is practicable also in the case where the
first conductivity type is the p type and the second conductivity
type is the n type. The embodiments and the modifications described
above are applicable to devices on either the Si surface or the C
surface.
[0134] Although the case is illustrated in the embodiments
described above where SiC is applied as the substrate 10, the first
epitaxial layer 20, and the second epitaxial layer 30, the
materials of these components are not limited to SiC; and the
embodiments are applicable also to materials that include crystal
defects and stacking faults that propagate from the basal
plane.
[0135] While certain embodiments have been described, these
embodiments have been presented by way of example only, and are not
intended to limit the scope of the inventions. Indeed, the novel
embodiments described herein may be embodied in a variety of other
forms; furthermore, various omissions, substitutions and changes in
the form of the embodiments described herein may be made without
departing from the spirit of the inventions. The accompanying
claims and their equivalents are intended to cover such forms or
modifications as would fall within the scope and spirit of the
invention.
* * * * *