U.S. patent application number 14/549086 was filed with the patent office on 2015-12-17 for array substrate and display device.
This patent application is currently assigned to BOE TECHNOLOGY GROUP CO., LTD.. The applicant listed for this patent is BOE TECHNOLOGY GROUP CO., LTD.. Invention is credited to HONGFEI CHENG, Pan Li, Wenbo Li, Yong Qiao, Jianbo Xian.
Application Number | 20150364494 14/549086 |
Document ID | / |
Family ID | 51651298 |
Filed Date | 2015-12-17 |
United States Patent
Application |
20150364494 |
Kind Code |
A1 |
CHENG; HONGFEI ; et
al. |
December 17, 2015 |
ARRAY SUBSTRATE AND DISPLAY DEVICE
Abstract
The present disclosure provides an array substrate and a display
device. The array substrate includes gate lines, data lines, and
thin film transistors (TFTs) connected to the gate lines and the
data lines. At least one of the data lines is divided into a first
branch and a second branch at a predetermined region where an
intersection of the at least one of the data lines and at least one
of the gate lines is located. The first branch overlaps the at
least one of the gate lines, and has a width less than a width of a
non-overlapping portion of the at least one of the data lines which
does not overlap the at least one of the gate lines. The second
branch overlaps a gate electrode of a corresponding one of the
TFTs, and serves as, or is connected to, a source electrode of the
corresponding TFT.
Inventors: |
CHENG; HONGFEI; (Beijing,
CN) ; Qiao; Yong; (Beijing, CN) ; Xian;
Jianbo; (Beijing, CN) ; Li; Wenbo; (Beijing,
CN) ; Li; Pan; (Beijing, CN) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
BOE TECHNOLOGY GROUP CO., LTD. |
Beijing |
|
CN |
|
|
Assignee: |
BOE TECHNOLOGY GROUP CO.,
LTD.
Beijing
CN
|
Family ID: |
51651298 |
Appl. No.: |
14/549086 |
Filed: |
November 20, 2014 |
Current U.S.
Class: |
257/72 |
Current CPC
Class: |
H01L 27/124 20130101;
G02F 1/1368 20130101; G02F 1/136286 20130101 |
International
Class: |
H01L 27/12 20060101
H01L027/12 |
Foreign Application Data
Date |
Code |
Application Number |
Jun 12, 2014 |
CN |
201420313509.7 |
Claims
1. An array substrate, comprising a plurality of gate lines, a
plurality of data lines intersecting with the gate lines, and a
plurality of thin film transistors (TFTs) connected to the gate
lines and the data lines, wherein at least one of the data lines is
divided into a first branch and a second branch at a predetermined
region where an intersection of the at least one of the data lines
and at least one of the gate lines is located; the first branch
overlaps the at least one of the gate lines; the first branch has a
width less than a width of a non-overlapping portion of the at
least one of the data lines which does not overlap the at least one
of the gate lines, and the second branch overlaps a gate electrode
of a corresponding one of the TFTs, and serves as, or is connected
to, a source electrode of the corresponding TFT; wherein a first
end of the second branch is connected to a first end of the first
branch, and a second end of the second branch is connected to a
second end of the first branch.
2. The array substrate according to claim 1, wherein the second
branch has a width less than the width of the non-overlapping
portion of the at least one of the data lines which does not
overlap the at least one of the gate lines.
3. The array substrate according to claim 1, wherein a gap is
defined between the first branch and the second branch.
4. The array substrate according to claim 3, wherein the at least
one of the gate lines is provided with a widening portion; the
widening portion has a width greater than a width of a
non-overlapping portion of the at least one of the gate lines that
does not overlap the at least one of the data lines; the widening
portion overlaps the second branch as the gate electrode of the
corresponding TFT, and a part of the widening portion is located in
the gap between the first branch and the second branch.
5. The array substrate according to claim 1, wherein the at least
one of the gate lines comprises a thinning portion; the thinning
portion overlaps the first branch; the thinning portion has a width
less than a width of a non-overlapping portion of the at least one
of the gate lines that does not overlap the at least one of the
data lines.
6. The array substrate according to claim 5, wherein there is a gap
defined between the first branch and the second branch.
7. The array substrate according to claim 6, wherein the at least
one of the gate lines is provided with a widening portion; the
widening portion has a width greater than the width of the
non-overlapping portion of the at least one of the gate lines that
does not overlap the at least one of the data lines; the widening
portion overlaps the second branch as the gate electrode of the
corresponding TFT; and a part of the widening portion is located in
the gap between the first branch and the second branch.
8. The array substrate according to claim 7, wherein the widening
portion and the thinning portion are arranged in abutment with each
other.
9. The array substrate according to claim 7, wherein the at least
one of the gate lines extends in a first direction, the at least
one of the data lines extends in a second direction perpendicular
to the first direction; the widening portion and the thinning
portion are arranged in abutment with each other in the first
direction.
10. The array substrate according to claim 7, wherein a region is
defined between an edge of the first branch which is located
adjacent to the second branch and an extension line of an edge of
the non-overlapping portion of the at least one of the data lines
which does not overlap the at least one of the gate lines and which
is located adjacent to the second branch, and a part of the
widening portion is located in the region.
11. array substrate according to claim 10, wherein the region is
located within the gap.
12-13. (canceled)
14. A display device, comprising an array substrate, wherein the
array substrate comprises a plurality of gate lines, a plurality of
data lines intersecting with the gate lines, and a plurality of
thin film transistors (TFTs) connected to the gate lines and the
data lines, and wherein at least one of the data lines is divided
into a first branch and a second branch at a predetermined region
where an intersection of the at least one of the data lines and at
least one of the gate lines is located; the first branch overlaps
the at least one of the gate lines; the first branch has a width
less than a width of a non-overlapping portion of the at least one
of the data lines which does not overlap the at least one of the
gate lines, and the second branch overlaps a gate electrode of a
corresponding one of the TFTs, and serves as, or is connected to, a
source electrode of the corresponding TFT; wherein a first end of
the second branch is connected to a first end of the first branch,
and a second end of the second branch is connected to a second end
of the first branch.
15. The display device according to claim 14, wherein a gap is
defined between the first branch and the second branch.
16. The display device according to claim 15, wherein the at least
one of the gate lines is provided with a widening portion; the
widening portion has a width greater than a width of a
non-overlapping portion of the at least one of the gate lines that
does not overlap the at least one of the data lines; the widening
portion overlaps the second branch as the gate electrode of the
corresponding TFT, and a part of the widening portion is located in
a gap between the first branch and the second branch.
17. The display device according to claim 16, wherein the at least
one of the gate lines comprises a thinning portion; the thinning
portion overlaps the first branch; the thinning portion has a width
less than the width of the non-overlapping portion of the at least
one of the gate lines that does not overlap the at least one of the
data lines.
18. The display device according to claim 17, wherein the at least
one of the gate lines extends in a first direction, the at least
one of the data lines extends in a second direction perpendicular
to the first direction, and the widening portion and the thinning
portion are arranged in abutment with each other in the first
direction.
19. The display device according to claim 16, wherein the
corresponding TFT further comprises a drain electrode, and the
array substrate further comprises a pixel electrode corresponding
to the corresponding TFT and in electrical connection to the drain
electrode.
20. An array substrate, comprising a plurality of gate lines, a
plurality of data lines intersecting with the gate lines, and a
plurality of thin film transistors (TFTs) connected to the gate
lines and the data lines, wherein at least one of the data lines is
divided into a first branch and a second branch at a predetermined
region where an intersection of the at least one of the data lines
and at least one of the gate lines is located; the first branch
overlaps the at least one of the gate lines; the first branch has a
width less than a width of a non-overlapping portion of the at
least one of the data lines which does not overlap the at least one
of the gate lines, and the second branch overlaps a gate electrode
of a corresponding one of the TFTs, and serves as, or is connected
to, a source electrode of the corresponding TFT; wherein a gap is
defined between the first branch and the second branch; wherein the
at least one of the gate lines comprises a first portion, a second
portion and a third portion; the first portion does not overlap the
at least one of the data lines and has a first width; the second
portion has a second width greater than the first width; the second
portion overlaps the second branch as the gate electrode of the
corresponding TFT, and a part of the second portion is located in
the gap between the first branch and the second branch; the third
portion overlaps the first branch; the third portion has a third
width less than the first width.
21. The array substrate according to claim 20, wherein a first end
of the second branch is connected to a first end of the first
branch, and a second end of the second branch is not connected to a
second end of the first branch.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] The present application claims a priority of the Chinese
patent application No. 201420313509.7 filed on Jun. 12, 2014, which
is incorporated herein by reference in its entirety.
FIELD OF THE INVENTION
[0002] The present disclosure relates to the field of display
technology, in particular to an array substrate and a display
device.
DESCRIPTION OF THE PRIOR ART
[0003] Liquid crystal display technology has been widely used in
TVs, mobile telephones and public information distributed systems.
A liquid crystal display panel includes an array substrate and a
color film substrate arranged opposite to each other to form a
cell. The array substrate includes a plurality of gate lines and a
plurality of data lines that intersect with each other. A coupling
capacitance, present at an overlapping portion between the gate
line and the data line, will adversely affect the transmission of a
gate line signal and a data line signal, and thus deteriorate the
display quality. Along with an increasing size of the display
panel, such a situation grows steadily worse.
SUMMARY OF THE INVENTION
[0004] In view of this, the present disclosure provides an array
substrate and a display device, which can reduce a coupling
capacitance at an overlapping region between a gate line and a data
line.
[0005] In order to solve the above technical problem, one
embodiment of the present disclosure provides an array substrate
including a plurality of gate lines, a plurality of data lines
intersecting with the gate lines, and a plurality of thin film
transistors (TFTs) connected to the gate lines and the data lines.
At least one of the data lines is divided into a first branch and a
second branch at a predetermined region where an intersection of
the at least one of the data lines and at least one of the gate
lines is located. The first branch overlaps the at least one of the
gate lines; the first branch has a width less than a width of a
non-overlapping portion of the at least one of the data lines which
does not overlap the at least one of the gate lines. The second
branch overlaps a gate electrode of a corresponding one of the
TFTs, and serves as, or is connected to, a source electrode of the
corresponding TFT.
[0006] Further, the second branch has a width less than the width
of the non-overlapping portion of the at least one of the data
lines which does not overlap the at least one of the gate
lines.
[0007] Further, the at least one of the gate lines includes a
thinning portion; the thinning portion overlaps the first branch;
the thinning portion has a width less than a width of a
non-overlapping portion of the at least one of the gate lines that
does not overlap the at least one of the data lines.
[0008] Further, the at least one of the gate lines is provided with
a widening portion; the widening portion has a width greater than
the width of the non-overlapping portion of the at least one of the
gate lines that does not overlap the at least one of the data
lines; the widening portion overlaps the second branch as the gate
electrode of the corresponding TFT. A part of the widening portion
is located in the gap between the first branch and the second
branch.
[0009] Further, the widening portion and the thinning portion are
arranged in abutment with each other.
[0010] Further, the at least one of the gate lines extends in a
first direction, the at least one of the data lines extends in a
second direction perpendicular to the first direction; the widening
portion and the thinning portion are arranged in abutment with each
other in the first direction.
[0011] Further, a region is defined between an edge of the first
branch which is located adjacent to the second branch and an
extension line of an edge of the non-overlapping portion of the at
least one of the data lines which does not overlap the at least one
of the gate lines and which is located adjacent to the second
branch, and a part of the widening portion is located in the
region.
[0012] Further, the region is located within the gap.
[0013] Further, a first end of the second branch is connected to a
first end of the first branch, and a second end of the second
branch is connected to a second end of the first branch.
[0014] Further, a first end of the second branch is connected to a
first end of the first branch, and a second end of the second
branch is not connected to a second end of the first branch.
[0015] One embodiment of the present disclosure provides a display
device including the above-mentioned array substrate.
[0016] The present disclosure has following advantageous
effect.
[0017] The first branch of the data line overlaps the gate line,
and the second branch overlaps the gate electrode of the TFT. Since
the width of the first branch is less than the width of the
non-overlapping portion of the data line that does not overlap the
gate line, thus, an area of an overlapping region between the data
line and the gate line may be reduced and the coupling capacitance
therebetween may be reduced, thereby improving a display effect of
the display device including the array substrate.
BRIEF DESCRIPTION OF THE DRAWINGS
[0018] FIG. 1 is a schematic view showing an array substrate
according to one embodiment of the present disclosure;
[0019] FIG. 2 is a sectional view of the array substrate taken
along a line A1-A2 in FIG. 1;
[0020] FIG. 3 is a schematic view showing an array substrate
according to another embodiment of the present disclosure;
[0021] FIG. 4 is a schematic view showing a data line according to
one embodiment of the present disclosure; and
[0022] FIG. 5 is a schematic view showing a gate line according to
one embodiment of the present disclosure.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0023] In order to prevent a display effect of a display panel from
being adversely affected due to signal delay caused by the coupling
capacitance present at an overlapping portion between a gate line
and a data line in an existing array substrate, one embodiment of
the present disclosure provides an array substrate including a
plurality of gate lines, a plurality of data lines intersecting
with the gate lines, and a plurality of TFTs connected to the gate
lines and the data lines. The data line is divided into a first
branch and a second branch at a predetermined region where an
intersection of the data line and the gate line is located. The
first branch overlaps the gate line. The first branch has a width
less than a width of a non-overlapping portion of the data line
which does not overlap the gate lines. The second branch overlaps a
gate electrode of the TFT, and serves as, or is connected to, a
source electrode of the TFT.
[0024] The predetermined region where the intersection of the data
line and the gate line refers to an overlapping region between the
data line and the gate line, or a region adjacent to the
overlapping region.
[0025] The non-overlapping portion of the data line that does not
overlap the gate line refers to a portion of the data line rather
than the first branch and the second branch.
[0026] In one embodiment, the first branch of the data line
overlaps the gate line and the second branch overlaps the gate
electrode of the TFT, i.e., an actual overlapping region between
the data line and the gate line is an overlapping region between
the first branch and the gate line. Since the width of the first
branch is less than a width of the non-overlapping portion of the
data line that does not overlap the gate line, thus, an area of the
overlapping region between the data line and the gate line may be
reduced and the coupling capacitance between the data line and the
gate line may be reduced, thereby improving a display effect of a
display device including the array substrate of one embodiment of
the present disclosure.
[0027] In one embodiment of the present disclosure, the second
branch of the data line overlaps the gate electrode of the TFT, and
serves as, or is connected to, the source electrode of the TFT.
Optionally, the second branch of the data line has a width less
than the width of the non-overlapping portion of the data line that
does not overlap the gate line, so as to reduce the coupling
capacitance between the gate electrode and the source electrode of
the TFT.
[0028] In order to further reduce the area of the overlapping
region between the data line and the gate line, optionally, the
gate line includes a thinning portion. The thinning portion
overlaps the first branch. The thinning portion has a width less
than a width of a non-overlapping portion of the gate line that
does not overlap the data line.
[0029] Optionally, the gate line is provided with a widening
portion. The widening portion has a width greater than the width of
the non-overlapping portion of the gate line that does not overlap
the data line. The widening portion overlaps the second branch as
the gate electrode of the TFT. A part of the widening portion is
located in a gap between the first branch and the second
branch.
[0030] Further, a region is formed between an edge of the first
branch which is located adjacent to the second branch and an
extension line of an edge of the non-overlapping portion of the
data line which does not overlap the gate line and which is located
adjacent to the second branch, and a part of the widening portion
is located in the region, so as to reduce an area of a pixel region
occupied by the TFT, thereby increasing an aperture ratio of a
pixel and further improving the display effect of the display
device.
[0031] In order to make the objects, the technical solutions and
the advantages of the present disclosure more apparent, the present
disclosure will be described hereinafter in conjunction with the
drawings and the embodiments.
[0032] FIG. 1 is a schematic view showing an array substrate
according to one embodiment of the present disclosure. FIG. 2 is a
sectional view of the array substrate taken along a line A1-A2 in
FIG. 1. FIG. 4 is a schematic view showing a data line according to
one embodiment of the present disclosure. FIG. 5 is a schematic
view showing a gate line according to one embodiment of the present
disclosure.
[0033] The array substrate includes a plurality of gate lines 10, a
plurality of data lines 20 intersecting with the gate lines 10, and
a plurality of TFTs connected to the gate lines 10 and the data
lines 20.
[0034] The data line 20 is divided into a first branch 20a and a
second branch 20b at a predetermined region where an intersection
of the data line 20 and the gate line 10 is located. A first end of
the second branch 20b is connected to a first end of the first
branch 20a, and a second end of the second branch 20b is connected
to a second end of the first branch 20a. In other words, as viewed
from top to bottom when the array substrate is located at position
shown in FIG. 1, the data line 20 is divided into the first branch
20a and the second branch 20b at a part of the data line 20
adjacent to the intersection of the data line 20 and the gate line
10; and the first branch 20a and the second branch 20b converge
after they pass through the intersection. Of course, in another
embodiment of the present disclosure, the first branch 20a and the
second branch 20b may not converge after they pass through the
intersection, i.e., the first end of the second branch 20b is
connected to the first end of the first branch 20a, and the second
end of the second branch 20b is not connected to the second end of
the first branch 20a.
[0035] As viewed from left to right when the array substrate is
located at the position shown in FIG. 1, the gate line 10 is
thinned at a part of the gate line 10 adjacent to the intersection
of the gate line 10 and the data line 20, thereby forming a
thinning portion 10a. The thinning portion 10a overlaps the first
branch 20a. In a gap 20c between the first branch 20a and the
second branch 20b of the data line 20, a part of the gate line 10
is thickened, thereby forming a widening portion lob. In other
words, a part of the widening portion 10b is located in the gap 20c
between the first branch 20a and the second branch 20b. The
widening portion 10b overlaps the second branch 20b as the gate
electrode of the TFT.
[0036] In this embodiment, a region 43 is formed between an edge 41
of the first branch 20a which is located adjacent to the second
branch 20b and an extension line 42 of an edge of the
non-overlapping portion of the data line 20 which does not overlap
the gate line 10 and which is located adjacent to the second branch
20b, and a part of the widening portion 10b is located in the
region 43, so as to reduce the area of the pixel region occupied by
the TFT and increase the aperture ratio of the pixel, thereby
further improving the display effect of the display device.
[0037] Referring to FIG. 4, both of a width W20a of the first
branch 20a and a width W20b of the second branch 20b are less than
a width W20 of the non-overlapping portion of the data line 20 that
does not overlap the gate line 10.
[0038] Referring to FIG. 5, a width W10a of the thinning portion
10a is less than a width W10 of the non-overlapping portion of the
gate line 10 that does not overlap the data line 20. A width W10b
of the widening portion 10b is greater than the width W10 of the
non-overlapping portion of the gate line 10 that does not overlap
the data line 20.
[0039] The TFT includes the gate electrode, an active layer 13, a
source electrode 21 and a drain electrode 22. The gate electrode of
the TFT is just the widening portion 10b, and the source electrode
21 thereof is connected to the second branch 20b of the data
line.
[0040] In this embodiment, the TFT includes a U-shaped channel.
Since the U-shaped channel has a large width to length ratio, thus
the TFT has a large on-state current.
[0041] The array substrate further includes a base plate 1, a gate
insulating layer 12 and a pixel electrode 32. The pixel electrode
32 is in electrical connection with the drain electrode 32 through
a via-hole 31.
[0042] FIG. 3 is a schematic view showing an array substrate
according to another embodiment of the present disclosure. The
array substrate in this embodiment differs from that in the
previous embodiment in that the second branch 20b of the data line
is directly used as the source electrode of the TFT, i.e., a
portion indicated by the reference sign 21 in FIG. 1 is
omitted.
[0043] In the above embodiments, the gate line 10 and the data line
20 may be made of a metallic material such as Cu, Al, Mo, Ti, Cr
and W, or an alloy thereof. The gate line 10 may be of a
single-layered structure or a multi-layered structure, e.g.,
Mo/Al/Mo, Ti/Cu/Ti or Mo/Ti/Cu.
[0044] In the above embodiments, the gate insulating layer 12 may
be made of SiN or SiO. The gate insulating layer 12 may be of a
single-layered structure or a multi-layered structure, e.g.,
SiO/SiN.
[0045] In the above embodiments, the active layer 13 may be made of
amorphous silicon, polycrystalline silicon, microcrystalline
silicon or an oxide semiconductive material.
[0046] In the above embodiments, the array substrate may further
include a passivation layer 30 made of an inorganic matter such as
SiN.
[0047] In the above embodiments, the pixel electrode 32 may be made
of ITO, IZO, or any other transparent metal oxide conductive
material.
[0048] A method for manufacturing the array substrate will be
described hereinafter in conjunction with FIG. 2. The method
includes steps of:
[0049] (1) depositing a metal layer, e.g., Al, on the base plate 1
by sputtering, applying a photoresist onto the metal layer, and
exposing, developing and etching the photoresist so as to form a
pattern of the gate line 10;
[0050] (2) depositing the gate insulating layer 12, e.g., SiN, by
PECVD;
[0051] (3) depositing a semiconductor layer, e.g., continuously
depositing a-Si and n+a-Si by PECVD or depositing IGZO by
sputtering, applying a photoresist onto the semiconductor layer,
and exposing, developing and etching the photoresist so as to form
a pattern of the active layer 13; and
[0052] (4) depositing a metal layer, e.g., Al, by sputtering,
applying a photoresist onto the metal layer, and exposing,
developing and etching the photoresist to form patterns of the data
line 20, the source electrode 21 and the drain electrode 22.
[0053] The method may further include steps of:
[0054] (5) depositing the passivation layer 30, e.g., SiN, by
PECVD, applying a photoresist onto the passivation layer 30, and
exposing, developing and etching the photoresist to form the
via-hole 31 through which the drain electrode 22 of a first TFT is
exposed; and
[0055] (6) depositing a layer of a transparent metal oxide
conductive material, e.g., ITO, by sputtering, applying a
photoresist onto the layer, and exposing, developing and etching
the photoresist to form a pattern of the pixel electrode 32.
[0056] The present disclosure further provides a display device
including the above-mentioned array substrate.
[0057] The above are merely the preferred embodiments of the
present disclosure. It should be appreciated that, a person skilled
in the art may make further improvements and modifications without
departing from the principle of the present disclosure, and these
improvements and modifications shall also fall within the scope of
the present disclosure.
* * * * *