U.S. patent application number 14/813610 was filed with the patent office on 2015-11-26 for three dimensional semiconductor device having lateral channel and method of manufacturing the same.
This patent application is currently assigned to SK hynix Inc.. The applicant listed for this patent is SK hynix Inc.. Invention is credited to Suk Ki KIM.
Application Number | 20150340463 14/813610 |
Document ID | / |
Family ID | 52389786 |
Filed Date | 2015-11-26 |
United States Patent
Application |
20150340463 |
Kind Code |
A1 |
KIM; Suk Ki |
November 26, 2015 |
THREE DIMENSIONAL SEMICONDUCTOR DEVICE HAVING LATERAL CHANNEL AND
METHOD OF MANUFACTURING THE SAME
Abstract
A 3D semiconductor device and a method of manufacturing the same
are provided. The 3D semiconductor device includes a semiconductor
substrate, an insulating layer formed on the semiconductor
substrate, an active line including a source region and a drain
region formed on the insulating layer, a gate electrode located on
a portion of the active line, corresponding to a region between the
source region and the drain region, and extending to a direction
substantially perpendicular to the active line, and a line-shaped
common source node formed to be electrically coupled to the source
region and extending substantially in parallel to the gate
electrode in a space between gate electrodes.
Inventors: |
KIM; Suk Ki; (Gyeonggi-do,
KR) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
SK hynix Inc. |
Gyeonggi-do |
|
KR |
|
|
Assignee: |
SK hynix Inc.
|
Family ID: |
52389786 |
Appl. No.: |
14/813610 |
Filed: |
July 30, 2015 |
Related U.S. Patent Documents
|
|
|
|
|
|
Application
Number |
Filing Date |
Patent Number |
|
|
14074452 |
Nov 7, 2013 |
9129984 |
|
|
14813610 |
|
|
|
|
Current U.S.
Class: |
438/151 ;
438/299 |
Current CPC
Class: |
H01L 45/126 20130101;
H01L 21/02236 20130101; H01L 45/1233 20130101; H01L 45/16 20130101;
H01L 27/2463 20130101; H01L 29/66477 20130101; H01L 29/66613
20130101; H01L 29/6681 20130101; H01L 27/2436 20130101; H01L 27/228
20130101; H01L 21/02532 20130101; H01L 45/06 20130101; H01L 45/141
20130101; H01L 45/147 20130101; H01L 45/14 20130101; H01L 45/04
20130101 |
International
Class: |
H01L 29/66 20060101
H01L029/66; H01L 21/02 20060101 H01L021/02 |
Foreign Application Data
Date |
Code |
Application Number |
Jul 26, 2013 |
KR |
10-2013-0088910 |
Claims
1. A method of manufacturing a semiconductor device, the method
comprising: sequentially stacking a first semiconductor layer and a
second semiconductor layer on a substrate; forming an active line
by patterning the second semiconductor layer and the first
semiconductor layer; forming a source region and a drain region in
predetermined regions of the active line; entirely oxidizing the
first semiconductor layer constituting the active line, and forming
an insulating layer on a surface of the second semiconductor layer;
forming line-shaped dummy patterns crossing the active line to pass
through the source region and the drain region; forming a gate
electrode in a region between the line-shaped dummy patterns;
selectively removing the line-shaped dummy pattern passing through
the source region; and forming a line-shaped common source node in
a region from which the line-shaped dummy pattern is removed.
2. The method of claim 1, wherein, the first semiconductor layer
includes a material having a higher oxidation rate than that of the
second semiconductor layer.
3. The method of claim 2, wherein the first semiconductor layer
includes a silicon germanium (Site) layer, and the second
semiconductor layer includes a silicon (Si) layer.
4. The method of claim wherein the forming of the gate electrode
includes: forming a conductive layer to be buried in the region
between the line-shaped dummy patterns; and recessing the
conductive layer.
5. A method of manufacturing a semiconductor device, the method
comprising: forming an active line layer on a substrate; forming an
active line pattern that extend to a first direction, by patterning
the active line layer; forming a source region and a drain region
in predetermined regions of the active line; forming line-shaped
dummy patterns on the active line pattern to pass through the
source region and the drain region, wherein the line-shaped dummy
patterns extend to a second direction that is substantially
perpendicular to the first direction; forming a gate electrode in a
region between the line-shaped dummy patterns, wherein the gate
electrode extend in parallel to the second direction; selectively
removing the line-shaped dummy pattern passing through the source
region; and forming a line-shaped common source node in a region
from which the line-shaped dummy pattern is removed.
6. The method of claim 5, wherein the forming of he gate electrode
includes: forming a conductive layer to be buried in the region
between the line-shaped dummy patterns; and recessing the
conductive layer.
Description
CROSS-REFERENCES TO RELATED APPLICATION
[0001] This application is a division of U.S. patent application
Ser. No. 14/074,452 filed on Nov. 7, 2013, which claims priority
under 35 U.S.C. 119(a) to Korean application No. 10-2013-0088910,
filed on Jul. 26, 2013, in the Korean patent intellectual property
Office. The disclosure of each of the foregoing application is
incorporated by reference in its entirety as set forth in full.
BACKGROUND
[0002] 1. Technical Field
[0003] The inventive concept relates to a semiconductor integration
circuit device, and more particularly, to a semiconductor device
having three-dimensional' (3D) lateral channel and a method of
manufacturing the same.
[0004] 2. Related Art
[0005] With the rapid development of mobile and digital information
communication and consumer electronic industry, studies on existing
electronic charge controlled devices may encounter limitations.
Thus, new functional memory devices of novel concepts other than
the existing electronic charge devices need to be developed. In
particular, next generation memory devices with large capacity,
ultra-high speed, and ultra-low power need to be developed.
[0006] Currently, resistance variable memory devices using a
resistance device as a memory medium have been suggested as the
next generation memory devices. Typical examples of resistive
variable memory devices are phase-change random access memories
(PCRAMs), resistance RAMs (ReRAMs), and magentoresistive RAMs
(MRAMs).
[0007] Each of the resistance variable memory devices may be
basically formed of a switching device and a resistance device and
store data "0" or "1" according to a state of the resistance
device.
[0008] Even in the resistive variable memory devices, the first
priority is to improve integration density and to integrate as many
memory cells as possible in a limited small area.
[0009] Currently, methods of forming the resistance variable memory
devices in 3D structures are suggested, and demands on methods of
stably stacking a plurality of memory cells with a narrow critical
dimension are growing.
[0010] As a manufacturing method of a typical 3D structure
resistance variable memory device, there is a method of
manufacturing a switching device using a vertical pillar. However,
the method of manufacturing a switching device using the vertical
pillar may have a concern in that a fabrication process of the
switching device is complex, and an aspect ratio is increased due
to a height of the vertical pillar, and thus the semiconductor
device is structurally unstable. 3D lateral channel structure is
suggested. The 3D lateral channel structure is a structure in which
an active region having a lateral channel (a lateral fin structure
or a lateral channel region) in a 3D structure is formed on a
semiconductor substrate unlike an existing buried type. In this 3D
lateral channel semiconductor device, in general, the lateral fin
structure is electrically coupled to the semiconductor substrate
through a common source node.
[0011] However, a manufacturing process of the 3D lateral channel
semiconductor device may include a process of aligning a channel of
the active region with the common source node, and a process of
aligning a gate (a word line) with the channel of the active
region. Therefore, a process defect such as misalignment may occur
in the manufactur g process.
SUMMARY
[0012] According to an exemplary embodiment of the present
invention, there is provided a semiconductor device. The
semiconductor device may include a semiconductor substrate, an
insulating layer formed on the semiconductor substrate, an active
line including a source region and a drain region formed on the
insulating layer, a gate electrode located on a portion of the
active line, corresponding to a region between the source region,
and the drain region and extending to a direction substantially
perpendicular to the active line, and a line-shaped common source
node formed to be electrically coupled to the source region and
extending substantially in parallel to the gate electrode in a
space between gate electrodes.
[0013] According to an exemplary embodiment of the present
invention, there is provided a semiconductor device. The
semiconductor device may include a semiconductor substrate, a
plurality of active lines floating over the substrate and extending
in parallel to a first direction, a plurality of gate electrodes
formed on each of the active lines and extending in parallel to a
second direction that is substantially perpendicular to the first
direction, a plurality of line-shaped common source nodes formed on
each of the active lines, extending in parallel to the second
direction, and located between the gate electrodes, drain regions
formed in each of the active lines at one sides of the gate
electrodes, and source regions formed in each of the active lines
at the other sides of the gate electrodes.
[0014] According to an exemplary embodiment of the present
invention, there is provided a method of manufacturing a
semiconductor device. The method may include sequentially stacking
a first semiconductor layer and a second semiconductor layer on a
semiconductor substrate, forming an active line by patterning the
second semiconductor layer and the first semiconductor layer,
forming a source region and a drain region in predetermined regions
of the active line; entirely oxidizing the first semiconductor
layer constituting the active line, and forming an insulating layer
on a surface of the second semiconductor layer; forming line-shaped
dummy patterns crossing the active line to pass through the source
region and the drain region, forming a gate electrode in a region
between the line-shaped dummy patterns, selectively removing the
line-shaped dummy pattern passing through the source region, and
forming a line-shaped common source node in a region from which the
line-shaped dummy pattern is removed.
[0015] Further, a hard mask layer may be formed on the gate
electrode between the forming of the gate electrode and the
removing of the dummy pattern.
[0016] Further, the source region and the drain region may be
exposed by selectively removing a dummy pattern on the drain region
simultaneously in the selectively removing of the dummy pattern
passing through the source region. And then, a heating electrode
may be formed on the exposed drain region simultaneously in the
forming of the common source node.
[0017] Further, a spacer insulating layer may be formed on the
heating electrode and the common source node to expose the heating
electrode and shield the common source node, and resistance
variable material layers may be formed on the heating electrode and
the common source node.
[0018] These and other features, aspects, and embodiments are
described below in the section entitled "DETAILED DESCRIPTION".
BRIEF DESCRIPTION OF THE DRAWINGS
[0019] The above and other aspects, features and other advantages
of the subject matter of the present disclosure will be more
clearly understood from the following detailed description taken in
conjunction with the accompanying drawings, in which:
[0020] FIGS. 1A to 1E are plan views illustrating a method of
manufacturing a semiconductor device having a 3D lateral channel
according to an embodiment of the inventive concept;
[0021] FIGS. 2A to 2E are cross-sectional views illustrating the
method of manufacturing the semiconductor device having the 3D
lateral channel shown in FIGS. 1A to 1E, taken along lines II-II'
of FIGS. 1A to 1E;
[0022] FIGS. 3A to 3E are cross-sectional views illustrating the
method of manufacturing the semiconductor device having the 3D
lateral channel shown in FIGS. 1A to 1E, taken along lines III-III'
of FIGS. 1A to 1E;
[0023] FIGS. 4A to 4E are cross-sectional views illustrating the
method of manufacturing the semiconductor device having the 3D
lateral channel shown in FIGS. 1A to 1E, taken along lines IV-IV'
of FIGS. 1A to 1E;
[0024] FIG. 5 is a perspective view illustrating a semiconductor
device having a 3D lateral channel according to an embodiment of
the inventive concept;
[0025] FIG. 6 is a block diagram illustrating a microprocessor
according to an embodiment of the inventive concept;
[0026] FIG. 7 is a block diagram illustrating a processor according
to an embodiment of the inventive concept; and
[0027] FIG. 8 is a block diagram illustrating a system according to
an embodiment of the inventive concept.
DETAILED DESCRIPTION
[0028] Hereinafter, exemplary embodiments will be described in
greater detail with reference to the accompanying drawings.
Exemplary embodiments are described herein with reference to
cross-sectional illustrations that are schematic illustrations of
exemplary embodiments (and intermediate structures). As such,
variations from the shapes of the illustrations as a result, for
example, of manufacturing techniques and/or tolerances, are to be
expected. Thus, exemplary embodiments should not be construed as
limited to the particular shapes of regions illustrated herein but
may be to include deviations in shapes that result, for example,
from manufacturing. In the drawings, lengths and sizes of layers
and regions may be exaggerated for clarity. Like reference numerals
in the drawings denote like elements. It is also understood that
when a layer is referred to as being "on" another layer or
substrate, it can be directly on the other layer or substrate, or
intervening layers may also be present. It is also noted that in
this specification, "connected/coupled" refers to one component not
only directly coupling another component but also indirectly
coupling another component through an intermediate component. In
addition, a singular form may include a plural form as long as it
is not specifically mentioned in a sentence.
[0029] The inventive concept is described herein with reference to
cross-section and/or plan illustrations that are schematic
illustrations of idealized embodiments of the inventive concept.
However, embodiments of the inventive concept should not be limited
construed as limited to the inventive concept. Although a few
embodiments of the inventive concept will be shown and described,
it will be appreciated by those of ordinary skill in the art that
changes may be made in these exemplary embodiments without
departing from the principles and spirit of the inventive
concept.
[0030] In the embodiment, a resistance variable memory device among
semiconductor devices will be described as an example.
[0031] Referring to FIGS. 1A, 2A, 3A, and 4A, a first semiconductor
layer 105 and a second semiconductor layer 110 may be sequentially
formed on a semiconductor substrate 100. The first semiconductor
layer 105 and the second semiconductor layer 110 may be formed of
materials having etching selectivities and oxidation rates
different from each other. The first semiconductor layer 105 may be
a layer for defining a common source node in a subsequent process,
and may include, for example, a silicon germanium (SiGe) layer. The
second semiconductor layer 110 may be a layer in which a junction
region and a channel region are to be formed, and formed thicker
than the first semiconductor layer 105. The first and second
semiconductor layers 105 and 110 may be formed through an epitaxial
growth method to have a perfect crystalline state. The second and
first semiconductor layers 110 and 105 may be patterned in a fin
shape to form a plurality of active lines F. Further, in FIG. 1A,
GT_P may denote a gate formation region, and DGT_P may be a dummy
gate formation region. A plurality of gate formation regions GT_P
may extend to be parallel to each other, and may be arranged
substantially to be perpendicular to the active lines F. Further,
one dummy gate formation region DGT_P may be formed in an interval
of every two gate formation regions GT_P to substantially separate
cells. In FIG. 1A, PS may denote a common source node formation
region.
[0032] Referring to FIGS. 1B, 2B, 3B, and 4B, a dummy layer may be
formed on the semiconductor substrate in which the active line F is
formed. The dummy layer may be patterned to be located in a line
shape between the gate formation regions GT_P and between the gate
formation region GT_P and the dummy gate formation region DGT_P to
form a dummy pattern 120 having a line shape. The dummy pattern 120
may be formed of a conductive layer, for example, a polysilicon
layer.
[0033] Before the dummy pattern 120 is formed, a source region S
and a drain region D may be alternately formed in portions of the
second semiconductor layer 110 corresponding to dummy patterns 120.
The process of forming the source and drain regions S and D may be
performed after a mask is formed on the gate formation region GT_P
and the dummy gate formation region DGT_P.
[0034] An oxidation process may be performed on the exposed
semiconductor substrate 100 to form first and second insulating
layers 115 and 117 between the process of forming the source and
drain regions S and D and the process of forming the dummy pattern
120. The first insulating layer 115 may be obtained by oxidizing
the first semiconductor layer 105. The oxidation of the first
semiconductor layer 105 may be performed by supplying oxygen
through an exposed side of the semiconductor layer 105. Further,
the second insulating layer 117 may be obtained by oxidizing
surfaces of the semiconductor substrate 100 and the second
semiconductor layer 110. For example, the first semiconductor layer
105 may be formed of a SiGe material, and the second semiconductor
layer 110 and the semiconductor substrate 100 may be formed of a
silicon (Si) material. In this case, since the SiGe material has an
oxidation rate greater than that of the Si material, the second
insulating layer 117 that is thinner than the first insulating
layer 115 may be formed on the second semiconductor layer 110 and
the semiconductor substrate 100, while the first semiconductor
layer 105 is entirely oxidized to form the first insulating layer
115. Further, as illustrated in FIG. 4B, the second insulating
layer 117 may be formed on an entire surface of the second
semiconductor layer 110.
[0035] The process of forming the source and drain regions S and D
and the process of forming the first and second insulating layers
may be interchangeably performed.
[0036] Referring to FIGS. 1C, 2C, 3C, and 4C, an oxide layer 125
may be formed on an exposed surface of the dummy pattern 120. Next,
a gate conductive layer is formed in the gate formation region GT_P
and the dummy gate formation region DGT_P. The gate conductive
layer may include a metal material, for example, one or more
materials selected from the group consisting of tungsten (W),
copper (Cu), titanium nitride (TiN), tantalum nitride (TaN),
tungsten nitride (WN), molybdenum nitride (MoN), niobium nitride
(NbN), titanium silicon nitride (TiSiN), titanium aluminum nitride
(TiAlN), titanium boron nitride (TiBN), zirconium silicon nitride
(ZrSiN), tungsten silicon nitride (WSiN), tungsten boron nitride
(WBN), zirconium aluminum nitride (ZrAlN), molybdenum silicon
nitride (MoSiN), molybdenum aluminum nitride (MoAlN), tantalum
silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN),
titanium (Ti), molybdenum (Mo), tantalum (Ta), titanium silicide
(TiSi), tantalum silicide (TaSi), titanium tungsten (TiW), titanium
oxynitride (TiON) titanium aluminum oxynitride (TiAlON), tungsten
oxynitride (WON) and tantalum oxynitride (TaON). The gate
conductive layer may be etched back to be left in a bottom of each
of the gate formation region GT_P and the dummy gate formation
region DGT_P, and thus a gate electrode 130 may be formed. At this
time, gate electrodes 130 may be insulated from each other by the
dummy pattern 120 and the oxide layer 125. A hard mask layer 135
may be formed on the gate electrode 130. The hard mask layer 135
may be formed to be buried in each of the gate formation region
GT_P and the dummy gate formation region DGT_P.
[0037] Referring to FIGS. 1D, 2D, 3D, and 4D a dummy pattern 120
located on the common source node formation region PS may be
selectively removed to form a source hole H. The process of forming
the source hole H may use a mask process. The process of forming
the source hole H may include an over etching process. A surface of
the source region S may be partially etched through the over
etching process. FIG. 4D illustrates a portion cut along the source
hole H.
[0038] Referring to FIGS. 1E 2E, 3E, and 4E, a dummy pattern 120 on
the active line F, that is, a dummy pattern on the drain region D
may be selectively removed, and then the second insulating layer
117 on the drain region D may be selectively removed
[0039] A conductive layer may be buried in the source hole H and in
a space from which the dummy pattern on the drain region D is
removed. The conductive layer may include a doped polysilicon
layer. The buried conductive layer may be recessed by a
predetermined thickness to form a common source node 140 on the
source region S and a heating electrode 145 on the drain region D.
Through the recess process, variable resistor regions may be formed
on the common source node 140 and the heating electrode 145.
[0040] The common source node 140 may be formed in a line shape
parallel to the gate electrode 130 since the common source node 140
is formed in the source hole H. Therefore, the common source node
140 may be in contact with the source region S on the active line
F, and the semiconductor substrate 100 in a space between the
active lines F.
[0041] An insulating layer 150 for a spacer may be deposited on the
semiconductor substrate in which the common source node 140 and the
heating electrode 145 are formed. A mask pattern (not shown) may be
formed to shield the insulating layer 150 for a spacer on the
common source node 140. Subsequently, the exposed insulating layer
150 for a spacer on the heating electrode 145 may be etched using a
general spacer etching process, for example, an anisotropical
etching process to form a spacer 155 on a sidewall of a variable
resistor region on the heating electrode 145.
[0042] The heating electrode 145 may be exposed by the spacer 155,
and the common source node 140 may be shielded by the insulating
layer 150 for a spacer. Next, the mask pattern may be removed
through a general process.
[0043] A resistance variable material layer 160 may be formed to be
buried in the variable resistor regions. As the resistance variable
material layer 160 may include a PCMO layer for a ReRAM, a
chalcogenide layer for a PCRAM, a magnetic layer for a MRAM a o
magnetization reversal device layer for a spin-transfer torque
magnetoresistive RAM (STTMRAM), or a polymer layer for a polymer
RAM (PoRAM). The resistance variable material layer 160 may be,
electrically coupled to the heating electrode 145 and electrically
isolated from the common source node 140.
[0044] Subsequently, although not shown, a bit line may be formed
on the resistance variable material layer 160. The bit line may be
formed in a direction substantially perpendicular to an extending
direction of the gate electrode 130.
[0045] According to the embodiment, since the common source node
140 is formed in a line shape between the gate electrodes 130, a
separate alignment process and a complex oxidation control process
are not necessary. Further, since the common source node 140 is
formed in such a manner that the common source node 140 of the
source region S is located on the source region S, and the common
source node 140 in the space between the active lines F is in
contact with the semiconductor substrate 100, current may be stably
provided to the semiconductor substrate 100 through the common
source node 140. Therefore, the lateral channel transistor in which
the common source node and the gate are formed in a self-aligned
manner may be completed.
[0046] Referring to FIG. 5, in a semiconductor device according to
the embodiment, a first insulating layer 115 and an active line F,
in which a source region (not shown) and a drain region D are
formed, are formed on a semiconductor substrate 100.
[0047] A gate electrode 130 may be arranged substantially to be
perpendicular to the active line on F between the source region and
the drain region D, and a common source node 140 may be formed
between gate electrodes 130 to be in contact with the source
region.
[0048] A heating electrode 145 may be formed on the drain region D,
and a resistance variable material layer 160 may be formed to be
electrically in contact with the heating electrode 145 and to be
insulated from the common source node 140.
[0049] The semiconductor device having a 3D lateral channel
according to the embodiment may include a line-shaped common source
node transversally or longitudinally crossing an active line. Since
the line-shaped common source node is formed without a complicated
alignment process and a process of partially oxidizing a first
semiconductor layer in a lower portion of the active line, a
process error may be reduced. Further, an aspect ratio of the
semiconductor device can be lowered using the lateral channel
structure, and electrical interaction characteristics may be
improved since a current discharge area is also increased according
to change to the line-shaped common source node from a common
source node of an existing pattern structure. With this line-shaped
common source node, current may be stably provided to a
semiconductor substrate, and a structural concern such as leaning
may also be alleviated.
[0050] Further, a gate electrode may be formed using a metal layer,
and thus conduction characteristics of the gate electrode may be
improved.
[0051] As illustrated in FIG. 6, a microprocessor 1000 to which the
semiconductor device according to the embodiment is applied may
control and adjust a series of processes, which receive data from
various external apparatuses, process the data and transmit
processing result to the external apparatuses. The microprocessor
1000 may include a storage unit 1010, an operation unit 1020, and a
control unit 1030. The microprocessor 1000 may be a variety of
processing apparatuses, such as a central processing unit (CPU), a
graphic processing unit (GPU), a digital signal processor (DSP), or
an application processor (AP).
[0052] The storage unit 1010 may be a processor register or a
register, and the storage unit may be a unit that may store data in
the microprocessor 1000 and include a data register, an address
register, and a floating point register. The storage unit 1010 may
include various registers other than the above-described registers.
The storage unit 1010 may function to temporarily store data to be
operated in the operation unit 1020, resulting data processed in
the operation unit 1020, and an address in which data to be
processed is stored.
[0053] The storage unit 1010 may include one of the semiconductor
devices according to embodiments. The storage unit 1010 including
the semiconductor device according to the above-described
embodiment may include a 3D semiconductor device including a
lateral channel structure in which a common source node is formed
in a line shape.
[0054] The operation unit 1020 may be a unit suitable for
performing an operation in the microprocessor 1000, and perform a
variety of four fundamental rules of an arithmetic operation or a
logic operation depending on a decryption result of a command in
the control unit 1030. The operation unit 1020 may include one or
more arithmetic and logic units (ALUs).
[0055] The control unit 1030 receives a signal from the storage
unit 1010, the operation unit 1020, or an external apparatus of the
microprocessor 1000, performs extraction or decryption of a
command, or input or output control, and executes a process in a
program form.
[0056] The microprocessor 1000 according to the embodiment may
further include a cache memory unit 1040 that may temporarily store
data input from or data to be output to an external apparatus other
than the storage unit 1010. At this time, the cache memory unit
1040 may exchange data with the storage unit 1010, the operation
unit 1020, and the control unit 1030 through a bus interface
1050.
[0057] As illustrated in FIG. 7, a processor 1100 according to the
embodiment may include various functions to implement performance
improvement and multifunction other than the functions of the
microprocessor that may control and adjust a series of processes,
which receive data from various external apparatuses, process the
data and transmit a processing result to the external apparatuses.
The processor 1100 may include a core unit 1110, a cache memory
unit 1120, and a bus interface 1130. The core unit 1110 in the
embodiment is a unit that may perform an arithmetic and logic
operation on data input from an external apparatus, and include a
storage unit 1111, an operation unit 1112, and a control unit 1113
The processor 1100 may be a variety of system on chips (SoCs) such
as a multi core processor (MCP) a GPO, and an AP.
[0058] The storage unit 1111 may be a processor register or a
register, and the storage unit 1111 may be a unit that may store
data in the processor 1100 and include a data register, an address
register, and a floating point register. The storage unit 1111 may
include various registers other than the above-described registers.
The storage unit 1111 may function to temporarily store data to be
operated in the operation unit 1112, resulting data processed in
the operation unit 1112, and an address in which data to be
processed is stored. The operation unit 1112 may be a unit that may
perform an operation in the processor 1100, and perform a variety
of four fundamental rules of arithmetic or a logic operation
depending on a decryption result of a command in the control unit
1113. The operation unit 1112 may include one or more arithmetic
and logic units (ALUs). The control unit 1113 receives a signal
from the storage unit 1111, the operation unit 1112, or an external
apparatus of the processor 1100, performs extraction or decryption
of a command, or input or output control, and executes a process in
a program form.
[0059] The cache memory unit 1120 may temporarily store data to
supplement a data processing rate of a low speed external apparatus
unlike the high speed core unit 1110. The cache memory unit 1120
includes a primary storage unit 1121, a secondary storage unit
1122, and a tertiary storage unit 1123. In general, the cache
memory unit 1120 may include the primary and secondary storage
units 1121 and 1122. When a high capacity storage unit is
necessary, the cache memory unit 1120 may include the tertiary
storage unit 1123. If necessary, the cache memory 1120 may include
more storage units. That is, the number of storage units included
in the cache memory unit 1120 may be changed according to design.
Here, processing rates of data storage and discrimination of the
primary, secondary, and tertiary storage units 1121, 1122, and 1123
may be the same as or different from each other. When the
processing rates of the storage units are different, the processing
rate of the primary storage unit is the largest. One or more of the
primary storage unit 1121, the secondary storage unit 1122, and the
tertiary storage unit 1123 in the cache memory unit 1120 may
include one of the semiconductor devices according to embodiments.
The cache memory unit 1120 including the semiconductor device
according to the above-described embodiment may include a 3D
semiconductor device including a lateral channel structure in which
a common source node is formed in a line shape. FIG. 7 has
illustrated that all the primary, secondary, tertiary storage units
1121, 1122, and 1123 are formed in the cache memory unit 1120.
However, all the primary, secondary, tertiary storage units 1121,
1122, and 1123 in the cache memory unit 1120 may be formed in the
outside of the core unit 1110, and may supplement a difference
between the processing rates of the core unit 1110 and an external
apparatus. Further, the primary storage unit 1121 of the cache
memory unit 1120 may be located in the core unit 1110, and the
secondary storage unit 1122 and the tertiary storage unit 1123 may
be formed in the outside of the core unit 1110 to enforce a
function to compensate a processing rate.
[0060] The bus interface 1130 is a unit that may couple the core
nit 1110 and the cache memory unit 1120 to efficiently transmit
data.
[0061] The processor 1100 according to the embodiment may include a
plurality of core units 1110, and the core units 1110 may share the
cache memory unit 1120. The core units 1110 and the cache memory
unit 1120 may be coupled through the bus interface 1130. The core
units 1110 may have the same configuration as the configuration of
the above-described core unit 1110. When the core units 1110 are
provided, the primary storage unit 1121 of the cache memory unit
1120 may be formed in each of the core units 1110 corresponding to
the number of core units 1110, and the secondary storage unit 1122
and the tertiary storage unit 1123 may be formed in one body in the
outsides of the core units 1110 to be shared through the bus
interface 1130. Here, the processing rate of the primary storage
unit 1121 may be greater than those of the secondary and tertiary
storage units 1122 and 1123.
[0062] The processor 1100 according to the embodiment may further
include an embedded memory unit 1140 that may store data, a
communication module unit 1150 that may transmit and receive data
to and from an external apparatus in a wired manner or a wireless
manner, a memory control unit 1160 that may drive an external
storage device, and a media processing unit 1170 that may process
data processed in the processor 1100 or data input from an external
apparatus and may output a processing result to an external
interface device. The processor may further include a plurality of
modules. At this time, the modules may transmit data to and receive
data from the core unit 1110 and the cache memory unit 1120, and
between the modules through the bus interface 1130.
[0063] The embedded memory unit 1140 may include a volatile memory
or a nonvolatile memory. The volatile memory may include a dynamic
random access memory (DRAM), a mobile DRAM, a static random access
memory (SRAM), and the like, and the nonvolatile memory may include
a read only memory (ROM), a NOR flash memory, a NAND flash memory,
a phase-change random access memory (PRAM), a resistive RAM (RRAM)
a spin transfer torque RAM (STTRAM), a magnetic RAM (MRAM), and the
like. The semiconductor device according to the embodiment may be
applied to the embedded memory unit 1140.
[0064] The communication module unit 1150 may include all modules
such as a module that may be coupled to a wired network and a
module that may be coupled to a wireless network. The wired network
module may include a local area network (LAN), a universal serial
bus (USB), Ethernet, a power One communication (PLC), and the like,
and the wireless network module may include Infrared Data
Association (IrDA), Code Division Multiple Access (CDMA), Time
Division Multiple Access (TDMA), Frequency Division Multiple Access
(FDMA), a wireless LAN, Zigbee, a Ubiquitous Sensor Network (USN),
Bluetooth, Radio Frequency Identification (RFID) Long Term
Evolution (LTE), Near Field Communication (NFC), Wireless Broadband
Internet (Wibro), High Speed Downlink Packet Access (HSDPA),
Wideband COMA (WCDMA) Ultra WideBand (UWB), and the like.
[0065] The memory control unit 1160 may manage data transmitted
between the processor 1100 and an external apparatus that may
operate according to a different communication standard from the
processor 1100. The memory control unit 1160 may include a variety
of memory controllers, or a controller that may control Integrated
Device Electronics (IDE), Serial Advanced Technology Attachment
(SATA), a Small Computer System Interface (SCSI), a Redundant Array
of Independent Disks (RAID), a solid state disk (SSD), External
SATA (eSATA), Personal Computer Memory Card International
Association (PCMCIA), a USB, a secure digital (SD) card, a mini
secure digital (mSD) card, a micro SD card, a secure digital high
capacity (SDRC) card, a memory stick card, a smart media card (SM),
a multi media card (MMC), an embedded MMC (eMMC), a compact flash
(CF) card, and the like.
[0066] The media processing unit 1170 may be a unit that may
process data processed in the processor 1100 or data input from an
external input device and may output a processing result to an
external interface device so that the processing result may be
transferred in video, a voice, and other types. The media
processing unit 1170 may include a GPU, a DSP, a HD audio, a high
definition multimedia interface (HDMI) controller, and the
like.
[0067] As illustrated in FIG. 8, a system 1200 to which the
semiconductor device according to an embodiment of the inventive
concept is applied is a data processing apparatus. The system 1200
may perform input, processing, output, communication, storage, and
the like to perform a series of operations on data, and include a
processor 1210, a main storage device 1220, an auxiliary storage
device 1230, and an interface device 1240. The system according to
the embodiment may be a variety of electronic systems that may
operate using a processor, such as a computer, a server, a personal
digital assistant (PDA), a portable computer, a web tablet, a
wireless phone, a mobile phone, a smart phone, a digital music
player, a portable multimedia player (PMP), a camera, a global
positioning system (GPS), a video camera, a voice recorder,
Telematics, an audio visual (AV) system, or a smart television.
[0068] The processor 1210 is a core configuration of the system
that may control interpretation of an input command and processing
such as an operation, comparison, and the like of data stored in
the system, and may be formed of a MPU, a CPU, a single/multi core
processor, a GPU, an AP, a DSP, or the like.
[0069] The main storage unit 1220 is a storage place that may move
and execute a program or data from the auxiliary storage device
1230 and may execute the program or the data, when the program is
executed. The main storage device 1220 retains the stored content
in power off, and may include the semiconductor device according to
the above-described embodiment. The main storage device 1220 may
include a semiconductor device having a lateral channel structure
in which a common source node is formed in a line shape.
[0070] The main storage device 1220 according to the embodiment may
further include an SRAM or a DRAM of a volatile memory type in
which all contents are erased in power off. Alternatively, the main
storage device 1220 may not include the semiconductor device
according to the embodiment but may include an SRAM or a DRAM of a
volatile memory type in which all contents are erased in power
off.
[0071] The auxiliary storage device 1230 is a storage device that
may store a program code or a data. The auxiliary storage device
1230 may have a lower data processing rate than that of the main
storage device 1220, but may store a large amount of data and
include the semiconductor device according to the above-described
embodiment. The auxiliary storage unit 1230 may also include a
semiconductor device having a lateral channel structure in which a
common source is formed in a line shape.
[0072] An area of the auxiliary storage device 1230 according to
the embodiment may be reduced, to reduce a size of the system 1200
and increase portability of the system 1200. Further, the auxiliary
storage device 1230 may further include a data storage system, such
as a magnetic tape and a magnetic disc using a magnetism, a laser
disc using light, a magneto-optical disc using a magnetism and
light, an SSD, a USB memory, a SD card, a mSD card, a micro SD
card, a SDHC card, a memory stick card, a smart media card, a MMC
card, an eMMC, or a CF card. Unlike this, the auxiliary storage
device 1230 may not include the semiconductor device according to
the above-described embodiment but may include a data storage
system, such as a magnetic tape and a magnetic disc using a
magnetism, a laser disc using, light, a magneto-optical disc using
a magnetism and light, an SSD, a USB memory, a SD card, a mSD card,
a micro SD card, a SDHC card, a memory stick card, a smart media
card, a MMC card, an eMMC, or a CF card.
[0073] The interface device 1240 may exchange a command and data of
an external apparatus with the system of the embodiment, and may be
a keypad, a keyboard, a mouse, a speaker, a mike, a display, a
variety of Human Interface Devices (HIDs), or a communication
device. The communication device may include all modules such as a
module that may be coupled to a wired network or a module that may
be coupled to a wireless network. The wired network module may
include a LAN, a USB, Ethernet, a PLC, and the like, and the
wireless network module may include IrDA, CDMA, TDMA, FDMA, a
wireless LAN, Zigbee, a USN, Bluetooth, RFI, NFC, fibro, HSDPA,
WCDMA, UWB, and the like.
[0074] The above embodiment of the present invention is
illustrative and not limitative. Various alternatives and
equivalents are possible. The invention is not limited by the
embodiment described herein. Nor is the invention limited to any
specific type of semiconductor device. Other additions,
subtractions, or modifications are obvious in view of the present
disclosure and are intended to fall within the scope of the
appended claims.
* * * * *