U.S. patent application number 14/812286 was filed with the patent office on 2015-11-19 for display.
The applicant listed for this patent is INNOLUX CORPORATION. Invention is credited to Yen-Wei CHEN, Li-Wei SUNG, Chung-Lin TSAI.
Application Number | 20150332629 14/812286 |
Document ID | / |
Family ID | 44911360 |
Filed Date | 2015-11-19 |
United States Patent
Application |
20150332629 |
Kind Code |
A1 |
SUNG; Li-Wei ; et
al. |
November 19, 2015 |
DISPLAY
Abstract
A display is disclosed. The display comprises a panel, a data
driver and a scan driver. The panel comprises pixels, data lines
and scan lines. The data lines transmit data signals to the pixels,
and the scan lines transmit scan signals to the pixels. The data
driver provides the data signals, and the scan driver provides the
scan signals. The scan driver comprises a shift register circuit.
The shift register circuit comprises an i+1.sup.th stage carry
shift register, an i.sup.th stage carry shift register and a
j.sup.th stage buffer shift register. The i.sup.th stage carry
shift register generates an i+1.sup.th start signal to start the
i+1.sup.th stage carry shift register, so that the i+1.sup.th stage
carry shift register generates an i+2.sup.th start signal. The
i+1.sup.th start signal starts the j.sup.th stage buffer shift
register to generate a j.sup.th output signal.
Inventors: |
SUNG; Li-Wei; (Chu-Nan,
TW) ; CHEN; Yen-Wei; (Chu-Nan, TW) ; TSAI;
Chung-Lin; (Chu-Nan, TW) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
INNOLUX CORPORATION |
Chu-Nan |
|
TW |
|
|
Family ID: |
44911360 |
Appl. No.: |
14/812286 |
Filed: |
July 29, 2015 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
13102334 |
May 6, 2011 |
9123282 |
|
|
14812286 |
|
|
|
|
Current U.S.
Class: |
345/204 |
Current CPC
Class: |
G09G 3/20 20130101; G09G
2320/0219 20130101; G09G 2310/0224 20130101; G11C 19/287 20130101;
G09G 3/2011 20130101; G09G 3/3266 20130101; G09G 2310/0286
20130101 |
International
Class: |
G09G 3/32 20060101
G09G003/32; G09G 3/20 20060101 G09G003/20 |
Foreign Application Data
Date |
Code |
Application Number |
May 11, 2010 |
TW |
099114964 |
Claims
1. A display, comprising: a panel, comprising: a plurality of
pixels; a plurality of data lines transmitting a plurality of data
signals to the pixels; a plurality of scan lines transmitting a
plurality of scan signals to the pixels; a data driver providing
the data signals; and a scan driver providing the scan signals,
wherein the scan driver comprises: a shift register circuit,
comprising: an i-th stage shift register comprising: a first
outputting transistor having a first control terminal and a first
outputting terminal; and a second outputting transistor having a
second control terminal and a second outputting terminal, wherein
both the first control terminal and the second control terminal
receive a start signal, and the first outputting terminal and the
second outputting terminal respectively generate another start
signal and an outputting signal.
2. The display according to claim 1, wherein the i-th stage shift
register further comprises: a first receiving transistor having a
first terminal coupled to the first outputting transistor via the
first outputting terminal, a second terminal receiving another
outputting signal, and a third terminal receiving a constant
voltage.
3. The display according to claim 1, wherein the i-th stage shift
register further comprises: a second receiving transistor having a
first terminal coupled to the second outputting transistor via the
second outputting terminal, a second terminal receiving another
outputting signal, and a third terminal receiving a constant
voltage.
4. The display according to claim 2, wherein the i-th stage shift
register further comprises: a third receiving transistor coupled to
the first control terminal.
5. The display according to claim 4, wherein a control terminal of
the third receiving transistor receives the another outputting
signal; or the control terminal of the third receiving transistor
receives still another outputting signal.
6. The display according to claim 2, wherein the i-th stage shift
register further comprises: a fourth receiving transistor coupled
to the second control terminal.
7. The display according to claim 6, wherein a control terminal of
the fourth receiving transistor receives the another outputting
signal; or the control terminal of the fourth receiving transistor
receives still another outputting signal.
8. The display according to claim 1, wherein the i-th stage shift
register further comprises: a fifth receiving transistor coupled to
the first control terminal, wherein a control terminal of the fifth
receiving transistor receives a clock signal.
9. The display according to claim 8, wherein the i-th stage shift
register further comprises: a sixth receiving transistor coupled to
the second control terminal, wherein a control terminal of the
sixth receiving transistor receives the clock signal.
10. The display according to claim 1, wherein the i-th stage shift
register further comprises: a first driving transistor coupled to
the first control terminal, for driving the first outputting
transistor according to the start signal; and a second driving
transistor coupled to the second control terminal, for driving the
second outputting transistor according to the start signal.
11. A display, comprising: a panel, comprising: a plurality of
pixels; a plurality of data lines transmitting a plurality of data
signals to the pixels; a plurality of scan lines transmitting a
plurality of scan signals to the pixels; a data driver providing
the data signals; and a scan driver providing the scan signals,
wherein the scan driver comprises: a shift register circuit,
comprising: an i-th stage shift register comprising: a first
outputting transistor having a first control terminal and a first
outputting terminal, wherein the first control terminal receives a
previous start signal and the first outputting terminal generates a
later start signal; and a second outputting transistor having a
second control terminal and a second outputting terminal, wherein
the second control terminal receives the previous start signal and
the second outputting terminal generates an outputting signal.
12. The display according to claim 11, wherein the i-th stage shift
register further comprises: a first receiving transistor having a
first terminal coupled to the first outputting transistor via the
first outputting terminal, a second terminal receiving another
outputting signal, and a third terminal receiving a constant
voltage.
13. The display according to claim 11, wherein the i-th stage shift
register further comprises: a second receiving transistor having a
first terminal coupled to the second outputting transistor via the
second outputting terminal, a second terminal receiving another
outputting signal, and a third terminal receiving a constant
voltage.
14. The display according to claim 12, wherein the i-th stage shift
register further comprises: a third receiving transistor coupled to
the first control terminal.
15. The display according to claim 14, wherein a control terminal
of the third receiving transistor receives the another outputting
signal; or the control terminal of the third receiving transistor
receives still another outputting signal.
16. The display according to claim 12, wherein the i-th stage shift
register further comprises: a fourth receiving transistor coupled
to the second control terminal.
17. The display according to claim 16, wherein a control terminal
of the fourth receiving transistor receives the another outputting
signal; or the control terminal of the fourth receiving transistor
receives still another outputting signal.
18. The display according to claim 11, wherein the i-th stage shift
register further comprises: a fifth receiving transistor coupled to
the first control terminal, wherein a control terminal of the fifth
receiving transistor receives a clock signal.
19. The display according to claim 18, wherein the i-th stage shift
register further comprises: a sixth receiving transistor coupled to
the second control terminal, wherein a control terminal of the
sixth receiving transistor receives the clock signal.
20. The display according to claim 11, wherein the i-th stage shift
register further comprises: a first driving transistor coupled to
the first control terminal, for driving the first outputting
transistor according to the previous start signal; and a second
driving transistor coupled to the second control terminal, for
driving the second outputting transistor according to the previous
start signal.
Description
[0001] This application is a continuation application of U.S.
application Ser. No. 13/102,334, filed on May 6, 2011, which claims
the benefit of Taiwan application Serial No. 99114964, filed May
11, 2010, the subject matter of which is incorporated herein by
reference.
BACKGROUND
[0002] 1. Technical Field
[0003] The disclosure relates in general to a display, and more
particularly to a display capable of independently generating start
signals and output signals respectively.
[0004] 2. Description of the Related Art
[0005] Referring to FIG. 1 and FIG. 2. FIG. 1 shows a conventional
shift register circuit. FIG. 2 shows a signal timing diagram of
FIG. 1. The conventional shift register circuit 122 comprises a
plurality of stages of shift registers. For convenience of
elaboration, the shift registers are exemplified by a first stage
shift register SR1 to a fourth stage shift register SR4. The first
stage shift register SR1 to the fourth stage shift register SR4
generate a first stage output signal O1 to a fourth stage output
signal O4. The first stage output signal O1 generated by the first
stage shift register SR1 is inputted to start the second stage
shift register SR2 to generate a second stage output signal O2. The
second stage output signal O2 generated by the second stage shift
register SR2 is inputted to start the third stage shift register
SR3 to generate a third stage output signal O3. The third stage
output signal O3 generated by the third stage shift register SR3 is
inputted to start the fourth stage shift register SR4 to generate a
fourth stage output signal O4. The operation of the output signals
of other stages can be obtained in the same manner.
[0006] Referring to FIG. 3, a circuit diagram of a first
conventional shift register is shown. The first stage shift
register SR1 comprises transistors T1.about.T4. The transistor T1
outputs a first stage output signal O1 according to a clock signal
CK1. The transistor T2 is coupled to the transistor T1 and
controlled by the second stage output signal O2 outputted from the
second stage shift register SR. The transistor T3 is controlled by
the second stage output signal O2 outputted from the second stage
buffer shift register SR2. The transistor T4 is coupled to the
transistor T3 for driving the transistor T1 according to the first
stage start signal STV. The transistor T2 is coupled to the
transistor T1 and a coupling capacitor Cb. The circuit design of
the second stage shift register SR2 is similar to that of the first
stage carry shift register SR1, and the similarities are not
repeated here.
[0007] Referring to FIG. 4, a circuit diagram of a second
conventional shift register is shown. FIG. 4 is different from of
FIG. 3 in that the shift registers SR1' and SR2' of FIG. 4 further
comprise a transistor T5. The transistor T5 is controlled by the
potential of a node B to selectively output a start signal C2 to
start the shift register SR2 according to the clock signal CK1.
[0008] In the display region (also referred as active matrix array
region) of the display panel, the scan lines and the data lines are
interlaced, when the voltage on the data lines varies, the voltage
on the scan lines varies as well. Thus, the output signal of the
conventional shift register circuit will be interfered with by the
noises. When the output signal interfered with by the noises is
inputted to the next stage shift register, the noises will be
amplified and cause abnormal operation to the shift register
circuit.
SUMMARY
[0009] The disclosure is directed to a display, which adopts a
carry shift register to independently output a start signal and
adopts a buffer shift register to independently output an output
signal. Since the buffer shift register and the carry shift
register are divided into two independent loops, the output signal
generated by the buffer shift register will not be used as a start
signal in the next stage. When the buffer shift register is
interfered with by noises, the noises will not be inputted to the
next stage. Thus, the abnormal operation of the shift register
circuit due to the amplification of the noises will not occur.
[0010] According to a first aspect of the present disclosure, a
display is provided. The display comprises a panel, a data driver
and a scan driver. The panel comprises pixels, data lines and scan
lines. The data lines transmit data signals to the pixels, and the
scan lines transmit scan signals to the pixels. The data driver
provides the data signals, and the scan driver provides the scan
signals. The scan driver comprises a shift register circuit. The
shift register circuit comprises a plurality of stages of carry
shift registers and a plurality of stages of buffer shift
registers. The carry shift registers generates a plurality of start
signals comprising an i+1.sup.th start signal and an i+2.sup.th
start signal. The carry shift registers comprise an i+1.sup.th
stage carry shift register and an i.sup.th stage carry shift
register. The i.sup.th stage carry shift register generates an
i+1.sup.th start signal to start the i+1.sup.th stage carry shift
register, so that the i+1.sup.th stage carry shift register
generates an i+2.sup.th start signal. The buffer shift registers
generates a plurality of output signals comprising a j.sup.th
output signal and respectively corresponding to a plurality of scan
signals. These stages of buffer shift registers comprise a j.sup.th
stage buffer shift register. The i+1.sup.th start signal starts the
j.sup.th stage buffer shift register to generate a j.sup.th output
signal
[0011] The above and other aspects of the disclosure will become
better understood with regard to the following detailed description
of the non-limiting embodiment(s). The following description is
made with reference to the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0012] FIG. 1 shows a conventional shift register circuit;
[0013] FIG. 2 shows a signal timing diagram of FIG. 1;
[0014] FIG. 3 shows a circuit diagram of a first conventional shift
register;
[0015] FIG. 4 shows a circuit diagram of a second conventional
shift register;
[0016] FIG. 5 shows a display;
[0017] FIG. 6 shows a panel;
[0018] FIG. 7 shows a partial view of a shift register circuit
according to a first embodiment of the disclosure;
[0019] FIG. 8 shows a first circuit diagram of carry shift register
and buffer shift register;
[0020] FIG. 9 shows a timing diagram of the signals of FIG. 8;
[0021] FIG. 10 shows a second circuit diagram of carry shift
register and buffer shift register;
[0022] FIG. 11 shows a timing diagram of the signals of FIG.
10;
[0023] FIG. 12 shows a partial view of a shift register circuit
according to a second embodiment of the disclosure; and
[0024] FIG. 13 shows a partial view of a shift register circuit
according to a third embodiment of the disclosure.
DETAILED DESCRIPTION
[0025] Referring to both FIG. 5 and FIG. 6. FIG. 5 shows a display.
FIG. 6 shows a panel. The display 50 comprises a panel 510, a scan
driver 520 and a data driver 530. The panel 510 comprises pixels
512, scan lines 514 and data lines 516. The data driver 530
provides the data signals D1.about.Dm, and the scan driver 520
provides the scan signals S1.about.Sn. The data lines 516 transmit
the data signals D1.about.Dm to the pixels 512, and the scan lines
514 transmit the scan signals S1.about.Sn to the pixels 512. The
scan driver 520 can be realized by such as an amorphous silicon
gate (ASG) and can be formed on the panel 510.
[0026] The scan driver 520 comprises a shift register circuit which
provides output signals respectively corresponding to the scan
signals S1.about.Sn. The shift register circuit adopts a carry
shift register to independently output a start signal and adopts a
buffer shift register to independently output an output signal.
Since the buffer shift register and the carry shift register are
divided into two independent loops, the output signal generated by
the buffer shift register will not be used as a start signal in the
next stage. Thus, when the buffer shift register is interfered with
by noises, the noises will not be inputted to the next stage. Thus,
the abnormal operation of the shift register circuit due to the
amplification of the noises will not occur. The composition of the
shift register circuit is elaborated below with a plurality of
embodiments.
First Embodiment
[0027] Referring to FIG. 7, a partial view of a shift register
circuit according to a first embodiment of the disclosure is shown.
In the first embodiment, one stage of carry shift register goes
with one stage of buffer shift register. The scan driver 520
further comprises a shift register circuit 522. The shift register
circuit 522 outputs a first stage output signal O1 to a fourth
stage output signal O4 respectively corresponding to the scan
signals S1.about.S4. The shift register circuit 522 comprises a
first stage carry shift register SR1a to a fourth stage carry shift
register SR4a and a first stage buffer shift register SR1b to a
fourth stage buffer shift register SR4b. It is noted that in the
shift register circuit 522, the number of the carry shift registers
is the same with that of the buffer shift registers. The first
stage carry shift register SR1a to the fourth stage carry shift
register SR4a respectively generate a second stage start signal C2
to a fifth stage start signal C5. The first stage buffer shift
register SR1b to the fourth stage buffer shift register SR4b
respectively generate the first stage output signal O1 to the
fourth stage output signal O4. The first stage output signal O1 to
the fourth stage output signal O4 and the first stage start signal
C1 to the fourth stage start signal C4 are respectively generated
synchronically.
[0028] The first stage start signal STV starts the first stage
carry shift register SR1a to generate a second stage start signal
C2', and further starts the first stage buffer shift register SR1b
to output a first stage output signal O1. The second stage start
signal C2 starts the second stage carry shift register SR2a to
generate a third stage start signal C3, and further starts the
second stage buffer shift register SR2b to output a second stage
output signal O2. The third stage start signal C3 starts the third
stage carry shift register SR3a to generate a fourth stage start
signal C4, and further starts the third stage buffer shift register
SR3b to output a third stage output signal O3. The fourth stage
start signal C4 starts the fourth stage carry shift register SR4a
to generate a fifth stage start signal C5, and further starts the
fourth stage buffer shift register SR4b to output a fourth stage
output signal O4. By the same token, in subsequent stages, the
principles of the operations of the carry shift registers and the
buffer shift registers are similar to that illustrated in the above
disclosure, and the similarities are not repeated here.
[0029] In the display region (also referred as active matrix array
region) of the display panel, the scan lines and the data lines are
interlaced, and when the voltage on the data lines varies, the
voltage on the scan lines will varies as well. Thus, the output
signal of the conventional shift register circuit will be
interfered with by the noises. When the output signal interfered
with by the noises is inputted to the next stage shift register,
the noises will be amplified and cause abnormal operation to the
shift register circuit.
[0030] To the contrary, in the first embodiment, since the buffer
shift register and carry shift register are divided into two
independent loops, the output signal generated by the buffer shift
register will not be used as a start signal in the next stage.
Thus, when the buffer shift register is interfered with by noises,
the noises will not be inputted to the next stage. Thus, the
abnormal operation of the shift register circuit due to the
amplification of the noises will not occur.
[0031] Referring to both FIG. 8 and FIG. 9. FIG. 8 shows a first
circuit diagram of carry shift register and buffer shift register.
FIG. 9 shows a timing diagram of the signals of FIG. 8. The first
stage carry shift register SR1a comprises transistors
T1a.about.T4a. The buffer shift register SR1b comprises transistors
T1.about.T4. The area ratio of the transistor T1 to that of the
transistor T1a is about 5.about.20. The transistor T1 outputs a
first stage output signal O1 at node A according to clock signal
CK1. The transistor T2 is coupled to the transistor T1 and
controlled by the second stage output signal O2 outputted from the
second stage buffer shift register SR2b. The transistor T3 is
controlled by the second stage output signal O2 outputted from the
second stage buffer shift register SR2b. The transistor T4 is
coupled to the transistor T3 via the node B for driving the
transistor T1 according to the first stage start signal STV. The
transistor T2 is coupled to the transistor T1 and transistor T2 via
a coupling capacitor Cb. The circuit design of the second stage
carry shift register SR2a is identical to that of the first stage
carry shift register SR1a, and the similarities are not repeated
here.
[0032] The circuit design of the first stage buffer shift register
SR1b is substantially identical to that of the first stage carry
shift register SR1a. The transistor T1a outputs a second stage
start signal C2 at the node A' according to the clock signal CK1.
The transistor T2a is coupled to the transistor T1a via the node A'
and controlled by the second stage output signal O2 outputted from
the second stage buffer shift register SR2b. The transistor T3a is
controlled by the second stage output signal O2 outputted from the
second stage buffer shift register SR2. The transistor T4a is
coupled to the transistor T3a via the node B' for driving the
transistor T1a according to the first stage start signal STV. The
transistor T2a is coupled to the transistor T1a via a coupling
capacitor Cb'. The circuit design of the second stage buffer shift
register SR2b is identical to that of the first stage buffer shift
register SR1b, and the similarities are not repeated here.
[0033] Referring to FIG. 10 and FIG. 11. FIG. 10 shows a second
circuit diagram of carry shift register and buffer shift register.
FIG. 11 shows a timing diagram of the signals of FIG. 10. The
circuits of carry shift register and the buffer shift register can
be realized by that illustrated in FIG. 8 or that illustrated in
FIG. 10. The first stage carry shift register SR1a' of FIG. 10 is
different from the first stage carry shift register SR1a of FIG. 8
in that: the first stage carry shift register SR1a' further
comprises a transistor T5a, a regulation capacitor C1, a regulation
capacitor C2 and a regulation capacitor C3, and that the transistor
T3a is controlled by the third output signal O3. The transistor T5a
is coupled to the transistors T1a, T3a and T4a via the node B', and
is controlled by clock signal CK3. One terminal of regulation
capacitor C1 is coupled to the control terminal of the transistor
T1a, and the other terminal of the regulation capacitor C1 receives
the clock signal CK2. One terminal of the regulation capacitor C2
is coupled to the control terminal of the transistor T1a, and the
other terminal of the regulation capacitor C2 receives the clock
signal CK3. One terminal of the regulation capacitor C3 is coupled
to the control terminal of the transistor T1a, and the other
terminal of the regulation capacitor C3 receives the clock signal
CK4. The circuit design of the second stage carry shift register
SR2a' is identical to that of the first stage carry shift register
SR1a' and the similarities are not repeated here.
[0034] The first stage buffer shift register SR1b' of FIG. 10 is
different from the first stage carry shift register SR1b of FIG. 8
in that: the first stage carry shift register SR1b' further
comprises a transistor T5, and the transistor T3 is controlled by
the third stage output signal O3. The transistor T5 is coupled to
the transistors T1, T3 and T4 via the node B, and is controlled by
the clock signal CK3. The circuit design of the second stage buffer
shift register SR2b' is identical to that of the first stage buffer
shift register SR1b', and the similarities are not repeated
here.
[0035] Moreover, the design of the regulation capacitors
C1.about.C3 suppresses the noises generated by the clock signal
CK1. When the level of the clock signal CK1 rises, the potential of
the node B will be affected due to the parasitic capacitance
between the gate and source of the transistor T1a. Thus, the levels
of the clock signals CK2.about.CK4 are stepped down to offset the
rise in the level of the clock signal CK1 to assure the normal
operation of the shift register circuit.
Second Embodiment
[0036] Referring to FIG. 12, a partial view of a shift register
circuit according to a second embodiment of the disclosure is
shown. The second embodiment is different from the first embodiment
in that: the number of the carry shift registers is different from
that of the buffer shift registers. In the second embodiment, one
stage of carry shift register goes with a plurality of stages of
buffer shift registers. For convenience of elaboration, the second
embodiment is exemplified by a shift register circuit in which one
stage of carry shift register goes with two stages of buffer shift
registers.
[0037] The scan driver 520 further comprises a shift register
circuit 524. The shift register circuit 524 outputs a first stage
output signal O1 to a fifth stage output signal O5 respectively
corresponding to the scan signals S1.about.S5. The shift register
circuit 524 comprises a first stage carry shift register SR1a to a
third stage carry shift register SR3a and a first stage buffer
shift register SR1b to a fifth stage buffer shift register SR5b. It
is noted that in the shift register circuit 522, the number of the
carry shift registers is smaller than that of the buffer shift
registers. The first stage carry shift register SR1a to the third
stage carry shift register SR3a respectively generate the second
stage start signal C2 to the third stage start signal C4, and the
first stage buffer shift register SR1b to the fifth stage buffer
shift register SR5b respectively generate the first stage output
signal O1 to the fifth stage output signal O5.
[0038] The first stage start signal STV starts the first stage
carry shift register SR1a to generate a second stage start signal
C2 at the node A'. The first stage start signal STV starts the
first stage buffer shift register SR1b to output a first stage
output signal O1 at the node A, and further starts the second stage
buffer shift register SR2b to output a second stage output signal
O2. The second stage start signal C2 starts the second stage carry
shift register SR2a to generate a third stage start signal C3. The
second stage start signal C2 starts the third stage buffer shift
register SR3b to output a third stage output signal O3, and starts
the fourth stage buffer shift register SR4b to output a fourth
stage output signal O4. By the same token, in subsequent stages,
the principles of the operations of the carry shift registers and
the buffer shift registers are similar to that illustrated in the
above disclosure, and the similarities are not repeated here.
Third Embodiment
[0039] Referring to FIG. 13, a partial view of a shift register
circuit according to a third embodiment of the disclosure is shown.
The third embodiment is different from the first embodiment in
that: the number of the carry shift registers is different from
that of the buffer shift registers. In the third embodiment, one
stage of buffer shift register goes with a plurality of stages of
carry shift registers. For convenience of elaboration, the third
embodiment is exemplified by a shift register circuit in which one
stage of buffer shift register goes with two stages of carry shift
registers.
[0040] The scan driver 520 further comprises a shift register
circuit 526. The shift register circuit 526 outputs the first stage
output signal O1 and the second stage output signal O2 respectively
corresponding to the scan signals S1.about.S2. The shift register
circuit 526 comprises a first stage carry shift register SR1a to a
fifth stage carry shift register SR5a and a first stage buffer
shift register SR1b and a second stage buffer shift register SR2b.
It is noted that in the shift register circuit 526, the number of
the carry shift registers is different from that of the buffer
shift register. The first stage carry shift register SR1a to the
fifth stage carry shift register SR5a respectively generate the
second stage start signal C2 to the sixth stage start signal C6.
The first stage buffer shift register SR1b and the second stage
buffer shift register SR2b respectively generate the first stage
output signal O1 and the second stage output signal O2.
[0041] The first stage start signal STV starts the first stage
carry shift register SR1a to generate a second stage start signal
C2, and the second stage start signal C2 starts the second stage
carry shift register SR2a to generate a third stage start signal
C3. The second stage start signal C2 and the third stage start
signal C3 start the first stage buffer shift register SR1b to
output a first stage output signal O1.
[0042] The third stage start signal C3 starts the third stage carry
shift register SR3a to generate a fourth stage start signal C4,
which starts the fourth stage carry shift register SR4a to generate
a fifth stage start signal C5. The fourth stage start signal C4 and
the fifth stage start signal C5 start the second stage buffer shift
register SR2b to output a second stage output signal O2. By the
same token, in subsequent stages, the principles of the operations
of the carry shift registers and the buffer shift registers are
similar to that illustrated in the above disclosure, and the
similarities are not repeated here.
[0043] The shift register circuit and the display disclosed in the
above embodiments of the disclosure have many advantages
exemplified below:
[0044] Firstly, the noises generated due to the clock signals are
suppressed to assure the normal operation of the shift register
circuit.
[0045] Secondly, the noises generated by the display region of the
panel are suppressed to assure the normal operation of the shift
register circuit.
[0046] While the disclosure has been described by way of example
and in terms of the exemplary embodiment (s), it is to be
understood that the disclosure is not limited thereto. On the
contrary, it is intended to cover various modifications and similar
arrangements and procedures, and the scope of the appended claims
therefore should be accorded the broadest interpretation so as to
encompass all such modifications and similar arrangements and
procedures.
* * * * *