U.S. patent application number 14/273953 was filed with the patent office on 2015-11-12 for system and method for adapting to network protocol updates.
This patent application is currently assigned to GOOGLE INC.. The applicant listed for this patent is Google Inc.. Invention is credited to Yuhong Mao.
Application Number | 20150326696 14/273953 |
Document ID | / |
Family ID | 53269723 |
Filed Date | 2015-11-12 |
United States Patent
Application |
20150326696 |
Kind Code |
A1 |
Mao; Yuhong |
November 12, 2015 |
SYSTEM AND METHOD FOR ADAPTING TO NETWORK PROTOCOL UPDATES
Abstract
A system and method are provided for updating network protocols.
A new ASIC is designed to adapt to future network protocols, the
ASIC including at least one packet editing program. The ASIC is
configured to classify a received packet to determine new protocols
to which the packet is to be updated, delete selected existing
headers of the packet, insert new headers in the packet based on
the classification, and modify selected headers based on the
classification.
Inventors: |
Mao; Yuhong; (Fremont,
CA) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Google Inc. |
Mountain View |
CA |
US |
|
|
Assignee: |
GOOGLE INC.
Mountain View
CA
|
Family ID: |
53269723 |
Appl. No.: |
14/273953 |
Filed: |
May 9, 2014 |
Current U.S.
Class: |
370/392 |
Current CPC
Class: |
H04L 69/08 20130101;
H04L 45/50 20130101; H04L 69/22 20130101 |
International
Class: |
H04L 29/06 20060101
H04L029/06; H04L 12/723 20060101 H04L012/723 |
Claims
1. A method, comprising: receiving a packet; classifying, with one
or more processors, the packet, the classification including
determining a new protocol to which the packet is to be updated;
deleting, with one or more processors, an existing header of the
packet; inserting, with one or more processors, a new header in the
packet based on the classification; and modifying, with one or more
processors, the new header based on the classification.
2. The method of claim 1, wherein determining the new protocol to
which the packet is to be updated comprises identifying pointers to
a packet editing program.
3. The method of claim 1, wherein deleting the existing packet
header comprises deleting selected portions of the existing header
that are not used by the new protocol.
4. The method of claim 3, wherein inserting the new packet header
comprises inserting portions of the new packet header based on the
new protocol and portions remaining from a previous packet
header.
5. The method of claim 1, wherein modifying the new packet header
comprises executing at least one of an overwrite or a
read-modify-write operation.
6. The method of claim 1, further comprising transmitting the
packet including the new header through a network based on the new
header.
7. A system, comprising: at least one memory; and at least one
processor in communication with the at least one memory, the at
least processor to: receive a packet; classify the packet, the
classification including determining a new protocol to which the
packet is to be updated; delete an existing header of the packet;
insert a new header in the packet based on the classification; and
modify the new header based on the classification.
8. The system of claim 7, wherein the at least one memory includes
at least one packet editing program, each packet editing program
including pointers to its editing instructions and pointers to sets
of static data, shared data, and dynamic data.
9. The system of claim 8, wherein the at least one memory further
includes meta data and register data accessible by the editing
instructions.
10. The system of claim 7, wherein the at least one memory and the
at least one processor reside on an application specific integrated
circuit (ASIC).
11. The system of claim 7, wherein determining the new protocol to
which the packet is to be updated comprises identifying pointers to
a packet editing program.
12. The system of claim 7, wherein deleting the existing packet
header comprises deleting selected portions of the existing header
that are not used by the new protocol.
13. The system of claim 12, wherein inserting the new packet header
comprises inserting portions of the new packet header based on the
new protocol and portions remaining from a previous packet
header.
14. The system of claim 7, wherein modifying the new packet header
comprises executing at least one of an overwrite or a
read-modify-write operation.
15. The system of claim 7, wherein the at least one processor is
further configured to transmit the packet including the new header
through a network based on the new header.
16. A non-transitory computer-readable medium storing instructions
executable by one or more processors for performing a method, the
method comprising: receiving a packet; classifying the packet, the
classification including determining a new protocol to which the
packet is to be updated; deleting an existing header of the packet;
inserting a new header in the packet based on the classification;
and modifying the new header based on the classification.
17. The non-transitory computer-readable medium of claim 16,
wherein determining the new protocol to which the packet is to be
updated comprises identifying pointers to a packet editing
program.
18. The non-transitory computer-readable medium of claim 16,
wherein: deleting the existing packet header comprises deleting
selected portions of the existing header that are not used by the
new protocol; and inserting the new packet header comprises
inserting portions of the new packet header based on the new
protocol and portions remaining from a previous packet header.
19. The non-transitory computer-readable medium of claim 16,
wherein modifying the new packet header comprises executing at
least one of an overwrite or a read-modify-write operation.
20. The non-transitory computer-readable medium of claim 16,
further comprising transmitting the packet including the new header
through a network based on the new header.
Description
BACKGROUND
[0001] Most networking application specific integrated circuits
(ASICs) implement a small and fixed set of packet header editing
capabilities for predefined network protocols. Examples of such
header editing capabilities for particular network protocols
include generic routing encapsulation (GRE) tunnel encapsulation
and decapsulation, virtual local area network/multiprotocol label
switching (VLAN/MPLS) tag push/pop, etc. New network protocols
require either a respin or a complete redesign of the ASIC, which
is both costly and time consuming. For example, redesigning and
replacing the ASICs in a network can take several years and cost
millions of dollars.
SUMMARY
[0002] A system and method is provided for expediently updating
network protocols. An ASIC adaptable to future network protocols
includes a Protocol Independent Packet Editor (PIPE), which may be
programmed to support packet header editing requirements of current
and possible future network protocols.
[0003] One aspect of the technology provides a method, comprising
receiving a packet, classifying, with one or more processors, the
packet, the classification including determining a new protocol to
which the packet is to be updated, deleting, with one or more
processors, an existing header of the packet, inserting, with one
or more processors, a new header in the packet based on the
classification, and modifying, with one or more processors, the new
header based on the classification. According to some examples,
determining the new protocol to which the packet is to be updated
comprises identifying pointers to a packet editing program.
Deleting the existing packet header may include deleting selected
portions of the existing header that are not used by the new
protocol. Moreover, inserting the new packet header may include
inserting portions of the new packet header based on the new
protocol and portions remaining from a previous packet header. The
packet including the new header may be transmitted through a
network based on the new header.
[0004] Another aspect of the disclosure provides a system,
comprising at least one memory and at least one processor in
communication with the at least one memory. The at least processor
is configured to receive a packet, classify the packet, the
classification including determining a new protocol to which the
packet is to be updated, delete an existing header of the packet,
insert a new header in the packet based on the classification, and
modify the new header based on the classification.
[0005] The at least one memory may include at least one packet
editing program, each packet editing program including pointers to
its editing instructions and pointers to sets of static data,
shared data, and dynamic data. The at least one memory may further
include meta data and register data accessible by the editing
instructions. Moreover, the at least one memory and the at least
one processor may reside on an application specific integrated
circuit (ASIC).
[0006] Yet another aspect of the disclosure provides a
non-transitory computer-readable medium storing instructions
executable by one or more processors for performing a method, the
method comprising receiving a packet, classifying the packet, the
classification including determining a new protocol to which the
packet is to be updated, deleting an existing header of the packet,
inserting a new header in the packet based on the classification,
and modifying the new header based on the classification.
BRIEF DESCRIPTION OF THE DRAWINGS
[0007] FIG. 1 is a system diagram according to an aspect of the
disclosure.
[0008] FIG. 2 is another system diagram according to aspects of the
disclosure.
[0009] FIGS. 3A-B illustrate example instruction formats according
to aspects of the disclosure.
[0010] FIG. 4 is another system diagram according to aspects of the
disclosure.
[0011] FIGS. 5A-F illustrate example instructions according to
aspects of the disclosure.
[0012] FIG. 6A-F illustrate example instructions according to
aspects of the disclosure.
[0013] FIG. 7 is another system diagram according to aspects of the
disclosure.
[0014] FIG. 8 is a flow diagram of an example method according to
aspects of the disclosure.
DETAILED DESCRIPTION
[0015] This disclosure provides a system and method for expediently
updating network protocols. Rather than redesigning and replacing
application specific integrated circuits (ASICs) when a network
protocol is updated, a new ASIC is designed to adapt to future
network protocols. The ASIC includes a Protocol Independent Packet
Editor (PIPE) which may be programmed to support packet header
editing requirements of current and possible future network
protocols.
[0016] According to one embodiment, the ASIC includes a Central
Editing Unit (CEU) that executes an editing program to operate on
the packet header. The Central Editing Unit is a processing
pipeline of three distinct editing units: a Deletion Unit, an
Insertion Unit, and a Modification Unit. Each unit operates on a
packet modified from the previous unit. This CEU pipeline enables
flexible packet header editing at high bandwidth and packet rate
with efficient hardware implementation in silicon.
[0017] The Deletion Unit enables the removal of arbitrary protocol
headers from the packet. The Insertion Unit enables the insertion
of arbitrary protocol headers into the packet. The Modification
Unit enables flexible rewriting (either overwrite, or
read-modify-write) of header fields.
[0018] The packet editing program executed by the CEU includes a
set of editing instructions (deletion, insertion, and field
modification), and a set of editing data (configuration, meta,
shared, and dynamic). One or more different editing programs may
exist for different packet header editing capabilities, such as
encapsulation, decapsulation, encryption, decryption, etc. A logic
unit parses and classifies the incoming packet to determine
pointers to program instructions and the associated data set.
[0019] The editing instructions may be, for example, 32 bytes or 64
byte in length. Editing instructions can be shared by the different
editing programs for different network operations. Each editing
program may include pointers to three sets of data: Static Data;
Shared Data (e.g., the [flowID,pkt_cnt,encryption key] of a
security flow state that is shared among different packet editing
programs); and Dynamic Data (e.g.. dedicated data to the program).
In addition, there are two sets of global data available to the
editing instructions: Meta Data, and Regular Data.
[0020] FIG. 1 illustrates an ASIC 100 according to aspects of the
disclosure. The ASIC 100 is adapted to receive a packet, such as
the packet 150, and update the packet in accordance with an updated
network protocol. According to some examples, the updated network
protocol may be a future network protocol that is not currently
developed. In this regard, rather than replacing each ASIC in a
network each time a protocol is updated, the ASIC and packets
transmitted through the network may be efficiently updated.
[0021] The ASIC 100 may be any of a number of ASICs interconnected
in a network. According to another example, the ASIC may be
designated for protocol updates. While the ASIC 100 is described as
having particular components, it should be understood that other
components, such as those typically found in an ASIC, may be
included. Moreover, while the components are shown as residing
within the ASIC 100, it should be understood that the components
may reside elsewhere in the network in communication with the ASIC
100.
[0022] The ASIC 100 includes user logic 110 and a packet editor
120. The packet editor 120 further includes at least one editing
program 130, including editing instructions 132 and editing data
134, and a central editing unit 140.
[0023] The user logic 110 parses packets received in the ASIC and
classifies the packets. For example, the user logic 110 may
determine which of a number of editing programs should operate on
the packet 150. Different editing programs may be created to update
different types of packets. For example, a first editing program
may be used to update a packet from a first protocol to a new
protocol, while a second editing program is used to update a packet
from a second protocol to the new protocol. According to another
example, a third editing program may be used to update encapsulated
packets, while a third editing program is used to update
decapsulated packets.
[0024] Each editing program includes editing data and editing
instructions. For example, the editing program 130 includes editing
instructions 132 and editing data 134. Further details of the
editing program are described below with respect to FIG. 4
[0025] The central editing unit 140 is a processing pipeline which
updates the packet 150 according to the editing program identified
by the user logic 110. Accordingly, the ASIC 100 can send updated
packet 150' through the network.
[0026] FIG. 2 illustrates further details of the central editing
unit 140. As shown, the central editing unit 140 includes a
deletion unit 210, an insertion unit 220, and a modification unit
230. Each of these units 210, 220, 230 operates on the incoming
packet 150 in accordance with a set of instructions for a
particular editing program, such as the instructions 132. As
discussed below with respect to FIG. 4, the instructions 132 may
include a separate set of instructions for each unit 210, 220, 230.
The insertion unit 220 operates on the packet 150 after the packet
has been modified by the deletion unit 210. Similarly, the
modification unit 230 operates on the packet after the packet has
been modified by the insertion unit 220. Each unit may realign a
byte stream for the packet after its operation and before passing
the packet to the next unit. This central editing unit pipeline
enables flexible packet header editing at high bandwidth and packet
rate. Moreover, the pipeline provides for efficient hardware
implementation in silicon.
[0027] The deletion unit 210 enables the removal of arbitrary
protocol headers from the packet. For example, for packets
including multiple headers, such as an inner IP header and an outer
IP header in a tunneled network, the deletion unit 210 may remove
all packet headers or selected packet headers. According to another
example, the deletion unit 210 may delete particular fields of
packet, while keeping others that are relevant to the updated
network protocol.
[0028] The insertion unit 220 enables the insertion of arbitrary
protocol headers into the packet. For example, the insertion unit
220 may generate a new set of header fields related to the update
network protocol and add these generated fields to the packet 150.
In the example where only particular fields are deleted by the
deletion unit 210, the insertion unit 220 may determine that the
remaining fields do not need to be regenerated, and instead only
generate the needed fields. In other examples, the insertion unit
220 may generate the header in its entirety.
[0029] The modification unit 230 enables flexible rewriting, such
as overwrite or read-modify-write, of header fields. For example,
the modification unit 230 may fill the packet header fields with
information enabling the packet to be appropriately transmitted
through the updated network.
[0030] As discussed above in connection with FIG. 1, each packet
editing program includes editing instructions and an editing data
set. For example, a program may have a 16-bit pointer to its
editing instructions. According to some examples, editing
instructions can be shared by different editing programs. For
example, encapsulation under a first network protocol and
encapsulation under a second network protocol may utilize the same
editing instructions.
[0031] FIGS. 3A and 3B illustrate example formats of the editing
instructions. In the example of FIG. 3A, the instructions are 32 B.
Bytes 0-7 are dedicated to deletion, bytes 8-15 are dedicated to
insertion, and bytes 16-31 are dedicated to modification. In the
example of FIG. 3B, the instructions are 64 B. Here, similar to the
32 B format, bytes 0-7 are dedicated to deletion. However, in
contrast to the 32 B format, bytes 8-31 are dedicated to insertion
in the 64 B format, and bytes 32-63 are dedicated to
modification.
[0032] FIG. 4 provides a more detailed illustration of an editing
program 430. The editing program 430 includes editing instructions
440 and editing data 450.
[0033] Editing data 450 includes static data 452, shared data 454,
and dynamic data 456. For example, each editing program may include
pointers to these data sets, which may be stored in a memory in
communication with the ASIC. According to one example, the static
data 452 and shared data 454 may each be 32 B, and the dynamic data
456 may be 32 B-64 B of data dedicated to the particular editing
program. According to one example, multipath load balancing can be
supported by selecting the shared/dynamic data sets from a group of
shared/dynamic data sets with a hash generated from selected
n-tuple header fields.
[0034] Though not shown, additional data may be available to the
editing instructions, such as meta data and register data. For
example, 32 B of meta data may be available, in which the first
8.times.2 B halfword are metadata, such as pkt_length, ip_pkt_id,
flow_hash, slice_ID, etc. The second 8.times.2 B halfwords are 2 B
header fields collected from the packet header, e.g. IP_PROTO, TTL,
TOS etc. For example, through the parsing of the user logic, the
packet format is identified and 8.times.2 B offsets are specified
to select the desired header fields. As another example, 64 B of
register data may be available to the editing instructions, with
8.times.8 B registers. In this example, Register 0 is hardcoded to
all zeros; Register 1 is optionally loaded with 64 bit packet
count; Register 2 is optionally loaded with 64 bit timestamp; and
Registers 3-7 are configured by software with static data.
[0035] Editing instructions 440 include delete instruction 442,
insert instruction 444, and modify instructions 446. Examples of
particular insert instructions 444 are shown, such as <INS
NOP> and <INS MOV>, and described in further detail in
FIGS. 5A-5F. Examples of particular modify instructions 446, such
as <MOD NOP> and <MOD WRITE META>, are also shown and
described in further detail in FIGS. 6A-6F.
[0036] Delete instructions 442 may be, for example, 8 B in length,
with each bit representing a 2 B halfword of a 128 B packet header.
When a bit is set, the corresponding 2 B halfword is deleted from
the packet header. A 64 bit zero is effectively a no operation
(NOP) deletion instruction.
[0037] Insert instructions 444 may be executed by, for example, the
insertion unit 220 of FIG. 2. According to one example, the
insertion unit 220 maintains an active header pointer (e.g., in
units of 2 B halfwords) which starts at zero. A MOV instruction,
described in further detail below with respect to FIG. 5A, moves
the header pointer forward. The insert instruction inserts the
specified data at the current active header pointer, and moves the
header pointer forward by the number of halfwords inserted. All
insert instructions 444 may be, for example, 8 bit wide.
[0038] FIGS. 5A-5F illustrate example insert instructions 444,
including move, and operations on particular data sets. Not shown
is a no operation insertion instruction. For example, 8 bits of
zeros is a NOP, indicating the end of the insertion
instructions.
[0039] FIG. 5A illustrates an example INS MOV instruction. This
instruction advances a current insertion pointer by a specified
count (cnt). For example, as shown, bits 0-5 include the count,
while bits 7-8 are set to 0.
[0040] FIG. 5B illustrates an example INS STATIC instruction. This
instruction inserts specified (cnt) halfwords from the Static Data
Set (e.g., static data 452 of FIG. 4). If h=0, the data starts from
the lower 16 B. If h=1, the data starts from the upper 16 B.
[0041] FIG. 5C illustrates an example INS SHARED instruction. This
instruction may operate on the shared data set (e.g., shared data
454 of FIG. 4) the same way that the INS STATIC instruction
operates on the static data set. Similarly, FIG. 5D illustrates an
example INS DYNAMIC L instructions that also operates the same way
on a first 32 B of dynamic data, such as the dynamic data 456 of
FIG. 4. Further, FIG. 5E illustrates an example INS DYNAMIC H
instructions, which also operates the same way on the second 32 B
of dynamic data.
[0042] FIG. 5F illustrates an example INS REG instruction, which
inserts cnt halfwords from selected global register data.
[0043] Modify instructions 446 may generally operate on a halfword,
with optional bits or bytes selected in some instructions.
According to some example, two modify instructions may operate on
same halfword, each operating on a different byte. MOD NOP
indicates a no operation modification instruction, and may be
represented by 16 bits of 0. This indicates the end of the modify
instructions.
[0044] FIG. 6A illustrates an example MOD WRITE META instruction.
According to this instruction, a write operation is performed at
the offset (in unit of halfwords) with the selected (sel[3:0]) 2 B
field from the Meta Data set, according to the specified op_code.
Examples of supported write op_code rewriting 4 nibbles of metadata
include: 1. ABCD>ABCD; 2. ABCD>ABXX; 3. ABCD>XXCD; 4.
ABCD>XXAB; 5. ABCD>CDXX; 6. ABCD>XCDX; 7. ABCD>XXBC. In
these examples, "X" indicates that the nibble is not changed.
Examples 6 and 7 may be usefully, for example, in copying DSCP/ECN
between IPv4 and IPv6 headers.
[0045] FIG. 6B illustrates an example MOD_CHKSUM instruction. This
instruction computes the 1's complement checksum (as in IPv4
header) starting at hdr_offset (within the first 64 B of the
header), for hdr_len halfwords, and writes the computed checksum
field at the specified csum offset location relative to the hdr
offset field. The checksum field itself is not included in the
checksum accumulation.
[0046] FIG. 6C illustrates an example MOD_ALU instruction, which
executes operations specified by the op_code, for the byte/halfword
(specified by byte enable "ben") at the header offset. Examples of
supported op_code include: 0--set to zero; 1--set to 1; 2--add 1;
3--add 1 but stops at 8 hF or 16 hFF; 4--subtract 1; 5--subtract 1
but stops at zero.
[0047] FIG. 6D illustrates an example MOD_CKSUM_INC instruction,
which performs an incremental checksum update of the checksum field
at csum_offset, with the incremental value specified in
imm_data.
[0048] FIG. 6E illustrates an example MOD_WRITE_IMM instruction,
which overwrites the header field at offset with the 16 bit
immediate data imm data. Each bit of the nibble en enables one
nibble in the halfword to be overwritten.
[0049] FIG. 6F illustrates an example MOD_WRITE_META IMM
instruction, which writes at the offset (in unit of halfwords) with
the result of operations (specified by the op_code) between the
imm_data and the selected (sel[3:0]) 2 B field from the Meta Data.
Examples of supported op_code include: 0--Add; 1--Bitwide OR;
2--Bitwide AND.
[0050] While a number of example instructions have been explained,
it should be understood that these examples are not exhaustive, and
that additional instructions may be used to update the packet
headers. Moreover, it should be understood that these example
instructions may be modified while still achieving the intended
effect.
[0051] FIG. 7 illustrates an example computing device which may be
implemented to update the packet headers as described herein. The
computing device may be an ASIC or other device, or multiple
computing devices or components in communication with each other,
including a processor 730 and a memory 720. The computing device
700 may further include one or more input ports 750 for receiving
data packets or other information from other computing devices.
Similarly, the computing device 700 may have one or more output
ports 760 for transmitting packets, for example, after the packet
headers have been updated according to the new network
protocol.
[0052] The memory 720 stores information accessible by processor
730, including instructions 728, and data 722 that may be executed
or otherwise used by the processor 730. The memory 720 may be of
any type capable of storing information accessible by the
processor, including a computer-readable medium, or other medium
that stores data that may be read with the aid of an electronic
device, such as a hard-drive, memory card, ROM, RAM, DVD or other
optical disks, as well as other write-capable and read-only
memories. According to one example, referring back to FIG. 4, the
editing data 450 and editing instructions 440 may share a single
logic SRAM, enabling dynamic allocation of SRAM resources among
them. Systems and methods may include different combinations of the
foregoing, whereby different portions of the instructions and data
are stored on different types of media.
[0053] The instructions 728 may be any set of instructions to be
executed directly (such as machine code) or indirectly (such as
scripts) by the processor 730. For example, the instructions may be
stored as computer code on the computer-readable medium. In that
regard, the terms "instructions" and "programs" may be used
interchangeably herein. The instructions may be stored in object
code format for direct processing by the processor, or in any other
computer language including scripts or collections of independent
source code modules that are interpreted on demand or compiled in
advance. Upon receipt of a packet, the processor 730 may execute
the instructions 728 to, for example, classify the packet, delete
the packet header, insert a new packet header based on the
classification, and modify the packet header based on the
classification.
[0054] The data 722 may be retrieved, stored or modified by
processor 730 in accordance with the instructions 728. For
instance, although the system and method is not limited by any
particular data structure, the data may be stored in computer
registers, in a relational database as a table having a plurality
of different fields and records, XML documents or flat files. The
data may also be formatted in any computer-readable format. The
data may comprise any information sufficient to identify the
relevant information, such as numbers, descriptive text,
proprietary codes, references to data stored in other areas of the
same memory or different memories (including other network
locations) or information that is used by a function to calculate
the relevant data.
[0055] The processor 730 may be any conventional processor, such as
processors in commercially available routers. Alternatively, the
processor may be a dedicated controller such as an ASIC or other
hardware-based processor. The processor and memory may actually
comprise multiple processors and memories that may or may not be
stored within the same physical housing. For example, memory may be
a hard drive or other storage media located in a server farm of a
data center. Accordingly, references to a processor, memory, or
computer will be understood to include references to a collection
of processors, memories or computers that may or may not operate in
parallel.
[0056] The computing device 700 may communicate with other
computing devices, for example, over a network. For example, the
devices may communicate via a wired connection or wirelessly. The
network, and intervening nodes, may comprise various configurations
and protocols including the Internet, World Wide Web, intranets,
virtual private networks, wide area networks, local networks,
private networks using communication protocols proprietary to one
or more companies, Ethernet, WiFi (such as 802.11, 802.11b, g, n,
or other such standards), and HTTP, and various combinations of the
foregoing. Such communication may be facilitated by any device
capable of transmitting data to and from other computers, such as
modems (e.g., dial-up, cable or fiber optic) and wireless
interfaces.
[0057] FIG. 8 illustrates an example method of updating packets to
comply with a new network protocol. For example, this method may be
performed by a computing device, such as the computing device
described above. It should be understood that the operations
involved in this method need not be performed in the precise order
described. Rather, various operations may be handled in a different
order or simultaneously, and operations may be added or
omitted.
[0058] In block 810, a packet is received. In block 820, the
received packet is classified. For example, classification may
include determining a format of the received packet and determining
a new protocol in accordance with which the received packet should
be updated. According to one example, classification includes
determining whether the received packet includes pointers to a
particular packet editing program and associated data set.
[0059] In block 830, the packet header is deleted. For example, the
header may be deleted in its entirety, or deleted in part based on
the new protocol header format.
[0060] In block 840, a new protocol header is inserted based on the
classification. For example, the new header may be inserted in
whole or in part, based on the deletion. The header may be inserted
using, for example, any of the operations described above in
connection with FIGS. 4 and 5A-F.
[0061] In block 850, the header may be modified. For example, the
new header fields may be written and/or existing header fields may
be overwritten or modified. Modification of the header fields may
be performed using, for example, any of the instructions described
above in connection with FIGS. 4 and 6A-F. Once the packet header
is modified, the updated packet may be output, for example, through
an output port of the computing device.
[0062] The systems, methods, and examples described above are
advantageous in that they provide for adapting existing networks to
new protocols that have not yet been defined. Rather than
redesigning and replacing numerous ASICs each time a protocol
update is to take place, packet headers may be modified for use by
the existing ASICs. In this regard, substantial time, effort, and
cost are saved.
[0063] As these and other variations and combinations of the
features discussed above can be utilized without departing from the
subject matter defined by the claims, the foregoing description of
the embodiments should be taken by way of illustration rather than
by way of limitation of the subject matter defined by the claims.
As an example, the preceding operations do not have to be performed
in the precise order described above. Rather, various steps can be
handled in a different order or simultaneously. Steps can also be
omitted unless otherwise stated. In addition, the provision of the
examples described herein, as well as clauses phrased as "such as,"
"including" and the like, should not be interpreted as limiting the
subject matter of the claims to the specific examples; rather, the
examples are intended to illustrate only one of many possible
embodiments. Further, the same reference numbers in different
drawings can identify the same or similar elements.
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