U.S. patent application number 14/737239 was filed with the patent office on 2015-10-29 for variable resistive memory device including vertical channel pmos transistor and method of manufacturing the same.
The applicant listed for this patent is SK hynix Inc.. Invention is credited to Nam Kyun PARK.
Application Number | 20150311316 14/737239 |
Document ID | / |
Family ID | 52466163 |
Filed Date | 2015-10-29 |
United States Patent
Application |
20150311316 |
Kind Code |
A1 |
PARK; Nam Kyun |
October 29, 2015 |
VARIABLE RESISTIVE MEMORY DEVICE INCLUDING VERTICAL CHANNEL PMOS
TRANSISTOR AND METHOD OF MANUFACTURING THE SAME
Abstract
A semiconductor device having a vertical channel, a variable
resistive memory device including the same, and a method of
manufacturing the same are provided. The semiconductor device
having a vertical channel includes a vertical pillar formed on a
semiconductor substrate and including an inner portion and an outer
portion surrounding the inner portion, junction regions formed in
the outer portion of the vertical pillar, and a gate formed to
surround the vertical pillar. The inner portion of the vertical
pillar has a lattice constant smaller than that of the outer
portion of the vertical pillar.
Inventors: |
PARK; Nam Kyun;
(Gyeonggi-do, KR) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
SK hynix Inc. |
Gyeonggi-do |
|
KR |
|
|
Family ID: |
52466163 |
Appl. No.: |
14/737239 |
Filed: |
June 11, 2015 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
14076921 |
Nov 11, 2013 |
9082697 |
|
|
14737239 |
|
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Current U.S.
Class: |
438/268 |
Current CPC
Class: |
H01L 29/1054 20130101;
H01L 27/2454 20130101; H01L 29/2003 20130101; H01L 29/1608
20130101; H01L 29/7827 20130101; H01L 27/228 20130101; H01L
29/66666 20130101 |
International
Class: |
H01L 29/66 20060101
H01L029/66; H01L 27/24 20060101 H01L027/24; H01L 29/16 20060101
H01L029/16 |
Foreign Application Data
Date |
Code |
Application Number |
Aug 19, 2013 |
KR |
10-2013-0097818 |
Claims
1-14. (canceled)
15. A method of manufacturing a semiconductor device, the method
comprising: forming a first semiconductor layer on a semiconductor
substrate, wherein the first semiconductor layer has a lattice
constant smaller than that of the semiconductor substrate;
patterning the first semiconductor layer and a portion of the
semiconductor substrate to form a preliminary pillar; forming a
second semiconductor layer having the same material as the
semiconductor substrate, on an outer circumference of the
preliminary pillar, to form a pillar; forming a drain in an upper
portion of the pillar and a source in a lower portion of the
pillar; and forming a gate to surround an outer circumference of
the pillar.
16. The method of claim 15, further comprising: forming a third
semiconductor layer having the same material as the semiconductor
substrate, on the first semiconductor layer, between the forming of
the first semiconductor layer and the patterning of the first
semiconductor layer and the portion of the semiconductor substrate;
and patterning the third semiconductor layer to form the
preliminary pillar during the patterning of the first semiconductor
layer and the portion of the semiconductor substrate.
17. The method of claim 16, wherein at least one of the
semiconductor substrate, the second semiconductor layer, and the
third semiconductor layer includes a silicon (Si) material.
18. The method of claim 16, wherein at least one of the
semiconductor substrate, the first semiconductor layer, the second
semiconductor layer, and the third semiconductor layer is formed
through an epitaxial growth method.
19. The method of claim 15, wherein the first semiconductor layer
includes one selected from the group consisting of SiC, AlN, GaN,
ZnS, ZnO, ZnSe, CdS, BP, InN, and CdSe.
20. The method of claim 15, wherein the forming of the first
semiconductor layer includes: forming a C-low concentration-SiC
layer that contains a content of C below a stoichiometric content
of C in SiC, on the semiconductor substrate; and forming a C-high
concentration-SiC layer that contains a content of C above the
stoichiometric content of C in SiC, on the C-low concentration-SiC
layer.
Description
CROSS-REFERENCES TO RELATED APPLICATION
[0001] This application claims priority under 35 U.S.C. 119(a) to
Korean application No. 10-2013-0097818, filed on Aug. 19, 2013, in
the Korean Intellectual Property Office, which is incorporated by
reference in its entirety as set forth in full.
BACKGROUND
[0002] 1. Technical Field
[0003] The inventive concept relates to a semiconductor integration
circuit device and a method of manufacturing the same, and, more
particularly, to a variable resistive memory device including a
PMOS transistor having a vertical channel and a method of
manufacturing the same.
[0004] 2. Related Art
[0005] With the rapid development of mobile and digital information
communication and consumer-electronic industries, studies on
existing electronic charge-controlled devices may encounter
limitations. Thus, new functional memory devices other than the
existing electronic charge-controlled devices need to be developed.
In particular, next-generation memory devices with large capacity,
ultra-high speed, and ultra-low power need to be developed to
satisfy demands on large capacity of memories in main information
apparatuses.
[0006] Currently, variable resistive memory devices using a
resistive device as a memory medium have been suggested as the
next-generation memory devices. Typically examples of the
resistance variable memory device are phase-change random access
memories (PCRAMs), resistive RAMs (ReRAMs), and magneto-resistive
RAMs (MRAMs).
[0007] Each of the variable resistive memory devices may include a
switching device and a resistive device, and store data "0" or "1"
according to a state of the resistive device.
[0008] Even in the variable resistive memory devices, the first
priority is to improve integration density and to integrate memory
cells in a limited and small area, integrating as many as
possible.
[0009] To satisfy the demands, the variable resistive memory
devices also employ a three-dimensional (3D) transistor structure.
The 3D transistors may include a channel extending to a direction
perpendicular to a surface of a semiconductor substrate and a
surrounding gate formed to surround the channel.
[0010] The 3D transistors require a high operation current to
maintain high resistance variable characteristics.
SUMMARY
[0011] According to an exemplary embodiment of the inventive
concept, there is provided a semiconductor device. The
semiconductor device may include a vertical pillar formed on a
semiconductor substrate and including an inner portion and an outer
portion surrounding the inner portion, junction regions formed in
the outer portion of the vertical pillar, and a gate formed to
surround the vertical pillar, Wherein the inner portion of the
vertical pillar has a lattice constant smaller than that of the
outer portion of the vertical pillar.
[0012] According to another exemplary embodiment of the inventive
concept, there is provided a variable resistive memory device. The
variable resistive memory device may include a pillar including a
channel region, a source located below the channel region, and a
drain located on the channel region; a gate formed to surround an
outer circumference of the pillar, a heating electrode formed over
the drain, and a variable resistance layer formed on the heating
electrode, wherein the channel region of the pillar is formed in
such a manner that compressive stress is provided to the channel
region by a junction of the channel region with at least one of
regions in which the source and the drain are formed.
[0013] According to still another exemplary embodiment of the
inventive concept, there is provided a method of manufacturing a
semiconductor device. The method may include forming a first
semiconductor layer on the semiconductor substrate, wherein the
first semiconductor layer has a lattice constant smaller than that
of a semiconductor substrate; patterning the first semiconductor
layer and a portion of the semiconductor substrate to form a
preliminary pillar; forming a second semiconductor layer having the
same material as the semiconductor substrate on an outer
circumference of the preliminary pillar to form a pillar; forming a
drain in an upper portion of the pillar and a source in a lower
portion of the pillar; and forming a gate to surround an outer
circumference of the pillar.
[0014] These and other features, aspects, and embodiments are
described below.
BRIEF DESCRIPTION OF THE DRAWINGS
[0015] The above and other aspects, features and other advantages
of the subject matter of the present disclosure will be more
clearly understood from the following detailed description taken in
conjunction with the accompanying drawings, in which:
[0016] FIGS. 1 to 5 are cross-sectional views illustrating a method
of manufacturing a semiconductor device having a vertical channel
according to an embodiment of the inventive concept;
[0017] FIG. 6 is a cross-sectional view illustrating a variable
resistive memory device including a semiconductor device having a
vertical channel according to an embodiment of the inventive
concept;
[0018] FIG. 7 is a perspective view illustrating a semiconductor
device having a vertical channel according to an embodiment of the
inventive concept; and
[0019] FIGS. 8 to 10 are cross-sectional views illustrating a
method of manufacturing a semiconductor device having a vertical
channel according to another embodiment of the inventive
concept.
DETAILED DESCRIPTION
[0020] Hereinafter, exemplary embodiments will be described in
greater detail with reference to the accompanying drawings.
Exemplary embodiments are described herein with reference to
cross-sectional illustrations that are schematic illustrations of
exemplary embodiments and intermediate structures. As such,
variations from the shapes of the illustrations as a result, for
example, of manufacturing techniques and/or tolerances, are to be
expected. Thus, exemplary embodiments should not be construed as
limited to the particular shapes of regions illustrated herein but
may include deviations in shapes that result, for example, from
manufacturing. In the drawings, lengths and sizes of layers and
regions may be exaggerated for clarity. Like reference numerals in
the drawings denote like elements. It is also understood that when
a layer is referred to as being "on" another layer or substrate, it
can be directly on the other or substrate, or intervening layers
may also be present. It is also noted that in this specification,
"connected/coupled" refers to one component not only directly
coupling another component but also indirectly coupling another
component through an intermediate component. In addition, a
singular form may include a plural form as long as it is not
specifically mentioned in a sentence.
[0021] The inventive concept is described herein with reference to
cross-section and/or plan illustrations that are schematic
illustrations of exemplary embodiments of the inventive concept.
However, embodiments of the inventive concept should not be
construed as limited to the inventive concept. Although a few
embodiments of the inventive concept will be shown and described,
it will be appreciated by those of ordinary skill in the art that
changes may be made in these exemplary embodiments without
departing from the principles and spirit of the inventive
concept.
[0022] Referring to FIG. 1 a semiconductor substrate 200 is
prepared. The semiconductor substrate 200 may be, for example, a
silicon (Si) substrate containing first conductivity impurities
such as N type impurities. The N type impurities may include
phosphor (P) or arsenic (As). A first semiconductor layer 210 and a
second semiconductor layer 220 are sequentially deposited on the
semiconductor substrate 200. The first semiconductor layer 210 may
be formed of a material having a lattice constant smaller than that
of the semiconductor substrate 200 formed of silicon (Si). The
first semiconductor layer 210 may include one selected from the
group consisting of silicon carbide (SiC), aluminum nitride (AlN),
gallium nitride (GaN), zinc sulfide (ZnS), zinc oxide (ZnO), zinc
selenide (ZnSe), cadmium sulfide (CdS), boron phosphide (BP),
indium nitride (InN), and cadmium selenide (CdSe). The first
semiconductor layer 210 may be a region in which a channel is to be
substantially formed in a subsequent process. A thickness of the
first semiconductor layer 210 may be determined by considering a
length of the channel. For example, the first semiconductor layer
210 may be grown in a single crystalline structure through an
epitaxial growth method by considering carrier mobility
characteristics. The second semiconductor layer 220 may be formed
on the first semiconductor layer 210. The second semiconductor
layer 220 may be formed of the same material as that of the
semiconductor substrate 200, for example, silicon (Si). The second
semiconductor layer 220 may be a region in which a drain region is
to be formed in a subsequent process. A length of the second
semiconductor layer 220 may be determined by considering a width of
the drain region.
[0023] Referring to FIG. 2, the second semiconductor layer 220, the
first semiconductor layer 210, and a portion of the semiconductor
substrate 200 are patterned to form a preliminary pillar P11. The
preliminary pillar P11 may have a line width smaller than that of a
vertical channel to be formed. The reference numerals 220a, 210a,
and 200a denote a patterned second semiconductor layer, a patterned
first semiconductor layer, and a patterned portion of the
semiconductor substrate, respectively.
[0024] Referring to FIG. 3, a third semiconductor layer 225 may be
formed on an outer wall of the preliminary pillar P11 referenced in
FIG. 2. For example, the third semiconductor layer 225 may be
formed of the same material as those of the patterned portion of
the semiconductor substrate 200a and the patterned second
semiconductor layer 220a, such as, a silicon (Si) material. The
third semiconductor layer 225 may be formed on the resulting
structure on the semiconductor substrate, in which the preliminary
pillar P11 referenced in FIG. 2 is formed, using an epitaxial
growth method. The third semiconductor layer 225 may be formed on
the outer wall of the preliminary pillar P11 referenced in FIG. 2
using a spacer etching method such as an anisotropic etching
method. Therefore, a pillar P for forming a vertical channel is
completed. An inner portion of the pillar P is formed of a material
having a lattice constant smaller than that of an outer portion of
the pillar P. That is, a channel region in which a channel is to be
substantially formed and a region other than the channel region may
be formed of different semiconductor materials from each other, and
the channel region may be formed to be surrounded with the region
other than the channel region. The channel region may be formed of
a material having a lattice constant smaller than that of the
region other than the channel region.
[0025] Referring to FIG. 4, a gate insulating layer 230 may be
formed on the pillar P and an exposed surface of the semiconductor
substrate 200. The gate insulating layer 230 may include a silicon
oxide (SiO.sub.2) layer formed through an oxidation method. The
gate insulating layer 230 may include a metal oxide layer such as a
tantalum oxide (TaO) layer, a titanium oxide (TiO) ager, a barium
titanate (BaTiO) layer, a barium zirconate (BaZrO) layer, a
zirconium oxide (ZrO) layer, a hafnium oxide (HfO) layer, a
lanthanum oxide (LaO) layer, an aluminum oxide (AlO) layer, an
yttrium oxide (YO) layer, or a zirconium silicide oxide (ZrSiO)
layer, or a metal nitride layer, or a combination thereof, which is
deposited through a deposition method.
[0026] Referring to FIG. 5, second conductivity impurities, for
example, P type impurities such as, ions containing boron (B), are
implanted into an upper region (a region corresponding to the
second semiconductor layer) and a lower region (a region
corresponding to the semiconductor substrate) of the pillar P to
form a drain D in the upper region of the pillar P and form a
source in the lower region of the pillar P, thus, a PMOS transistor
is defined. The source may be formed in the entire semiconductor
substrate 200, that is, an entire active region defined in the
semiconductor substrate 200 to operate as a common source CS. The
drain D may be formed in a lightly doped drain (LDD) manner to
reduce a short channel effect such as gate-induced drain leakage
(GIDL). Next, a surrounding gate 240 may be formed on an outer
circumference of the pillar P. The surrounding gate 240 may be
formed, for example, by depositing a gate conductive layer on a
surface of the resulting structure on the semiconductor substrate,
in which the gate insulating layer 230 is formed, and etching the
gate conductive layer using an anisotropic etching method. The
surrounding gate 240 may be formed to have a height lower than that
of the pillar P. The surrounding gate 240 may be formed to
correspond to a substantial channel region, that is, a region of
the patterned first semiconductor layer 210a. The surrounding gate
240 may include, for example, at least one selected from the group
consisting of tungsten (W), copper (Cu), titanium nitride (TiN),
tantalum nitride (TaN), tungsten nitride (WN), molybdenum nitride
(MoN), niobium nitride (NbN), titanium silicon nitride (TiSiN),
titanium aluminum nitride (TiAlN), titanium boron nitride (TiBN),
zirconium silicon nitride (ZrSiN), tungsten silicon nitride (WSiN),
tungsten boron nitride (WBN), zirconium aluminum nitride (ZrAlN),
molybdenum silicon nitride (MoSiN), molybdenum aluminum nitride
(MoAlN), tantalum silicon nitride (TaSiN), tantalum aluminum
nitride (TaAlN), titanium (Ti), molybdenum (Mo), tantalum (Ta),
titanium silicide (TiSi), tantalum silicide (TaSi), titanium
tungsten (TiW), titanium oxynitride (TiON), titanium aluminum
oxynitride (TiAlON), tungsten oxynitride (WON), tantalum oxynitride
(TaON), and doped polysilicon. Next, an interlayer insulating layer
245 may be formed to be buried in the resulting structure on the
semiconductor substrate, in which the surrounding gate 240 is
formed.
[0027] As illustrated in FIG. 6, a heating electrode 250 and a
patterned variable resistance layer 255 are sequentially formed on
the drain D to form a variable resistive memory device. The heating
electrode 250 and the patterned variable resistance layer 255 may
be formed by sequentially forming a heating electrode layer and a
variable resistance layer on the resulting structure on the
semiconductor substrate, in which the interlayer insulating layer
245 is formed, and patterning the heating electrode layer and the
variable resistance layer. The patterned variable resistance layer
255 may include a PCMO layer for a ReRAM, a chalcogenide layer for
a PCRAM, a magnetic layer for a MRAM, a magnetization reversal
device layer for a spin-transfer torque magnetoresistive RAM
(STTMRAM), or a polymer layer for a polymer RAM (PoRAM).
[0028] As illustrated in FIG. 7, the PMOS transistor according to
an embodiment may be formed so that the patterned first
semiconductor layer 210a in which a channel is to be substantially
formed may be formed of a material having a smaller lattice
constant than the region other than the channel region, which
includes, for example, the patterned portion of the semiconductor
substrate 200a, the patterned second semiconductor layer 220a, and
the third semiconductor layer 225. Therefore, differences of the
lattice constants may be generated in junction interfaces between
the semiconductor substrate 200 and the patterned first
semiconductor layer 210a and between the patterned first
semiconductor layer 210a and the patterned second semiconductor
layer 220a, and thus compressive stress may be applied to the
patterned first semiconductor layer 210a. When the compressive
stress is applied to the patterned first semiconductor layer 210a
in which the channel is to be formed, hole mobility of the PMOS
transistor in which holes are major mobility may be considerably
increased, and thus current drivability of the PMOS transistor may
be improved.
[0029] Further, an outer circumference of the patterned first
semiconductor layer 210a is surrounded with the third semiconductor
layer 225 having a lattice constant different from the patterned
first semiconductor layer 210a, in order to further apply
additional compressive stress to the patterned first semiconductor
layer 210a through a lateral junction between the patterned first
semiconductor layers 210a and the third semiconductor layers
225.
[0030] As illustrated in FIG. 8, a patterned first semiconductor
layer 210a of a preliminary pillar P11 may be formed of a stacking
layer including a first sub semiconductor layer 210-1, a second sub
semiconductor layer 210-2, and a third sub semiconductor layer
210-3. When the patterned first semiconductor layer 210a is formed
of SiC, the first sub semiconductor layer 210-1 and the third sub
semiconductor layer 210-3 may be a SiC layer (hereinafter, referred
to as a C-low concentration-SiC layer) in which a content of carbon
(C) below a stoichiometric ratio of C in SiC is contained, and the
second sub semiconductor layer 210-2 may be a SiC layer
(hereinafter, referred to as a C-high concentration-SiC layer) in
which a content of C above the stoichiometric ratio of C in SiC is
contained. When the content of C in the SiC layer is increased, the
lattice constant of the SiC layer tends to decrease. Therefore, a
material having the smallest lattice constant is formed in a
substantial effective channel zone of the patterned first
semiconductor layer 210a to reduce electron mobility in the channel
and to maximize hole mobility in the channel.
[0031] As illustrated in FIG. 9, a patterned first semiconductor
layer 212 further extends by a length of a drain to form a
preliminary pillar P11 without the patterned second semiconductor
layer 220a of FIG. 2. Therefore, a drain D may be formed in an
upper portion of the patterned first semiconductor layer 212.
[0032] As illustrated in FIG. 10, a patterned first semiconductor
layer 215 extends by a length of a drain to form a preliminary
pillar P11 without the patterned second semiconductor layer 220a of
FIG. 2 as described in FIG. 9. The patterned first semiconductor
layer 215 may be formed of a C-low concentration-SiC layer 215-1
and a C-high concentration-SiC layer 215-2. The configuration of
the patterned first semiconductor layer 215 may reduce a lattice
constant of a channel to a direction of a drain D to increase a
drain current of the PMOS transistor.
[0033] According to the embodiments, in a pillar structure having
an inner portion and an outer portion formed to surround the inner
portion, the inner portion is formed of a material having a smaller
lattice constant than that of the outer portion. Therefore,
compressive stress is applied to the inner portion of the pillar,
in which a channel is to be substantially formed, thereby improving
current drivability of the PMOS transistor.
[0034] The above embodiment of the present invention is
illustrative and not limitative. Various alternatives and
equivalents are possible. The invention is not limited by the
embodiments described herein. Nor is the invention limited to any
specific type of semiconductor device. Other additions,
subtractions, or modifications are obvious in view of the present
disclosure and are intended to fall within the scope of the
appended claims.
* * * * *