U.S. patent application number 14/310826 was filed with the patent office on 2015-10-29 for array substrate, its manufacturing method, and display device.
The applicant listed for this patent is BEIJING BOE DISPLAY TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.. Invention is credited to Jinchao Bai, Xiangqian Ding, Zongjie Guo, Liangliang Li, Yao Liu.
Application Number | 20150311222 14/310826 |
Document ID | / |
Family ID | 51241556 |
Filed Date | 2015-10-29 |
United States Patent
Application |
20150311222 |
Kind Code |
A1 |
Bai; Jinchao ; et
al. |
October 29, 2015 |
Array Substrate, Its Manufacturing Method, and Display Device
Abstract
The present invention provides an array substrate, its
manufacturing method, and a display device. The array substrate
comprises a gate metal layer, a gate insulating layer, a
source/drain metal layer, first common electrode lines arranged on
an identical layer to the gate metal layer, a first via hole
arranged in the gate insulating layer and corresponding to the
first common electrode line, a source/drain metal filling part
arranged within the first via hole, a second via hole in
communication with the first via hole, and a transparent connection
part. The first common electrode lines are, by means of the
transparent connection part and the source/drain metal filling
part, in electrical connection with each other through the second
via hole. According to the present invention, it is able to reduce
the depth of the via holes in the array substrate, and improve the
uneven diffusion of an alignment layer.
Inventors: |
Bai; Jinchao; (Beijing,
CN) ; Liu; Yao; (Beijing, CN) ; Li;
Liangliang; (Beijing, CN) ; Ding; Xiangqian;
(Beijing, CN) ; Guo; Zongjie; (Beijing,
CN) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
BOE TECHNOLOGY GROUP CO., LTD.
BEIJING BOE DISPLAY TECHNOLOGY CO., LTD. |
Beijing
Beijing |
|
CN
CN |
|
|
Family ID: |
51241556 |
Appl. No.: |
14/310826 |
Filed: |
June 20, 2014 |
Current U.S.
Class: |
257/72 ;
438/158 |
Current CPC
Class: |
H01L 23/5226 20130101;
H01L 27/124 20130101; H01L 2924/0002 20130101; H01L 2924/0002
20130101; H01L 2924/00 20130101 |
International
Class: |
H01L 27/12 20060101
H01L027/12 |
Foreign Application Data
Date |
Code |
Application Number |
Apr 24, 2014 |
CN |
201410168661.5 |
Claims
1. An array substrate, comprising a gate metal layer, a gate
insulating layer, and a source/drain metal layer, the array
substrate further comprising: a plurality of first common electrode
lines arranged on an identical layer to the gate metal layer; a
first via hole arranged in the gate insulating layer and
corresponding to the first common electrode line; a source/drain
metal filling part arranged within the first via hole; a second via
hole arranged in communication with the first via hole; and a
transparent connection part, wherein the first common electrode
lines are, by means of the transparent connection part and the
source/drain metal filling part, in electrical connection with each
other through the second via hole.
2. The array substrate according to claim 1, further comprising: a
passivation layer, in which the second via hole is formed.
3. The array substrate according to claim 1, wherein the first
common electrode lines are arranged on an identical layer, and made
of an identical material, to the gate metal layer.
4. The array substrate according to claim 1, wherein the
source/drain metal filling part is arranged on an identical layer,
and made of an identical material, to the source/drain metal
layer.
5. The array substrate according to claim 1, further comprising: a
first transparent conductive layer, wherein the transparent
connection part is arranged on an identical layer, and made of an
identical material, to the first transparent conductive layer.
6. The array substrate according to claim 1, further comprising: a
plurality of second common electrode lines arranged on an identical
layer, and made of an identical material, to the source/drain metal
layer; and a source/drain metal connection part arranged within the
first via hole, wherein the second common electrode line is, by
means of the source/drain metal connection part, in electrical
connection with the first common electrode line through the first
via hole.
7. A method for manufacturing an array substrate, comprising: a
step of forming a plurality of first common electrode lines on a
gate metal layer; a step of forming a first via hole corresponding
to the first common electrode line on a gate insulating layer; a
step of forming a source/drain metal filling part within the first
via hole; a step of forming a second via hole in communication with
the first via hole; and a step of forming a transparent connection
part, wherein the first common electrode lines are, by means of the
transparent connection part and the source/drain metal filling
part, in electrical connection with each other through the second
via hole.
8. The method according to claim 7, wherein the first common
electrode line is formed together with the gate metal layer by a
one-time patterning process.
9. The method according to claim 7, wherein the source/drain metal
filling part is formed together with the source/drain metal layer
by a one-time patterning process.
10. The method according to claim 7, further comprising: a step of
forming a first transparent conductive layer, wherein the
transparent connection part is formed together with the first
transparent conductive layer by a one-time patterning process.
11. The method according to claim 7, comprising: forming the gate
metal layer and the plurality of first common electrode lines on a
substrate by a one-time patterning process; forming the gate
insulating layer on the substrate with the gate metal layer and the
first common electrode lines, and forming the first via hole
corresponding to the first common electrode line on the gate
insulating layer; forming an active layer on the substrate with the
gate insulating layer; forming the source/drain metal layer and the
source/drain metal filling part on the substrate with the active
layer by a one-time patterning process, the source/drain metal
filling part being arranged within the first via hole; forming a
passivation layer on the substrate with the source/drain metal
layer and the source/drain metal filling part, and forming the
second via hole in communication with the first via hole in the
passivation layer; and forming the first transparent conductive
layer and the transparent connection part on the substrate with the
passivation layer by a one-time patterning process, the first
common electrode lines being, by means of the transparent
connection part and the source/drain metal filling part, in
electrical connection with each other through the second via
hole.
12. The method according to claim 7, further comprising: a step of
forming a plurality of second common electrode lines and a
source/drain metal connection part, the source/drain metal
connection part being arranged within the first via hole, and the
second common electrode line being, by means of the source/drain
metal connection part, in connection with the first common
electrode line through the first via hole, wherein the second
common electrode lines and the source/drain metal connection part
are formed together with the source/drain metal layer by a one-time
patterning process.
13. A display device comprising the array substrate according to
claim 1.
14. The display device according to claim 13, the array substrate
further comprising: a passivation layer, in which the second via
hole is formed.
15. The display device according to claim 13, wherein the first
common electrode lines are arranged on an identical layer, and made
of an identical material, to the gate metal layer.
16. The display device according to claim 13, wherein the
source/drain metal filling part is arranged on an identical layer,
and made of an identical material, to the source/drain metal
layer.
17. The display device according to claim 13, the array substrate
further comprising: a first transparent conductive layer, wherein
the transparent connection part is arranged on an identical layer,
and made of an identical material, to the first transparent
conductive layer.
18. The display device according to claim 17, wherein the first
transparent conductive layer is a pixel electrode layer or a common
electrode layer.
19. The display device according to claim 13, the array substrate
further comprising: a plurality of second common electrode lines
arranged on an identical layer, and made of an identical material,
to the source/drain metal layer; and a source/drain metal
connection part arranged within the first via hole, wherein the
second common electrode line is, by means of the source/drain metal
connection part, in electrical connection with the first common
electrode line through the first via hole.
20. The array substrate according to claim 5, wherein the first
transparent conductive layer is a pixel electrode layer or a common
electrode layer.
Description
CROSS REFERENCE
[0001] The present application claims a priority of the Chinese
patent application No. 201410168661.5 filed on Apr. 24, 2014, the
disclosures of which are incorporated herein by reference in its
entirety.
TECHNICAL FIELD
[0002] The present invention relates to the field of display
technology, in particular to an array substrate, its manufacturing
method, and a display device.
BACKGROUND
[0003] Referring to FIG. 1, which is a schematic view showing a
thin film transistor array substrate in the prior art, the thin
film transistor array substrate comprises common electrodes 102,
gate lines 103, common electrode lines 104, and data lines 105. The
common electrode lines 104 are connected to the common electrodes
102, so as to reduce the resistance of the common electrodes
102.
[0004] A method for manufacturing the thin film transistor array
substrate with the above-mentioned structure comprises the
following steps:
[0005] S11: forming the common electrodes on a substrate;
[0006] S12: forming a gate metal layer and the common electrode
lines on the substrate with the common electrodes by a one-time
patterning process, the gate metal layer including gate electrodes
and gate lines;
[0007] S13: forming a gate insulating layer on the substrate with
the gate metal layer and the common electrode lines;
[0008] S14: forming an active layer on the substrate with the gate
insulating layer;
[0009] S15: forming a source/drain metal layer on the substrate
with the active layer, the source/drain metal layer including
source/drain electrodes and data lines;
[0010] S16: forming a passivation layer (PVX) on the substrate with
the source/drain metal layer, and a via hole penetrating through
the passivation layer and the gate insulating layer; and
[0011] S17: forming, on the substrate with the passivation layer, a
pixel electrode layer, a first connection part for connecting pixel
electrodes to the drain electrodes and a second connection part for
connecting the adjacent common electrode lines on the gate metal
layer.
[0012] Referring to FIG. 2, which is a schematic view showing a
connection mode of the common electrode lines on the gate metal
layer in the prior art. FIG. 2 includes: the substrate 101, the
common electrode lines 104 arranged on an identical layer to the
gate metal layer, the gate insulating layer 106, the passivation
layer 107, the via holes 108 in the passivation layer, and the
second connection part 109 arranged on an identical layer to the
pixel electrode layer.
[0013] As shown in FIG. 2, the via hole 108 formed in the
passivation layer 107 is relatively deep, so a rough surface will
occur at the via hole 108, and an alignment layer (PI) will diffuse
unevenly, thereby the image quality of a display panel will be
affected seriously. For example, such undesirable phenomena as
black Mura of the alignment layer at the periphery of the display
panel, and M24 defects (with a plurality of vertical, linear Mura,
blackening in the middle and whitening at both sides) and white
spots (with discontinuous, dot-like black points) within a pixel
region, will occur.
[0014] Hence, such problems as how to reduce the depth of the via
holes in the array substrate and improve the uneven diffusion of
the alignment layer urgently need to be addressed.
SUMMARY
[0015] An object of embodiments of the present invention is to
provide an array substrate, its manufacturing method, and a display
device, so as to reduce the depth of via holes in the array
substrate and improve the uneven diffusion of an alignment
layer.
[0016] In one aspect, an embodiment of the present invention
provides an array substrate, comprising:
[0017] a gate metal layer;
[0018] a gate insulating layer;
[0019] a source/drain metal layer;
[0020] a first common electrode line arranged on an identical layer
to the gate metal layer;
[0021] a first via hole arranged in the gate insulating layer and
corresponding to the first common electrode line;
[0022] a source/drain metal filling part arranged within the first
via hole;
[0023] a second via hole arranged in communication with the first
via hole; and
[0024] a transparent connection part.
[0025] The first common electrode lines are, by means of the
transparent connection part and the source/drain metal filling
part, in electrical connection with each other through the second
via hole.
[0026] The array substrate further comprises a passivation layer,
in which the second via hole is formed. The first common electrode
lines are arranged on an identical layer, and made of an identical
material, to the gate metal layer. The source/drain metal filling
part is arranged on an identical layer, and made of an identical
material, to the source/drain metal layer.
[0027] The array substrate further comprises a first transparent
conductive layer. The transparent connection part is arranged on an
identical layer, and made of an identical material, to the first
transparent conductive layer, and the first transparent conductive
layer is a pixel electrode layer or a common electrode layer.
[0028] The array substrate further comprises a second common
electrode line arranged on an identical layer, and made of an
identical material, to the source/drain metal layer, and a
source/drain metal connection part arranged within the first via
hole. The second common electrode line is, by means of the
source/drain metal connection part, in electrical connection with
the first common electrode line through the first via hole.
[0029] In another aspect, an embodiment of the present invention
further provides a method for manufacturing an array substrate,
comprising:
[0030] a step of forming a first common electrode line on a gate
metal layer;
[0031] a step of forming a first via hole corresponding to the
first common electrode line on a gate insulating layer;
[0032] a step of forming a source/drain metal filling part within
the first via hole;
[0033] a step of forming a second via hole in communication with
the first via hole; and
[0034] a step of forming a transparent connection part.
[0035] The first common electrode lines are, by means of the
transparent connection part and the source/drain metal filling
part, in electrical connection with each other through the second
via hole.
[0036] The first common electrode line is formed together with the
gate metal layer by a one-time patterning process. The source/drain
metal filling part is formed together with the source/drain metal
layer by a one-time patterning process.
[0037] The method further comprises a step of forming a first
transparent conductive layer. The transparent connection part is
formed together with the first transparent conductive layer by a
one-time patterning process.
[0038] To be specific, the method comprises:
[0039] forming the gate metal layer and a plurality of first common
electrode lines on a substrate by a one-time patterning
process;
[0040] forming the gate insulating layer on the substrate with the
gate metal layer and the first common electrode lines, and forming
the first via hole corresponding to the first common electrode line
on the gate insulating layer;
[0041] forming an active layer on the substrate with the gate
insulating layer;
[0042] forming the source/drain metal layer and the source/drain
metal filling part on the substrate with the active layer by a
one-time patterning process, the source/drain metal filling part
being arranged within the first via hole;
[0043] forming a passivation layer on the substrate with the
source/drain metal layer and the source/drain metal filling part,
and forming the second via hole in communication with the first via
hole in the passivation layer; and
[0044] forming the first transparent conductive layer and the
transparent connection part on the substrate with the passivation
layer by a one-time patterning process, the first common electrode
lines being, by means of the transparent connection part and the
source/drain metal filling part, in electrical connection with each
other through the second via hole.
[0045] The method further comprises a step of forming a second
common electrode line and a source/drain metal connection part, the
source/drain metal connection part being arranged within the first
via hole, and the second common electrode line being, by means of
the source/drain metal connection part, in connection with the
first common electrode line through the first via hole. The second
common electrode line and the source/drain metal connection part
are formed together with the source/drain metal layer by a one-time
patterning process.
[0046] In yet another aspect, an embodiment of the present
invention provides a display device comprising the above-mentioned
array substrate.
[0047] The present invention has the following advantages. The
source/drain metal filling part is filled in the via hole above the
first common electrode line arranged on the identical layer to the
gate metal layer. As a result, it is able to reduce the depth of
the via holes above the first common electrode line, thereby to
improve the smoothness of the array substrate, the uneven diffusion
of an alignment layer, and the display quality.
BRIEF DESCRIPTION OF THE DRAWINGS
[0048] FIG. 1 is a schematic view showing an array substrate in the
prior art;
[0049] FIG. 2 is a schematic view showing a connection mode of
common electrode lines arranged on an identical layer to a gate
metal layer in the prior art;
[0050] FIG. 3 is a schematic view showing an array substrate
according to one embodiment of the present invention;
[0051] FIG. 4 is another schematic view showing the array substrate
according to one embodiment of the present invention;
[0052] FIG. 5 is a schematic view showing a connection mode of a
common electrode line arranged on an identical layer to a gate line
and a common electrode line arranged on an identical layer to a
data line in the prior art; and
[0053] FIG. 6 is a schematic view showing a connection mode of a
common electrode line arranged on an identical layer to a gate line
and a common electrode line arranged on an identical layer to a
data line according to one embodiment of the present invention.
DETAILED DESCRIPTION
[0054] In order to make the objects, the technical solutions and
the advantages of the present invention more apparent, the present
invention will be described hereinafter in conjunction with the
drawings and the embodiments.
[0055] An array substrate comprises a gate metal layer, a gate
insulating layer, a source/drain metal layer, a first common
electrode line arranged on an identical layer to the gate metal
layer, a first via hole arranged in the gate insulating layer and
corresponding to the first common electrode line, a source/drain
metal filling part arranged within the first via hole, a second via
hole in communication with the first via hole, and a transparent
connection part. The first common electrode lines are, by means of
the transparent connection part and the source/drain metal filling
part, in electrical connection with each other through the second
via hole.
[0056] Through the above-mentioned structure, the source/drain
metal filling part is filled within the first via hole above the
first common electrode line. As a result, it is able to reduce the
depth of the via holes (including the first via holes and the
second via holes) above the first common electrode line, thereby to
improve the smoothness of the array substrate, the uneven diffusion
of an alignment layer, and the display quality.
[0057] In this embodiment, the gate metal layer includes gate lines
and gate electrodes, and the first common electrode line is
parallel to the gate line and connected to the common electrode, so
as to reduce the resistance thereof. The first common electrode
line is arranged on an identical layer, and made of an identical
material, to the gate metal layer.
[0058] The source/drain metal layer includes source/drain
electrodes and data lines, and the source/drain metal filling part
may be arranged on an identical layer, and made of an identical
material, to the source/drain metal layer.
[0059] The array substrate may further comprise a first transparent
conductive layer. The transparent connection part may be arranged
on an identical layer, and made of an identical material, to the
first transparent conductive layer, and the first transparent
conductive layer may be a pixel electrode layer or a common
electrode layer.
[0060] When the array substrate is of an ADS mode, it may further
comprise a second transparent conductive layer which may be
arranged on an identical layer to the gate metal layer.
[0061] Referring to FIG. 3, which is a schematic view showing the
array substrate according to one embodiment of the present
invention, the array substrate comprises a substrate 201, the first
common electrode line 204 arranged on an identical layer to the
gate metal layer, the gate insulating layer 205, the first via hole
206 arranged in the gate insulating layer 205 and corresponding to
the first common electrode line 204, the source/drain metal filling
part 207 arranged within the first via hole 206, a passivation
layer 201, the second via hole 211 arranged in the passivation
layer 210 and in communication with the first via hole 206, and the
transparent connection part 212.
[0062] The first common electrode lines 204 are, by means of the
transparent connection part 212 and the source/drain metal filling
part 207, in electrical connection with each other through the
second via hole 211.
[0063] It can therefore be seen that, as compared with the array
substrate in FIG. 2, the depth of the via holes above the first
common electrode line 204 in FIG. 3 is reduced significantly due to
the source/drain metal filling part 207 filled therein.
[0064] In this embodiment, the array substrate comprises the common
electrode line arranged on an identical layer to the gate metal
layer, and the common electrode line are connected to the common
electrode, so as to reduce the resistance thereof. In addition, the
array substrate may comprise the common electrode line arranged on
an identical layer to the source/drain metal layer simultaneously,
so it is able to further reduce the resistance of the common
electrode.
[0065] Referring to FIG. 4, which is another schematic view showing
the array substrate according to one embodiment of the present
invention, the array substrate comprises the common electrode 202,
the gate line 203, the first common electrode line arranged on an
identical layer to the gate line 203, the data line 208, and the
second common electrode line 209 arranged on an identical layer to
the data line 208. The first common electrode line 204 and the
second common electrode line 209 are connected to the common
electrode, so as to reduce the resistance thereof.
[0066] The second common electrode line 209 is parallel to the data
line 208, and arranged on an identical layer, and the second common
electrode line 209 may be made of an identical material, to the
data line 208.
[0067] In order to balance the voltage over the common electrode
lines, the second common electrode line 209 may be connected to the
first common electrode line 204.
[0068] Referring to FIG. 5, which is a schematic view showing a
connection mode of the common electrode line arranged on an
identical layer to the gate line and the common electrode line
arranged on an identical layer to the data line. FIG. 5 includes:
the substrate 101, the common electrode line 104 arranged on an
identical layer to the gate line, the gate insulating layer 106,
the active layer 110, the common electrode line 111 arranged on an
identical layer to the data line, the passivation layer 107, the
via holes 112 and 113 arranged in the passivation layer, and the
third connection part 109 on the transparent conductive layer. The
common electrode line 104 arranged on an identical layer to the
gate line is, by means of the third connection part 109, in
electrical connection to the common electrode line 111 arranged on
an identical layer to the data line through the via holes 113 and
112 in the passivation layer.
[0069] As can be seen from FIG. 5, there exists a problem that the
via hole 110 above the common electrode line 104 is also deep.
[0070] In order to overcome the above problem, referring to FIG. 6,
the array substrate may further comprise the source/drain metal
connection part 207 arranged within the first via hole. The second
common electrode line 209 arranged on an identical layer to the
source/drain metal layer may be, by means of the source/drain metal
connection part 207, in electrical connection with the first common
electrode line 204. In FIG. 6, 213 represents the active layer.
[0071] It can therefore be seen that, as compared with the array
substrate in FIG. 5, in the array substrate in FIG. 6, it is
unnecessary to provide the via hole for connecting the first common
electrode line and the second common electrode line after the
formation of the passivation layer. As a result, it is able to
improve the smoothness of the array substrate, the uneven diffusion
of the alignment layer, and the display quality.
[0072] The present invention further provides a method for
manufacturing an array substrate, comprising:
[0073] a step of forming a first common electrode line on a gate
metal layer;
[0074] a step of forming a first via hole corresponding to the
first common electrode line on a gate insulating layer;
[0075] a step of forming a source/drain metal filling part within
the first via hole;
[0076] a step of forming a second via hole in communication with
the first via hole; and
[0077] a step of forming a transparent connection part.
[0078] The first common electrode lines are, by means of the
transparent connection part and the source/drain metal filling
part, in electrical connection with each other through the second
via hole.
[0079] Through the above-mentioned method, the source/drain metal
filling part is filled within the first via hole above the first
common electrode line, so as to reduce the depth of the via holes
(including the first and second via holes) above the first common
electrode line, thereby to improve the smoothness of the array
substrate, the uneven diffusion of the alignment layer and the
display quality.
[0080] Alternatively, the first common electrode line is formed
together with the gate metal layer by a one-time patterning
process, and the source/drain metal filling part is formed together
with the source/drain metal layer by a one-time patterning
process.
[0081] Alternatively, the method further comprises a step of
forming a first transparent conductive layer. The transparent
connection part is formed together with the first transparent
conductive layer by a one-time patterning process.
[0082] The one-time patterning process includes steps of forming a
film, applying a photoresist, exposing and developing, etching, and
removing the remaining photoresist.
[0083] Alternatively, the method comprises the steps of:
[0084] S21: forming the gate metal layer and a plurality of first
common electrode lines on the substrate by a one-time patterning
process, the gate metal layer including the gate lines and the gate
electrodes;
[0085] S22: forming the gate insulating layer on the substrate with
the gate metal layer and the first common electrode line, and
forming the first via hole corresponding to the first common
electrode line on the gate insulating layer;
[0086] S23: forming the active layer on the substrate with the gate
insulating layer;
[0087] S24: forming the source/drain metal layer and the
source/drain metal filling part on the substrate with the active
layer by a one-time patterning process, the source/drain metal
filling part being arranged within the first via hole, the
source/drain metal layer including the data lines, source
electrodes and drain electrodes;
[0088] S25: forming the passivation layer on the substrate with the
source/drain metal layer and the source/drain metal filling part,
and forming the second via hole in communication with the first via
hole in the passivation layer; and
[0089] S26: forming the first transparent conductive layer and the
transparent connection part on the substrate with the passivation
layer by a one-time patterning process, the first common electrode
lines being, by means of the transparent connection part and the
source/drain metal filling part, in electrical connection with each
other through the second via hole.
[0090] In an existing method for manufacturing an array substrate,
a hole penetrating through a passivation layer and a gate
insulating layer is formed after the formation of a passivation
layer, and then a second connection part is formed in the hole so
as to connect common electrode lines arranged on an identical layer
to a gate metal layer, so the hole formed in this method is
relatively deep. However, in embodiments of the present invention,
the first via hole is provided in the gate insulating layer after
the gate insulating layer is formed, and when the source/drain
metal layer is formed, the source/drain metal connection part is
formed within the first via hole. Then, after the passivation layer
is formed, the second via hole in communication with the first via
hole is provided in the passivation layer. Because the source/drain
metal connection part us filled in the first via hole, the depth of
the via holes (including the first and second via holes) above the
first common electrode line will be reduced. As a result, it is
able to improve the smoothness of the array substrate, the uneven
diffusion of the alignment layer and the display quality.
[0091] In the above embodiments, the array substrate comprises the
first common electrode lines arranged on an identical layer to the
gate metal layer, and the first common electrode line is connected
to the common electrode, so as to reduce the resistance thereof. In
addition, the array substrate may comprise the second common
electrode lines arranged on an identical layer to the source/drain
metal layer, so as to further the resistance of the common
electrode.
[0092] In order to balance the voltage over the common electrode
lines, the second common electrode line arranged on an identical
layer to the source/drain metal layer may be connected to the first
common electrode line.
[0093] At this time, the method may further comprise a step of
forming the second common electrode line and the source/drain metal
connection part, the source/drain metal connection part being
arranged within the first via hole, and the second common electrode
line being, by means of the source/drain metal connection part, in
connection with the first common electrode line through the first
via hole.
[0094] The second common electrode line and the source/drain metal
connection part are formed together with the source drain metal
layer by a one-time patterning process.
[0095] Through the above-mentioned structure, it is unnecessary to
provide the via hole for connecting the first common electrode line
and the second common electrode line after the formation of the
passivation layer. As a result, it is able to improve the
smoothness of the array substrate, the uneven diffusion of the
alignment layer and the display quality.
[0096] In addition, when the array substrate is of an ADS mode, the
method may further comprise a step of forming the second
transparent conductive layer, and the second transparent conductive
layer may be arranged on an identical layer to the gate metal
layer.
[0097] The present invention further provides a display device
comprising the above-mentioned array substrate. The display device
may be any product or part having a display function, such as a
liquid crystal display panel, an electronic paper, an OLED panel, a
mobile phone, a tablet PC, a TV, a display, a laptop PC, a digital
photo frame and a navigator.
[0098] The above are merely the preferred embodiments of the
present invention. It should be appreciated that, a person skilled
in the art may make further modifications and improvements, without
departing from the principle of the present invention, and these
modifications and improvements shall also be considered as the
scope of the prevent invention.
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