U.S. patent application number 14/430872 was filed with the patent office on 2015-10-08 for method for separating regions of a semiconductor layer.
This patent application is currently assigned to OSRAM OPTO SEMICONDUCTORS GMBH. The applicant listed for this patent is OSRAM OPTO SEMICONDUCTORS GMBH. Invention is credited to Bernd Boehm, Lorenzo Zini.
Application Number | 20150287880 14/430872 |
Document ID | / |
Family ID | 49253298 |
Filed Date | 2015-10-08 |
United States Patent
Application |
20150287880 |
Kind Code |
A1 |
Zini; Lorenzo ; et
al. |
October 8, 2015 |
METHOD FOR SEPARATING REGIONS OF A SEMICONDUCTOR LAYER
Abstract
The invention relates to a method for separating regions of a
semiconductor layer and for introducing an outcoupling structure
into an upper side of the semiconductor layer, the outcoupling
structure being provided to couple light out of the semiconductor
layer. The upper side of the semiconductor layer is covered by a
mask having first openings for introducing the outcoupling
structure and at least a second opening, which is provided to
introduce a separating trench into the semiconductor layer. With
the aid of an etching method, the outcoupling structure is
introduced into the upper side of the semiconductor layer in the
region of the first openings and simultaneously a separating trench
passing through the semiconductor layer is introduced into the
semiconductor layer via the second opening, and a region of the
semiconductor layer is separated.
Inventors: |
Zini; Lorenzo; (Regensburg,
DE) ; Boehm; Bernd; (Obertraubling, DE) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
OSRAM OPTO SEMICONDUCTORS GMBH |
Regensburg |
|
DE |
|
|
Assignee: |
OSRAM OPTO SEMICONDUCTORS
GMBH
Regensburg
DE
|
Family ID: |
49253298 |
Appl. No.: |
14/430872 |
Filed: |
September 26, 2013 |
PCT Filed: |
September 26, 2013 |
PCT NO: |
PCT/EP2013/070042 |
371 Date: |
March 24, 2015 |
Current U.S.
Class: |
257/98 ;
438/29 |
Current CPC
Class: |
H01L 25/167 20130101;
H01L 2924/0002 20130101; H01L 2924/0002 20130101; H01L 33/20
20130101; H01L 33/0095 20130101; H01L 2924/00 20130101; H01L 33/24
20130101 |
International
Class: |
H01L 33/20 20060101
H01L033/20; H01L 33/22 20060101 H01L033/22; H01L 33/32 20060101
H01L033/32; H01L 33/00 20060101 H01L033/00 |
Foreign Application Data
Date |
Code |
Application Number |
Sep 27, 2012 |
DE |
10 2012 217 524.5 |
Nov 15, 2012 |
DE |
10 2012 220 909.3 |
Claims
1. A method for separating regions of a semiconductor layer having
an active zone for generating light and for introducing a
coupling-out structure into a top side of the semiconductor layer,
wherein the coupling-out structure is provided in order to couple
out light from the semiconductor layer, wherein the top side of the
semiconductor layer is covered with a mask, wherein the mask has
first openings for introducing the coupling-out structure, wherein
the mask has at least one second opening, wherein the second
opening is provided in order to introduce a separating trench
around a region of the semiconductor layer, wherein the
coupling-out structure is simultaneously introduced into the top
side of the semiconductor layer via the first openings with the aid
of an etching method, and wherein the second opening is chosen with
a size such that the separating trench is simultaneously introduced
in the region of the second opening over the entire thickness of
the semiconductor layer and a region of the semiconductor layer is
thus separated.
2. The method according to claim 1, wherein the separated region of
the semiconductor layer has a roughened central region surrounded
by a smooth, non-roughened edge.
3. The method according to claim 1, wherein a mask having a
substantially identical thickness in the region of the first and
the second openings is used.
4. The method according to claim 1, wherein a hard mask is used as
the mask.
5. The method according to claim 4, wherein the hard mask is a
resist mask.
6. The method according to claim 1, wherein a gaseous or liquid
etching medium is used as etchant.
7. The method according to claim 1, wherein the etching method is a
dry etching method.
8. The method according to claim 7, wherein a plasma is used in the
dry etching method.
9. The method according to claim 1, wherein the semiconductor layer
comprises an epitaxially applied layer at least at the top
side.
10. The method according to claim 1, wherein the semiconductor
layer comprises at least one GaN layer.
11. The method according to claim 1, wherein the mask is removed
and, in a further etching step, the previously covered regions of
the top side of the semiconductor layer are also provided with a
coupling-out structure by means of an etching method.
12. The method according to claim 1, wherein the separated region
of the semiconductor layer constitutes a semiconductor chip, in
particular an LED semiconductor chip.
13. An optoelectronic semiconductor chip having a semiconductor
layer having an active zone for generating light, having a
coupling-out structure for coupling out light having a
circumferential etched edge region, wherein the coupling-out
structure and the circumferential edge region were produced
according to a method according to any of the preceding claims.
14. The semiconductor chip according to claim 13, wherein a central
region has the roughened coupling-out structure, wherein the
central region is surrounded by a non-roughened edge region.
Description
[0001] The invention relates to a method for separating regions of
a semiconductor layer according to patent claim 1 and to an
optoelectronic semiconductor chip according to claim 8.
[0002] This patent application claims the priorities of German
patent applications 10 2012 217 524.5 and 10 2012 220 909.3, the
disclosure content of which is hereby incorporated by
reference.
[0003] DE 10 2011 010 503 A1 discloses providing a semiconductor
layer of an optoelectronic semiconductor chip with a mask and
introducing a coupling-out structure into a coupling-out side of
the semiconductor layer. Afterward, the mask is removed and, with
the aid of a second mask, likewise by means of an etching method,
the semiconductor layer is separated into individual regions from
which individual semiconductor chips are produced later.
[0004] The object of the invention is to provide a simpler and
faster method for separating regions of a semiconductor layer and
for introducing a coupling-out structure into the semiconductor
layer.
[0005] The object is achieved by means of the method according to
claim 1 and the semiconductor chip according to claim 10. Further
advantageous embodiments are specified in the dependent claims.
[0006] The method described has the advantage that, just with one
mask and in one method step, the coupling-out structure is
introduced into the semiconductor layer and at the same time at
least one region of the semiconductor layer is separated.
Consequently, the method described is simple, cost-effective and
fast to carry out. In contrast to the prior art, it is not
necessary to use a plurality of masks and/or to carry out a
plurality of etching methods. By way of example, an optoelectronic
semiconductor chip having a semiconductor layer for generating
light is produced with the aid of the method described. As a result
of the simultaneous roughening and the introduction of a trench
around the semiconductor chip, i.e. the mesa etching, a
non-roughened edge is obtained around the semiconductor chip. On
account of this sharp chip edge, the chip edge can be monitored
more easily for defects or contaminants in a concluding optical
inspection. The reliability of the optical inspection is increased
as a result.
[0007] In the prior art, the chip edge is also roughened and, as a
result, the chip edge appears very wavy in the inspection, such
that a clear definable boundary for the automatic inspection can be
recognized only with difficulty.
[0008] In one embodiment, the mask is applied in one method step
and thus has a uniform thickness.
[0009] In one development, a hard mask is used as the mask. The
hard mask is simple to produce, cost-effective and enables an
accurate structuring of the coupling-out structure and of the
separation of a region of the semiconductor layer.
[0010] In a further embodiment, the hard mask is a resist mask.
[0011] In a further embodiment, a gaseous or liquid etching medium
is used as etchant. The use of gaseous or liquid etching media
constitutes a known technology and enables the method to be carried
out cost-effectively.
[0012] In a further embodiment, the etching method is a dry etching
method.
[0013] In a further embodiment, a plasma is used in the dry etching
method. By way of example, this involves a Cl plasma.
[0014] The method described is particularly suitable for
introducing a coupling-out structure into an epitaxially applied
semiconductor layer. By way of example, the epitaxially grown
semiconductor layer can be embodied in the form of a gallium
nitride layer.
[0015] In a further embodiment, after the removal of the mask, a
further structuring step is carried out in order to provide the
previously covered regions of the semiconductor layer with a
coupling-out structure. The efficiency for coupling out light is
improved in this way.
[0016] The above-described properties, features and advantages of
this invention and the way in which they are achieved will become
clearer and more clearly understood in association with the
following description of the exemplary embodiments which are
explained in greater detail in association with the drawings,
wherein
[0017] FIG. 1 shows a first method step in a schematic
illustration,
[0018] FIG. 2 shows a second method step in a schematic
illustration,
[0019] FIG. 3 shows a schematic plan view of a semiconductor layer
with a mask, and
[0020] FIG. 4 shows a schematic illustration of semiconductor
chips.
[0021] FIG. 1 shows a schematic sectional view of a semiconductor
layer 2, on the top side of which a structured mask 1 is applied.
The semiconductor layer 2 can be arranged on a carrier 20, as
illustrated. The carrier 20 can for example comprise Ge, Si, GaAs,
AlN or SiN or consist of a corresponding layer composed of Ge, Si,
GaAs, AlN or SiN. The mask 1 is embodied in the form of a hard mask
for example. The hard mask can comprise silicon nitride or silicon
oxide, for example. Furthermore, the hard mask can also be a resist
mask. The structuring of the mask is performed by means of a
lithographic method using photoresist and corresponding etching
media. By way of example, an etching process using hydrofluoric
acid (HF) or an ammonia-buffered hydrofluoric acid can be carried
out for structuring or for removing the mask.
[0022] The semiconductor layer 2 comprises an upper first doped
semiconductor layer 3, for example. Adjoining the first
semiconductor layer 3, a second doped semiconductor layer 4 is
provided. The first semiconductor layer 3 can be negatively doped
and the second semiconductor layer 4 can be positively doped.
Equally, the first semiconductor layer 3 can be positively doped
and the second semiconductor layer 4 can be negatively doped. An
active zone 5 for generating light is formed in the boundary region
between the first and second semiconductor layers 3, 4. More
complex layer structures for the formation of an active zone 5 can
also be provided depending on the embodiment chosen. In particular,
the active zone 5 can be formed from a sequence of layers having
different dopings. The semiconductor layer 2 constitutes for
example an optoelectronic semiconductor layer, in particular an LED
semiconductor chip.
[0023] The structured mask 1 is applied on the first semiconductor
layer 3. Depending on the embodiment chosen, the semiconductor
layer 2 can also comprise other or additional layers, in particular
a mirror layer.
[0024] The mask 1 has first mask elements 10 and second mask
elements 12. A first opening 40 is in each case provided between a
first mask element 10 and a further first mask element 10, or
between a first mask element 10 and a second mask element 12. The
width of the first opening 40, i.e. a first distance 13 between a
first mask element 10 and a further first mask element 10 or
between a first mask element 10 and a second mask element 12, is in
a first range. By way of example, the first distances 13 between
two first mask elements 10 and a first mask element 10 and a second
mask element 12 are identical in magnitude. The second mask element
12 is arranged in each case circumferentially around a region of
the semiconductor layer 2. The second mask element 12 can have a
width of 10 .mu.m to 5 .mu.m, for example.
[0025] The first mask elements 10 preferably have the same width
along an x-axis illustrated in FIG. 1. The width of the second mask
element 12 along the x-axis is greater than the width of the first
mask elements 10 along the x-axis. A second opening 41 is provided
between two second mask elements 12. The second opening 41 has a
greater second width 14 than the first opening 40 in the x-axis.
Consequently, two adjacent second mask elements 12 have a greater
second distance 14 than two adjacent first mask elements 10.
Moreover, two adjacent second mask elements 12 have a greater
second distance 14 than a second mask element 12 from a first mask
element 10. The first distance 13 is thus less than the second
distance 14. The first distance 13 is defined in such a way that,
during an etching process, a desired cutout is introduced into the
semiconductor layer 2, which constitutes a part of an optical
coupling-out structure. The second distance 14 is chosen in such a
way that simultaneously during the etching process for introducing
the optical coupling-out structure a separating trench is
introduced into the semiconductor layer 2, said separating trench
extending through the entire thickness of the semiconductor layer
2. The second distance can be between 1.5 .mu.m and 2.5 .mu.m, for
example. The magnitude of the second distance 14 depends on the
thickness and the material of the semiconductor layer 2 and on the
etching method used, in particular on the etching medium. The
etching medium used can be for example KOH or phosphoric acid for a
wet-chemical etching method.
[0026] FIG. 2 shows the arrangement from FIG. 1 after the etching
process has been carried out. Between two first mask elements 10
and between a first mask element 10 and a second mask element 12,
in each case a cutout 15 is introduced into the semiconductor layer
2. Moreover, between two second mask elements 12, a separating
trench 16 is introduced into the semiconductor layer 2.
[0027] The cutouts 15 have boundary surfaces 17, 18 that support a
coupling-out of light generated by the active zone 5. The
separating trench 16 extends over the entire thickness of the
semiconductor layer 2. If the separating trench 16 is embodied as a
closed ring in the plane of the semiconductor layer 2, then a first
and a second region 19, 20 of the semiconductor layer 2 are
separated, as a result of the formation of the separating trench 16
i.e. a mesa etching is carried out. A region of the semiconductor
layer 2 is separated by the separating trench 16, as a result of
which a semiconductor chip such as e.g. an LED chip is separated.
In the case where a carrier 20 is provided, the individual regions
of the carrier 20 can be separated by a further etching method
and/or by a laser separating method along the separating trench 16.
An optoelectronic semiconductor chip, in particular an LED having a
region of the semiconductor layer can be produced after the
separation of the regions of the semiconductor layer.
[0028] The boundary surfaces 17, 18 arranged in an inclined manner
reduce that proportion of electromagnetic radiation which is
subjected to total internal reflection at the outer surface of the
layer 2. The boundary surfaces 17, 18 form an angle of for example
35.degree. to 75.degree., preferably 50.degree. to 70.degree., with
the plane of the layer 2. The concrete angle is predefined by a
crystal direction of the doped first semiconductor layer 3 and the
chemical removal. The etching depth, i.e. the depth of the cutouts
15, can be in the micrometers range. The cutouts 15 can have
pyramidal depressions. In the case of an etching depth in the
micrometers range and in the case of angles from above ranges of
values, the cutouts 15 have the shape of pyramids which are
particularly suitable for coupling out electromagnetic radiation in
the visible wavelength range, that is to say at wavelengths of
between 0.3 .mu.m and approximately 0.8 .mu.m. The diameter of a
base of the pyramidal cutouts 15 is likewise in the micrometers
range. The diameter is thus significantly greater than the
wavelength of the electromagnetic radiation. The base of the
pyramidal cutout has a hexagonal shape, in the case of the
embodiment of the first semiconductor layer 3 composed of gallium
nitride. After the removal of the mask 1, a plurality of separated
semiconductor chips are obtained, wherein a central region of each
semiconductor chip is roughened. The roughened central region is
surrounded by a smooth, non-roughened edge which was covered by the
second mask element 12 during the etching.
[0029] In a further embodiment, the mask 1 is subsequently removed
and the then uncovered regions of the surface of the first
semiconductor layer 3 are roughened by means of a further etching
step. The regions covered in the first etching step are thus also
provided with a coupling-out structure.
[0030] The semiconductor layer can be embodied as an epitaxially
grown layer structure having a plurality of layers. In this case,
the individual layers can consist of a III-V semiconductor
material. By way of example, a layer of the semiconductor layer can
be embodied on the basis of GaN, GaInN or AlN. Moreover, a layer
can be constructed on the basis of InGaAlN. InGaAlN-based layer
structures include, in particular, those in which the epitaxially
produced layer structure generally comprises a layer sequence
composed of different individual layers which contains at least one
individual layer comprising a material from the III-V compound
semiconductor material system InxAlyGa1-x-yN where 0<=x<=1,
0<=y<=1 and x+y<=1. The layer structure comprising at
least one active layer or an active region on the basis of InGaAlN
can emit for example electromagnetic radiation in an ultraviolet to
green wavelength range.
[0031] Alternatively or additionally, the layers of the
semiconductor layer can also be based on InGaAlP, that is to say
that the layer structure can comprise different individual layers,
at least one individual layer of which comprises a material from
the III-V compound semiconductor material system InxAlyGa1-x-yP
where 0<=x<=1, 0<=y<=1 and x+y<=1. The layer
structure comprising at least one active layer or an active region
on the basis of InGaAlP can for example preferably emit
electromagnetic radiation having one or more spectral components in
a green to red wavelength range.
[0032] Alternatively or additionally, the layers of the
semiconductor layer can also comprise other III-V compound
semiconductor material systems, for example an AlGaAs-based
material, or II-VI compound semiconductor material systems. In
particular, an active layer comprising an AlGaAs-based material can
be suitable for emitting electromagnetic radiation having one or
more spectral components in a red to infrared wavelength range. A
II-VI compound semiconductor material system can comprise at least
one element from the second main group, such as Be, Mg, Ca, Sr, for
example, and an element from the sixth main group, such as O, S,
Se, for example. In particular, a II-VI compound semiconductor
material system comprises a binary, ternary or quaternary compound
comprising at least one element from the second main group and at
least one element from the sixth main group. Such a binary, ternary
or quaternary compound can moreover comprise for example one or a
plurality of dopants and additional constituents. By way of
example, the II-VI compound semiconductor materials include ZnSe,
ZnTe, ZnO, ZnMgO, ZnS, CdS, ZnCdS, MgBeO.
[0033] FIG. 3 shows, in a schematic illustration, a plan view of a
semiconductor layer 2 provided with a mask 1. The mask 1 is
embodied in the form of a plurality of mask regions 30. Each mask
region 30 covers a region of the semiconductor layer 2 that is
separated by the subsequent etching process of the semiconductor
chip. In the exemplary embodiment illustrated, the mask 1 has
identical mask regions 30. Each mask region 30 is embodied
identically and has substantially a rectangular mask layer, in
which 12 first openings 40 are introduced in each case. In the
exemplary embodiment illustrated, in each case four first openings
40 are arranged alongside one another, three rows of four first
openings 40 being provided. In each case two mask regions 30 are
separated from one another by a second opening 41. The second
openings 41 form a right-angled strip pattern. In each case two
mask regions 30 are at a second distance 14 from one another both
in an x-axis and in a y-axis. The x-axis and the y-axis are
perpendicular to one another and are depicted schematically in FIG.
3. The first openings 40 have a first distance 13 in each case both
in the x-direction and in the y-direction. What is achieved by the
second openings 41 is that the semiconductor layer 2 is severed
between the mask regions 30 as a result of the formation of the
separating trench during the etching process carried out and
explained with reference to FIG. 2, i.e. individual semiconductor
chips of the semiconductor layer 2 are separated. Moreover, through
the first openings 40, corresponding pyramidal cutouts 15 are
introduced into the semiconductor layer 2, i.e. a central region of
the semiconductor chip is roughened. The central region is
surrounded by a smooth, non-roughened region. In FIG. 3, a
sectional line corresponding to the sectional illustration in FIG.
1 is depicted by A-A.
[0034] Depending on the embodiment chosen, the mask 1 can also have
a different structure, wherein the second distances are chosen
between adjacent mask regions in such a way that the semiconductor
layer 2 is provided with corresponding circumferential separating
trenches 16 passing through the entire semiconductor layer 2 during
the etching of the coupling-out structure.
[0035] FIG. 4 shows a schematic illustration of a carrier 20, on
which two semiconductor chips 21 were structured from a
semiconductor layer 2 in accordance with the method described. Each
semiconductor chip 21 has on a top side a central region 23
surrounded by an edge region 22. The central region 23 has the
coupling-out structure in the form of a cutout 15, which were
introduced into the top side of the semiconductor layer 2 with the
aid of the mask and the first openings 40. The central region 23 is
thus roughened. The edge region 22 was covered by a circumferential
edge region of the etching mask of the second mask element 12
during the etching process and is therefore not roughened. This has
the effect that the smooth edge region 22 can be distinguished
optically more easily from the roughened edge region 23.
Consequently, a sharp chip edge is identified optically, as a
result of which an optical inspection can easily be carried out
automatically. An optical inspection is necessary for example for
checking for defects or contaminants. Each semiconductor chip 21 is
surrounded by a circumferential, etched edge region 24. The edge
region 24 was etched simultaneously with the coupling-out
structure.
[0036] Although the invention has been more specifically
illustrated and described in detail by means of the preferred
exemplary embodiment, nevertheless the invention is not restricted
by the examples disclosed, and other variations can be derived
therefrom by the person skilled in the art, without departing from
the scope of protection of the invention.
LIST OF REFERENCE SIGNS
[0037] 1 Mask [0038] 2 Semiconductor layer [0039] 3 1.sup.st
semiconductor layer [0040] 4 2.sup.nd semiconductor layer [0041] 5
Active zone [0042] 10 1.sup.st mask element [0043] 12 2.sup.nd mask
element [0044] 13 1.sup.st distance [0045] 14 2.sup.nd distance
[0046] 15 Cutout [0047] 16 Separating trench [0048] 17 1.sup.st
boundary surface [0049] 18 2.sup.nd boundary surface [0050] 20
Carrier [0051] 21 Semiconductor chips [0052] 22 Edge region [0053]
23 Central region [0054] 24 Edge region [0055] 30 Mask region
[0056] 40 1.sup.st opening [0057] 41 2.sup.nd opening [0058] 42
Edge
* * * * *