U.S. patent application number 14/742809 was filed with the patent office on 2015-10-08 for memory and process sharing via input/output with virtualization.
The applicant listed for this patent is Moon J. Kim. Invention is credited to Moon J. Kim.
Application Number | 20150286578 14/742809 |
Document ID | / |
Family ID | 49326142 |
Filed Date | 2015-10-08 |
United States Patent
Application |
20150286578 |
Kind Code |
A1 |
Kim; Moon J. |
October 8, 2015 |
MEMORY AND PROCESS SHARING VIA INPUT/OUTPUT WITH VIRTUALIZATION
Abstract
Embodiments of the present invention provide an approach for
memory and process sharing via input/output (I/O) with
virtualization. Specifically, embodiments of the present invention
provide a circuit design/system in which multiple chipsets are
present that communicate with one another via a communications
channel. Each chipset generally comprises a processor coupled to a
memory unit. Moreover, each component has its own distinct/separate
power supply. Pursuant to a communication and/or command exchange
with a main controller, a processor of a particular chipset may
disengage a memory unit coupled thereto, and then access a memory
unit of another chipset (e.g., coupled to another processer in the
system). Among other things, such an inventive configuration
reduces memory leakage and enhances overall performance and/or
efficiency of the system.
Inventors: |
Kim; Moon J.; (Palo Alto,
CA) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Kim; Moon J. |
Palo Alto |
CA |
US |
|
|
Family ID: |
49326142 |
Appl. No.: |
14/742809 |
Filed: |
June 18, 2015 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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14507922 |
Oct 7, 2014 |
9081766 |
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14742809 |
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13444025 |
Apr 11, 2012 |
8898397 |
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14507922 |
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Current U.S.
Class: |
710/308 ;
711/147 |
Current CPC
Class: |
G06F 12/06 20130101;
Y02D 10/00 20180101; G06F 12/0284 20130101; G06F 13/28 20130101;
G06F 1/3287 20130101; G06F 2212/2532 20130101; G06F 2212/1028
20130101; G06F 13/4234 20130101; G06F 13/1694 20130101; Y02D 10/13
20180101; Y02D 10/151 20180101; G06F 12/1081 20130101; G06F 12/08
20130101; Y02D 10/171 20180101 |
International
Class: |
G06F 12/10 20060101
G06F012/10; G06F 13/16 20060101 G06F013/16; G06F 13/42 20060101
G06F013/42 |
Claims
1. A circuit having multiple chipsets, comprising: a first chipset
having a first processor and a first memory unit; a second chipset
having a second processor and a second memory unit; a third chipset
having a third processor and a third memory unit; and a
communication channel coupling the first chipset, the second
chipset, and the third chipset to each other; and wherein the first
processor is configured to disengage the first memory unit and to
access the third memory unit, and wherein the second processor is
configured to disengage the second memory unit based and to access
the third memory unit.
2. The circuit of claim 1, wherein the first processor, second
processor and the third processor are configured to communicate
with a main controller.
3. The circuit of claim 2, the first processor, second processor,
and the third processor each comprising: an input/output (I/O)
unit; a core unit coupled to the I/O unit; a cache unit coupled to
the core unit; and a memory controller coupled to the cache
unit.
4. The circuit of claim 3, the I/O unit having direct memory access
(DMA) for internal and external services.
5. The circuit of claim 3, the core unit being configured to
negotiate with the main controller to adjust a virtualized memory
size and perform memory mapping for the circuit.
6. The circuit of claim 1, wherein a multiple-to-one virtualized
mapping is performed between the first chipset, second chipset, and
the third chipset.
7. The circuit of claim 1, wherein the first processor, the first
memory unit, the second processor, and the second memory unit, and
the third processor, and the third memory each have a separate
power supply.
8. The circuit of claim 1, wherein the third memory unit is larger
than the second memory unit, and wherein the third memory unit is
larger than the first memory unit.
9. The circuit of claim 8, the first processor, the second
processor, and the third processor each being configured to poll
data within the circuit , and wherein the data is pertaining to at
least one of the following: memory type, memory size, communication
latency, data rate, available power, and memory utilization.
10. The circuit of claim 1, wherein the first processor serves as a
main controller.
11. A system having multiple chipsets, comprising: a main
controller; a first chipset in communication with the main
controller, the first chipset having a first processor coupled to a
first power supply and a first memory unit coupled to a second
power supply; a second chipset in communication with the main
controller, the second chipset having a second processor coupled to
a third power supply and a second memory unit coupled to a fourth
power supply; a third chipset in communication with the main
controller, the second chipset having a third processor coupled to
a fifth power supply and a third memory unit coupled to a sixth
power supply; and a communication channel coupling the first
chipset, the second chipset, and the third chipset to each other,
and wherein the first processor is configured to disengage the
first memory unit and to access the third memory unit, and wherein
the second processor is configured to disengage the second memory
unit and to access the third memory unit.
12. The system of claim 11, the first processor, second processor,
and third processor each comprising: an input/output (I/O) unit; a
core unit coupled to the I/O unit; a cache unit coupled to the core
unit; and a memory controller coupled to the cache unit.
13. The system of claim 12, the I/O unit having direct memory
access (DMA) for internal and external services.
14. The system of claim 12, the core unit being configured to
negotiate with the main controller to adjust a virtualized memory
size and perform memory mapping for the system.
15. The system of claim 11, wherein processes and memory addresses
are configured to perform a multiple-to-one virtualized mapping
between the first chipset, second chipset, and the third
chipset.
16. The system of claim 11, the first processor, second processor,
and third processor each being configured to poll data within the
system.
17. The system of claim 16, the data pertaining to at least one of
the following: memory type, memory size, communication latency,
data rate, available power, and memory utilization.
18. The system of claim 11, wherein the first processor comprises
the main controller.
19. The system of claim 11, wherein the third memory unit is larger
than the second memory unit, and wherein the third memory unit is
larger than the first memory unit.
20. The system of claim 19, wherein the first processor is
configured to transfer memory contents from the first memory unit
to the third memory unit prior to disengaging the first memory
unit, and wherein the second processor is configured to transfer
memory contents from the second memory unit to the third memory
unit prior to disengaging the second memory unit.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application is a continuation of commonly-owned and
co-pending application Ser. No. 14/507,922, filed Oct. 7, 2014,
which is a continuation application of commonly-owned application
Ser. No. 13/444,025, filed on Apr. 11, 2012 (now U.S. Pat. No.
8,898,397, issued Nov. 25, 2014).
FIELD OF THE INVENTION
[0002] In general, embodiments of the present invention provide a
multiple chipset circuit design. Specifically, embodiments of the
present invention provide an approach for memory and process
sharing via input/output (I/O) with virtualization.
BACKGROUND OF THE INVENTION
[0003] With increasing demands on functionality and performance as
well as improved fabrication techniques, newer generations of
processors and other integrated circuits have significantly higher
levels of integration than their predecessors. Additionally, in
some instances, different market segments may exist for compatible
versions of processors and other types of integrated circuits
having price and performance characteristics specific to a
particular market segment. However, given the complexity and
expense of designing a single version of a processor or other
integrated circuit having a large transistor count, it may be
impractical to separately design and manufacture a processor for
each of several different market segments.
[0004] These issues may be compounded as mobile devices become more
pervasive. Specifically, mobile systems typically suffer from power
leakage and consumption of their internal circuits. Currently,
low-power circuits are based on conventional design schemes.
Moreover, mobile multi-core processor and multi-chip systems
require a fundamentally different design approach for cores and
on-chip memories. Under such configurations, multiple chipsets may
be utilized in a single system, with each chipset requiring
separate memory resources. Such scattered memory resources may lead
to extensive power leakage.
[0005] Heretofore, attempts have been made in providing improved
circuitry. Such attempts include the following:
[0006] U.S. Patent Application Publication No. U.S. 2008/0244222
discloses a method for virtual processing.
[0007] U.S. Patent Application Publication No. U.S. 2005/0114586
discloses a method of performing memory mapped input/output
operations to an alternate address space.
[0008] U.S. Pat. No. 7,984,122 discloses an approach in which
processor core data regarding a client device is received from the
client device.
[0009] U.S. Pat. No. 7,873,776 discloses a multiple-core processor
with support for multiple processors.
[0010] U.S. Pat. No. 7,849,327 discloses a technique to improve the
performance of virtualized input/output (I/O) resources of a
microprocessor within a virtual machine environment.
[0011] U.S. Pat. No. 7,552,436 discloses a method of performing
memory mapped input/output operations to an alternate address
space.
[0012] Unfortunately, none of these approaches addresses issues
such as power leakage and/or consumption for multiple chipset
designs.
SUMMARY OF THE INVENTION
[0013] In general, embodiments of the present invention provide an
approach for memory and process sharing via input/output (I/O) with
virtualization. Specifically, embodiments of the present invention
provide a circuit design/system in which multiple chipsets are
present that communicate with one another via a communications
channel. Each chipset generally comprises a processor coupled to a
memory unit. Moreover, each component has its own distinct/separate
power supply. Pursuant to a communication and/or command exchange
with a main controller, a processor of a particular chipset may
disengage a memory unit coupled thereto, and then access a memory
unit of another chipset (e.g., coupled to another processer in the
system). Among other things, such an inventive configuration
reduces memory leakage and enhances overall performance and/or
efficiency of the system.
[0014] A first aspect of the present invention provides a circuit
having multiple chipsets, comprising: a first chipset having a
first processor and a first memory unit; a second chipset having a
second processor and a second memory unit; and a communication
channel coupling the first chipset to the second chipset, wherein
the first processor is configured to disengage the first memory
unit and to access the second memory unit, and wherein the second
processor is configured to disengage the second memory unit and to
access the first memory unit.
[0015] A second aspect of the present invention provides a system
having multiple chipsets, comprising: a main controller; a first
chipset in communication with the main controller, the first
chipset having a first processor coupled to a first power supply
and a first memory unit coupled to a second power supply; a second
chipset in communication with the main controller, the second
chipset having a second processor coupled to a third power supply
and a second memory unit coupled to a fourth power supply; and a
communication channel coupling the first chipset to the second
chipset, wherein the first processor is configured to disengage the
first memory unit and to access the second memory unit, and wherein
the second processor is configured to disengage the second memory
unit and to access the first memory unit.
[0016] A third aspect of the present invention provides a method
for virtualizing memory within a circuit, comprising: receiving a
request from a main controller on a first processor of a first
chipset; communicating a first set of data from the first processor
to the main controller in response to the request; receiving a
command on the first processor in response to the first set of
data; disengaging a first memory unit of the first chipset in
response to the command, the first memory unit being coupled to the
first processor; and accessing a second memory unit of a second
chipset from the first processor in response to the disengaging of
the first memory unit, the second memory unit being coupled to a
second processor within the second chipset.
BRIEF DESCRIPTION OF THE DRAWINGS
[0017] These and other features of this invention will be more
readily understood from the following detailed description of the
various aspects of the invention taken in conjunction with the
accompanying drawings in which:
[0018] FIG. 1 depicts a diagram of chipset system according to an
embodiment of the present invention.
[0019] FIG. 2 depicts a diagram of a chipset system in a first mode
according to an embodiment of the present invention.
[0020] FIG. 3 depicts a method flow diagram according to an
embodiment of the present invention.
[0021] FIG. 4 depicts another method flow diagram according to an
embodiment of the present invention.
[0022] FIG. 5 depicts a diagram of a processor according to an
embodiment of the present invention.
[0023] FIG. 6 depicts a diagram of a chipset in a second mode
according to an embodiment of the present invention.
[0024] FIG. 7 depicts a diagram of a chipset in a third mode
according to an embodiment of the present invention.
[0025] FIG. 8 depicts a diagram of multiple processors in
communication with one another according to an embodiment of the
present invention.
[0026] The drawings are not necessarily to scale. The drawings are
merely schematic representations, not intended to portray specific
parameters of the invention. The drawings are intended to depict
only typical embodiments of the invention, and therefore should not
be considered as limiting the scope of the invention. In the
drawings, like numbering represents like elements.
DETAILED DESCRIPTION
[0027] Illustrative embodiments will now be described more fully
herein with reference to the accompanying drawings, in which
exemplary embodiments are shown. This disclosure may, however, be
embodied in many different forms and should not be construed as
limited to the exemplary embodiments set forth herein. Rather,
these exemplary embodiments are provided so that this disclosure
will be thorough and complete and will fully convey the scope of
this disclosure to those skilled in the art. In the description,
details of well-known features and techniques may be omitted to
avoid unnecessarily obscuring the presented embodiments.
[0028] The terminology used herein is for the purpose of describing
particular embodiments only and is not intended to be limiting of
this disclosure. As used herein, the singular forms "a", "an", and
"the" are intended to include the plural forms as well, unless the
context clearly indicates otherwise. Furthermore, the use of the
terms "a", "an", etc., do not denote a limitation of quantity, but
rather denote the presence of at least one of the referenced items.
The term "set" is intended to mean a quantity of at least one. It
will be further understood that the terms "comprises" and/or
"comprising", or "includes" and/or "including", when used in this
specification, specify the presence of stated features, regions,
integers, steps, operations, elements, and/or components, but do
not preclude the presence or addition of one or more other
features, regions, integers, steps, operations, elements,
components, and/or groups thereof.
[0029] Embodiments of the present invention provide an approach for
memory and process sharing via input/output (I/O) with
virtualization. Specifically, embodiments of the present invention
provide a circuit design/system in which multiple chipsets are
present that communicate with one another via a communications
channel. Each chipset generally comprises a processor coupled to a
memory unit. Moreover, each component has its own distinct/separate
power supply. Pursuant to a communication and/or command exchange
with a main controller, a processor of a particular chipset may
disengage a memory unit coupled thereto, and then access a memory
unit of another chipset (e.g., coupled to another processer in the
system). Among other things, such an inventive configuration
reduces memory leakage and enhances overall performance and/or
efficiency of the system.
[0030] As used herein, virtualization of resources refers to any
number of techniques used to share computing resources among a
number of systems and/or software applications (collectively
referred to as "guest" software or entity). Virtualization
techniques can broadly be categorized as employing a "dedicated
policy", in which computing hardware is partitioned and each
partition is dedicated to particular guest software, or a "shared
policy", in which computing hardware is allocated to guest software
according to some arbitration scheme, such as a time-based
allocation algorithm (e.g., "time multiplexing").
[0031] Referring now to FIG. 1, a circuit system/design 10
according to an embodiment of the present invention is shown. As
depicted, system 10 comprises chipsets 14A-N each having a
processor 16A-N that is coupled to a memory unit 18A-N. Further,
each component (e.g., processors 16A-N and memory unit 18A-N) has
its own distinct/separate power supply 19A-N. As further shown, one
of the processors (in this case processor 16A) can function and/or
be assigned main controller duties. Alternatively, system 10 can
comprise a distinct main controller 12 with which processors 16A-N
communicate. Still yet, each chip set 16A-N may communicate with
one another via a communications channel, which can be any type of
communication channel now known or hereafter developed.
[0032] Under the embodiments of the present invention,
communication between chipsets 14A-N may include data pertaining to
memory resources, throughput, performance, power, etc. As indicated
above, a single chipset (e.g., 14A) may take a controller and/or
moderator role. Under such a configuration, the controller powers
on and off (e.g., engages and/or disengages) individual chipsets
and the memory associated therewith. Is general, processes and
memory addresses are virtualized between chipsets 14A-N. Moreover,
processing and memory resources may be delegated between chipsets
14A-N.
[0033] Under the embodiments of the present invention, memory
units/blocks 18A-N may be diverse in size, performance, and/or
power. Under previous approaches, power consumption and leakage
though all components were extensive. Under the present invention,
processors 16B-N report to controller 16A (or 12) about the
respective processor 16B-N, subsystem specifications, and statuses
through chip-to-chip or module-to-module communication channel,
such Hyper Transport (HT), Quick Path Interconnect (QPI), SPI
(Serial Peripheral Interface Bus), Peripheral Component
Interconnect Express (PCIe), etc. The main processor 16A polls data
and, in response, processors 16B-N report events and requirements
such as memory type, memory size, data latency, data rate, power,
utilization, etc.
[0034] Referring now to FIG. 2, system 10 is shown when system 10
is placed in a low-power mode for low-performance processing. As
depicted, memory unit 18B was disengaged (e.g., in response to
communication of data from processor 16B to main controller 18A (or
12), and receipt of a subsequent command from controller 16A (or
12) in response thereto. Under such an embodiment, processor 16B
would access the memory unit of another chipset such as memory unit
18N of chipset 14N. In general, main controller 16A (or 12)
determines which memory units to turn off based on power and
performance requirements versus processor and memory
specifications. Memory power supply is controlled by the processor
to which it is coupled. The processor receives command on memory
module power supply from the main controller. Processor power
supply is controlled by the main controller 16A or 12. In this
example, processor 16N virtualizes memory space in memory unit 18N
for processor 16B, and enables virtualized memory access. Before
memory unit 18B is disengaged/shutdown (e.g., by disengaging power
supply 19E), existing memory contents are transferred to memory
unit 18N. This configuration conserves power and prevents power
leakage.
[0035] Referring now to FIG. 3, a method flow diagram according to
an embodiment of the present invention is shown. As shown, in step
S1, the main controller sends a request for reports to the
processors in the system. In step S2, the processors send the
request reports to the main controller. In step S3, the main
controller determines whether an adjustment is needed. If not, the
process can return to step S1 for cycling. If so, the main
controller determines the system operation mode based on power and
performance requirements, and then in step S5, sends
directions/commands to the processors of the chipsets. In step S6,
the processors send responses to the main controller where they are
analyzed. In step S7, the main controller determines from the
responses whether a further adjustment is needed. If not, the
process returns to step S1. If so, the process returns to step S4.
If no, power off.
[0036] Referring now to FIG. 4, another method flow diagram
according to an embodiment of the present invention is shown. As
shown, in step T1, a processor receives a request from a main
controller. In step T2, the processor generates a status and
requirement report in response to the request. In step T3, the
processor sends the report to the main controller. In step T4, the
processor receives direction/commands from the main controller. In
step T5, the processor updates the setup according to the
direction/commands received from the main controller. In step T6,
it is determined (e.g., by the processor) whether an adjustment is
needed. If so, a corresponding request is sent to the main
controller in step T7, and the process returns to step T4.
[0037] Referring now to FIG. 5, a more detailed diagram of a
processor 16 according to an embodiment of the present invention is
shown. Specifically, FIG. 5 depicts the virtualization of memory
access hereunder. As shown, each processor 16 may comprise an I/O
22 coupled to a core unit 24 that is coupled to a cache unit 26.
The cache unit 26 is itself coupled to a memory controller 28 that
is coupled to a memory unit 18. Under this embodiment, I/O 22 may
have DMA (Direct Memory Access) for internal and external services.
Based on the main controller's direction, core unit 24 may
establish DMA and a virtualized address space table. When a memory
access request is received from another processor, I/O unit 22 may
directly access memory unit 18 and respond via I/O unit 22. Core
unit 24 further negotiates with the main controller to adjust
virtualized memory size and mapping. If necessary, core unit 24
transfers virtualized memory contents to a memory unit other than
the original memory unit.
[0038] Referring now to FIG. 6, an example of multiple
processors-to-one memory mapping in accordance with an embodiment
of the present invention is shown. As depicted, system 10 comprises
the components shown and described above in conjunction with FIG. 1
such as chipsets 14A-N, processors 16A-N, memory units 18A-N, power
supplies 19A-N, and optional main controller 12. In this example,
it is assumed that memory unit 18A is relatively larger than memory
units 18B-N and serves processors 16B-N through virtualization.
Under this embodiment, memory units 18B-N are shutdown/disengaged
after the multiple-to-one virtualized mapping is performed (e.g.,
by main controller 16A or 12).
[0039] FIG. 7 shows an example of one processor-to-multiple memory
mapping in accordance with an embodiment of the present invention.
As depicted, system 10 comprises the components shown and described
above in conjunction with FIG. 1 such as chipsets 14A-N, processors
16A-N, memory units 18A-N, power supplies 19A-N, and optional main
controller 12. Depending on the address space assigned, memory
virtualization may be divided between multiple processors and
memory units. When processor 16B's memory requirement grows beyond
a capacity available in processor 16A through memory
access/virtualization A, processor 16B extends to memory
access/virtualization B through processor 16N. Such access can be
shrunk to single or reduce number of access when requirement
decreases, with memory virtualization consolidation.
[0040] Referring now to FIG. 8, an example of a direct DMA-I/O-DMA
transaction with virtualization is depicted. As depicted,
processors 16A-N each comprise the components described above such
as I/O units 22A-N, core units 24A-N, cache units 26A-N, and memory
controllers 28A-N that communicate with memory units 18A-N. Under
this embodiment, core units 24A-N establish virtualized DMA in
accordance with the main controller's policy. Virtualized DMA may
then function directly without involvement of core units 24A-N.
Such a configuration reduces latency and participating cores'
memory-related loading.
[0041] As described hereinabove, the embodiments of the present
invention allow for main controller delegation. Under such
embodiments, main controller function is delegated to lower-power
consuming processors when needed. The power-performance budget of
the processors may be determined during system design. Under this
configuration, the main controller and operating system maintain
(among other things) the power and performance budget(s) and a list
of processors, as well as scenario and sequence of
power-performance trade-offs. Typically, the main controller
follows predetermined power saving policies.
[0042] The foregoing description of various aspects of the
invention has been presented for purposes of illustration and
description. It is not intended to be exhaustive or to limit the
invention to the precise form disclosed and, obviously, many
modifications and variations are possible. Such modifications and
variations that may be apparent to a person skilled in the art are
intended to be included within the scope of the invention as
defined by the accompanying claims.
* * * * *