U.S. patent application number 14/642602 was filed with the patent office on 2015-09-10 for method, apparatus and system for level shifting of common mode voltage from input to output for capacitive feedback transimpedance amplifier.
The applicant listed for this patent is Texas Instruments Incorporated. Invention is credited to Susan Ann Curtis, Karan Singh Jain, Harish Venkataraman.
Application Number | 20150256136 14/642602 |
Document ID | / |
Family ID | 54018420 |
Filed Date | 2015-09-10 |
United States Patent
Application |
20150256136 |
Kind Code |
A1 |
Jain; Karan Singh ; et
al. |
September 10, 2015 |
METHOD, APPARATUS AND SYSTEM FOR LEVEL SHIFTING OF COMMON MODE
VOLTAGE FROM INPUT TO OUTPUT FOR CAPACITIVE FEEDBACK TRANSIMPEDANCE
AMPLIFIER
Abstract
A circuit for a level shifting of common mode voltage. The
circuit includes a first amplifier, wherein the input of the first
amplifier is coupled to a voltage source and another input of the
first amplifier is coupled 2.5v, feedback resistor, R.sub.fb, and
feedback capacitor, C.sub.fb, connected coupled to the voltage
source, wherein other side of feedback resistor is coupled between
two resistors, R2 and R2', and wherein the other side of the
feedback capacitor is coupled between R2' and the output of the
first amplifier, R2 is connected to V.sub.bias from one side and
R.sub.fb and R2' from the other, R2' is connected to R.sub.fb and
R2 from one side and C.sub.fb and output of the first amplifier
from the other side, another resistor, R1, is connect to the output
of the first amplifier, C.sub.fb and R2' from one side and R1', yet
another resistor, and input of amp2 from the other, a second
amplifier, Amp2, is connected to the R1 and R1' at one input and
1.5v at the other input, and wherein the output of the second
amplifier is connected to R1', and R1' connects to one input of the
second amplifier and the output of the second amplifier.
Inventors: |
Jain; Karan Singh; (Dallas,
TX) ; Curtis; Susan Ann; (Allen, TX) ;
Venkataraman; Harish; (Wylie, TX) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Texas Instruments Incorporated |
Dallas |
TX |
US |
|
|
Family ID: |
54018420 |
Appl. No.: |
14/642602 |
Filed: |
March 9, 2015 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
61949391 |
Mar 7, 2014 |
|
|
|
Current U.S.
Class: |
345/174 ;
330/291 |
Current CPC
Class: |
H03F 2200/555 20130101;
H03F 2203/45101 20130101; G09G 5/003 20130101; H03F 2200/144
20130101; H03F 2203/45528 20130101; H03F 2203/45138 20130101; H03F
3/45475 20130101; H03F 2203/45526 20130101; G06F 3/047 20130101;
G09G 2300/0404 20130101; G06F 3/041 20130101; H03F 2200/135
20130101; H03F 1/0205 20130101 |
International
Class: |
H03F 3/04 20060101
H03F003/04; G06F 3/044 20060101 G06F003/044; G06F 3/047 20060101
G06F003/047; G09G 5/00 20060101 G09G005/00; H03F 1/02 20060101
H03F001/02; G01D 5/24 20060101 G01D005/24 |
Claims
1. A circuit for a level shifting of common mode voltage,
comprising: A first amplifier, wherein the input of the first
amplifier is coupled to a voltage source and another input of the
first amplifier is coupled 2.5v; feedback resistor, R.sub.fb, and
feedback capacitor, C.sub.fb, connected coupled to the voltage
source, wherein other side of feedback resistor is coupled between
two resistors, R2 and R2', and wherein the other side of the
feedback capacitor is coupled between R2' and the output of the
first amplifier; R2 is connected to V.sub.bias from one side and
R.sub.fb and R2' from the other; R2' is connected to R.sub.fb and
R2 from one side and C.sub.fb and output of the first amplifier
from the other side; another resistor, R1, is connect to the output
of the first amplifier, C.sub.fb and R2' from one side and R1', yet
another resistor, and input of amp2 from the other; a second
amplifier, Amp2, is connected to the R1 and R1' at one input and
1.5v at the other input, and wherein the output of the second
amplifier is connected to R1'; and R1' connects to one input of the
second amplifier and the output of the second amplifier.
2. The circuit for a level shifting of common mode voltage of claim
1, wherein R1 and R1' have the same value.
3. The circuit for a level shifting of common mode voltage of claim
1, wherein R2 and R2' have the same value.
4. The circuit for a level shifting of common mode voltage of claim
1, wherein the circuit is couple to a touch screen.
Description
CROSS REFERENCES TO RELATED APPLICATIONS
[0001] This application claims priority from U.S. Provisional
Patent Application No. 61/949,391 filed on Mar. 7, 2014, which is
hereby incorporated by reference in its entirety.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] Embodiments of the present invention generally relate to a
method, apparatus and system for touch screen processing. More
specifically, to a level shifting of common mode voltage from input
to output for capacitive feedback transimpedance amplifier
[0004] 2. Description of the Related Art
[0005] In a touch screen's amplifier configuration, the input of
amplifier is capacitive. However, the amplifier configuration is
required to be held at DC voltage different than output of the
amplifier. As a result, a lot of DC current is wasted, which is
inefficient, or another analog stage of amplifier is required,
which comes at a cost of adding another source of noise to the
system and its associated complexity.
[0006] Therefore, there is a need to hold the DC voltage without
the extra stage or wasted DC power.
SUMMARY OF THE INVENTION
[0007] Embodiments of the present invention relate to a circuit for
a level shifting of common mode voltage. The circuit includes a
first amplifier, wherein the input of the first amplifier is
coupled to a voltage source and another input of the first
amplifier is coupled 2.5v, feedback resistor, R.sub.fb, and
feedback capacitor, C.sub.fb, connected coupled to the voltage
source, wherein other side of feedback resistor is coupled between
two resistors, R2 and R2', and wherein the other side of the
feedback capacitor is coupled between R2' and the output of the
first amplifier, R2 is connected to V.sub.bias from one side and
R.sub.fb and R2' from the other, R2' is connected to R.sub.fb and
R2 from one side and C.sub.fb and output of the first amplifier
from the other side, another resistor, R1, is connect to the output
of the first amplifier, C.sub.fb and R2' from one side and R1', yet
another resistor, and input of amp2 from the other, a second
amplifier, Amp2, is connected to the R1 and R1' at one input and
1.5v at the other input, and wherein the output of the second
amplifier is connected to R1', and R1' connects to one input of the
second amplifier and the output of the second amplifier.
BRIEF DESCRIPTION OF THE DRAWINGS
[0008] So that the manner in which the above recited features of
the present invention can be understood in detail, a more
particular description of the invention, briefly summarized above,
may be had by reference to embodiments, some of which are
illustrated in the appended drawings. It is to be noted, however,
that the appended drawings illustrate only typical embodiments of
this invention and are therefore not to be considered limiting of
its scope, for the invention may admit to other equally effective
embodiments.
[0009] FIG. 1 is an embodiment of a circuit schematic of the prior
art;
[0010] FIG. 2 is an embodiment of a graph depicting performance of
the prior art;
[0011] FIG. 3 is an embodiment of a circuit schematic for a level
shifting of common mode voltage;
[0012] FIG. 4 is an embodiment of a graph depicting performance of
the circuit schematic of FIG. 3.
DETAILED DESCRIPTION
[0013] The proposed solution provides for a way of providing DC
feedback which leads the amplifier to think it is regulating the
same voltage both at the input and the output. The solution uses a
common mode DC shift current inside the feedback loop, which
maintains a different DC voltage at the output with respect to the
input of the amplifier.
[0014] FIG. 1 is an embodiment of a circuit schematic of the prior
art. The circuit comprises ample 1, amp 2, R.sub.fb, C.sub.fb, R1,
R1' and switch S1. The amp1 receives input from an input voltage
source and 2.5 v. The amp1 is connected in series with R.sub.fb and
C.sub.fb, where one lead of R.sub.fb and C.sub.fb is coupled to the
voltage source and the other is coupled to the output of amp1. V1
is measures at the output of amp 1 to be 2.5v. R1 is connect in
series at the output of amp 1. R1 is coupled to the output of amp1,
R1' on one side and R1' and S1 on the other. S1 is coupled to R1,
R1' and amp2 from one side and V.sub.bias one the other. R'1 is
connected to the input of amp 2, R1 and V.sub.bias; on the other
side, R1' is connected to the output of amp2. Amp2 has input
voltage of 1.5 v on one lead and R1, R1' and S1 on the other input
lead. The output of amp2 is v2. FIG. 2 is an embodiment of a graph
depicting performance of the prior art. The performance of this
circuit is shown in the graph of FIG. 2 and is defined as
follows:
TABLE-US-00001 Characteristics Performance DC Power Idc1 = (2.5 -
1.5)/R1 If R1 5 Kohms .fwdarw. Then Idc1 = 200 uA/Amplifier If R1
40 Kohms .fwdarw. Then Idc1 = 25 uA/Amplifier Output-Dynamic 4 Vpp
Range Area Impact Require Vbias generation can be used for all the
Amps
[0015] FIG. 3 is an embodiment of a circuit schematic for a level
shifting of common mode voltage. The circuit comprises ample 1, amp
2, R.sub.fb, C.sub.fb, R1, R1', R2, and R2'. One lead of amp1 is
coupled to the voltage source and the other to 2.5v. One lead of
R.sub.fb and C.sub.fb are connected to the voltage source. The
other side of R.sub.fb is connected between R2 and R2'. R2 is
connected to V.sub.bias from one side and R.sub.fb and R2' from the
other. R2' is connected to R.sub.fb and R2 from one side and
C.sub.fb and output of amp1 from the other side. R1 is connect to
the output of amp1, C.sub.fb and R2' from one side and R1' and
input of amp2 from the other. Amp2 is connected to the R1 and R1'
at one input, 1.5v at the other input and R1' at its output. R1'
connects to one input of amp2 and the output of amp2. FIG. 4 is an
embodiment of a graph depicting performance of the circuit
schematic of FIG. 3. The performance of this circuit is shown in
the graph of FIG. 4 and is defined as follows:
TABLE-US-00002 Characteristics Comments DC Power Idc1 = 0; Idc2 =
(2.5 - 1.5)/R2 ~= 100 Kohms Then Idc2 = 10 uA/Amplifier Output 2
Vpp Dynamic Range Area Impact Require Vbias generation can be used
for all the Amps
[0016] The improved solution between FIG. 1 and FIG. 3 does not
require an increase DC power or noise of system and is simple and
simple to implement.
[0017] While the foregoing is directed to embodiments of the
present invention, other and further embodiments of the invention
may be devised without departing from the basic scope thereof, and
the scope thereof is determined by the claims that follow.
* * * * *