U.S. patent application number 14/716968 was filed with the patent office on 2015-09-10 for semiconductor device.
This patent application is currently assigned to Kabushiki Kaisha Toshiba. The applicant listed for this patent is Kabushiki Kaisha Toshiba. Invention is credited to Kentaro IKEDA.
Application Number | 20150255453 14/716968 |
Document ID | / |
Family ID | 50193392 |
Filed Date | 2015-09-10 |
United States Patent
Application |
20150255453 |
Kind Code |
A1 |
IKEDA; Kentaro |
September 10, 2015 |
SEMICONDUCTOR DEVICE
Abstract
A semiconductor device according to one embodiment is provided
with a first metal substrate, a second metal substrate separated
from the first metal substrate, a normally-off transistor of a
silicon semiconductor provided on the first metal substrate, and a
normally-on transistor of a nitride semiconductor provided on the
second metal substrate.
Inventors: |
IKEDA; Kentaro; (Kanagawa,
JP) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Kabushiki Kaisha Toshiba |
Minato-ku |
|
JP |
|
|
Assignee: |
Kabushiki Kaisha Toshiba
Minato-ku
JP
|
Family ID: |
50193392 |
Appl. No.: |
14/716968 |
Filed: |
May 20, 2015 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
14206032 |
Mar 12, 2014 |
9087766 |
|
|
14716968 |
|
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Current U.S.
Class: |
257/106 ;
257/476 |
Current CPC
Class: |
H01L 23/49541 20130101;
H01L 23/495 20130101; H01L 2224/48464 20130101; H01L 2224/73265
20130101; H01L 2924/12032 20130101; H01L 2224/45144 20130101; H01L
2924/181 20130101; H01L 2224/32245 20130101; H01L 24/73 20130101;
H01L 29/872 20130101; H01L 2224/45147 20130101; H01L 2224/0603
20130101; H01L 23/49537 20130101; H01L 29/866 20130101; H01L
23/49575 20130101; H01L 2224/45124 20130101; H01L 2224/73265
20130101; H01L 2924/13091 20130101; H01L 23/62 20130101; H01L
2924/19107 20130101; H01L 27/0629 20130101; H01L 23/492 20130101;
H01L 2224/48247 20130101; H01L 2224/48195 20130101; H01L 2224/45144
20130101; H01L 2224/45147 20130101; H01L 23/49562 20130101; H01L
2224/48247 20130101; H01L 2224/32245 20130101; H01L 2924/00
20130101; H01L 2924/00014 20130101; H01L 25/18 20130101; H01L
2924/13091 20130101; H01L 23/49568 20130101; H01L 2924/00012
20130101; H01L 29/7786 20130101; H01L 2924/12032 20130101; H01L
2224/45124 20130101; H01L 2224/48137 20130101; H01L 2924/181
20130101; H01L 2924/00014 20130101; H01L 2924/00012 20130101; H01L
2924/00 20130101; H01L 2924/00014 20130101 |
International
Class: |
H01L 27/06 20060101
H01L027/06; H01L 23/492 20060101 H01L023/492; H01L 29/872 20060101
H01L029/872; H01L 29/778 20060101 H01L029/778; H01L 29/866 20060101
H01L029/866 |
Foreign Application Data
Date |
Code |
Application Number |
Jun 25, 2013 |
JP |
2013-133108 |
Claims
1. A semiconductor device comprising: a first metal substrate; a
second metal substrate separated from the first metal substrate; a
normally-off transistor formed of silicon semiconductor and
provided on the first metal substrate; and a normally-on transistor
formed of nitride semiconductor and provided on the second metal
substrate.
2. The device according to claim 1, further comprising a diode
provided on the first metal substrate.
3. The device according to claim 2, wherein a distance between the
diode and the normally-on transistor is longer than a distance
between the normally-off transistor and the normally-on
transistor.
4. The device according to claim 2, wherein the diode is a zener
diode.
5. The device according to claim 2, wherein the diode is a
schottky-barrier diode.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application is a division of and claims the benefit of
priority under 35 U.S.C. .sctn.120 from U.S. Ser. No. 14/206,032
filed Mar. 12, 2014, and claims the benefit of priority under 35
U.S.C. .sctn.119 from Japanese Patent Application No. 2013-133108
filed Jun. 25, 2013, the entire contents of each of which are
incorporated herein by reference.
FIELD
[0002] Embodiments described herein relate generally to a
semiconductor device.
BACKGROUND
[0003] A group III nitride, for example, GaN (gallium nitride)
based nitride semiconductor is expected as a material for a
next-generation power semiconductor device. The GaN based
semiconductor device has a wide band gap compared to Si (silicon),
and can realize a high withstand voltage and a low loss compared to
a Si semiconductor device.
[0004] A GaN based transistor is generally applied with a high
electron mobility transistor (HEMT) structure in which a
two-dimensional electronic gas (2DEG) is used as a carrier. A
general HEMT is a normally-on transistor which comes to be a
conduction state even when a voltage is not applied to a gate.
There is a problem in that it is difficult to realize a
normally-off transistor which does not come to be the conduction
state as long as the voltage is not applied to the gate.
[0005] In power circuits handling large power such as several
hundreds of voltage to a thousand voltage, a normally-off operation
is required for the safety. Therefore, there is proposed a circuit
configuration in which a normally-on transistor of a nitride
semiconductor and a normally-off transistor of a silicon
semiconductor are connected in cascode on the same substrate to
realize a normally-off operation.
[0006] However, in such a circuit configuration, the heat generated
by the normally-on transistor which consumes a large amount of
power affects the operation of other elements. Therefore, there is
a concern that the characteristics of the circuit may vary.
BRIEF DESCRIPTION OF THE DRAWINGS
[0007] FIG. 1 is a cross-sectional view schematically illustrating
a semiconductor device according to a first embodiment;
[0008] FIG. 2 is a top view schematically illustrating the
semiconductor device according to the first embodiment, in which a
mold resin is removed;
[0009] FIG. 3 is a circuit diagram illustrating a semiconductor
device according to the first embodiment;
[0010] FIG. 4 is a top view schematically illustrating a
semiconductor device according to a second embodiment, in which a
mold resin is removed;
[0011] FIG. 5 is a top view schematically illustrating a
semiconductor device according to a third embodiment, in which a
mold resin is removed;
[0012] FIG. 6 is a circuit diagram illustrating the semiconductor
device according to the third embodiment;
[0013] FIG. 7 is a top view schematically illustrating a
semiconductor device according to a fourth embodiment, in which a
mold resin is removed; and
[0014] FIG. 8 is a circuit diagram illustrating a semiconductor
device according to the fourth embodiment.
DETAILED DESCRIPTION
[0015] A semiconductor device according to an embodiment is
provided with a first metal substrate, a second metal substrate
separated from the first metal substrate, a normally-off transistor
of a silicon semiconductor provided on the first metal substrate,
and a normally-on transistor of a nitride semiconductor provided on
the second metal substrate.
[0016] Hereinafter, embodiments will be described with reference to
the drawings. Further, in the following descriptions, the same
members will be denoted with the same reference numerals, and
members once described will not be described again
appropriately.
[0017] In addition, in the specification, the semiconductor device
means a power module in which a plurality of elements such as
discrete semiconductors are assembled or an intelligent power
module in which the plurality of elements such as the discrete
semiconductors are assembled with driving circuits for driving
these elements and with self-protecting functions, or includes all
the systems which are provided with the power modules and the
intelligent power modules.
[0018] In addition, in the specification, the normally-on
transistor means a transistor in which a channel comes to be in an
on state and current flows between the source and the drain when
the source and the gate are at the same potential. In addition, in
the specification, the normally-off transistor means a transistor
in which the channel comes to be in an off state and the current
does not flow between the source and the drain when the source and
the gate is at the same potential.
[0019] In addition, in the specification, the nitride semiconductor
is a semiconductor which uses nitride as a group V element among
the III-V semiconductors. For example, the nitride semiconductor is
a semiconductor which contains GaN (gallium nitride), AlN (aluminum
nitride), InN (indium nitride), or an intermediate composition
thereof. In addition, a GaN based semiconductor is a generic term
referring to the III-V semiconductors including Ga (gallium) as a
group III element among the nitride semiconductors.
First Embodiment
[0020] A semiconductor device according to the embodiment is
provided with a first metal substrate, a second metal substrate
separated from the first metal substrate, a normally-off transistor
of a silicon semiconductor provided on the first metal substrate,
and a normally-on transistor of a nitride semiconductor provided on
the second metal substrate.
[0021] FIG. 1 is a cross-sectional view schematically illustrating
the semiconductor device according to the embodiment. FIG. 2 is a
top view schematically illustrating the semiconductor device
according to the embodiment, in which a mold resin is removed. FIG.
1 is a cross sectional view taken along line A-A of FIG. 2. FIG. 3
is a circuit diagram illustrating the semiconductor device
according to the embodiment.
[0022] The semiconductor device according to the embodiment is
provided with a normally-off transistor 10 formed using the silicon
semiconductor and a normally-on transistor 20 formed using the
nitride semiconductor. The semiconductor device according to the
embodiment is, for example, a power module having a rated voltage
of 600 V or 1200 V.
[0023] As illustrated in FIG. 3, the semiconductor device according
to the embodiment is configured to include the normally-off
transistor 10 and the normally-on transistor 20 which are connected
in series to form the power module. The normally-off transistor 10
is, for example, a vertical metal oxide semiconductor field effect
transistor (MOSFET) formed of Si (silicon). In addition, the
normally-on transistor 20 is, for example, a horizontal HEMT formed
of GaN (gallium nitride) based semiconductor. The normally-on
transistor 20 is provided with a gate insulating film.
[0024] The normally-off transistor 10 has a low withstand voltage
compared to the normally-on transistor 20. The withstand voltage of
the normally-off transistor 10 is, for example, within 10 to 30 V.
In addition, the withstand voltage of the normally-on transistor 20
is, for example, within 600 to 1200 V.
[0025] The semiconductor device is provided with a source terminal
100, a drain terminal 200, and a gate terminal 300. Then, the
normally-off transistor 10 includes a first source 11 connected to
the source terminal 100, a first drain 12, and a first gate 13
connected to the gate terminal 300. In addition, the normally-on
transistor 20 includes a second source 21 connected to the first
drain 12, a second drain 22 connected to the drain terminal 200,
and a second gate 23 connected to the source terminal 100.
[0026] With such a configuration described above, the semiconductor
device according to the embodiment serves as a normally-off
transistor which is provided with the source terminal 100, the
drain terminal 200, and the gate terminal 300.
[0027] As illustrated in FIGS. 1 and 2, the semiconductor device
according to the embodiment is provided with a first metal
substrate 95 and a second metal substrate 96 physically separated
from the first metal substrate 95. The first metal substrate 95 and
the second metal substrate 96 are physically separated from each
other with a material, which has a thermal conductivity lower than
those of the first metal substrate 95 and the second metal
substrate 96, interposed therebetween. The first and second metal
substrates 95 and 96 are, for example, copper alloys.
[0028] Then, the normally-off transistor 10 is provided on the
first metal substrate 95, and the normally-on transistor 20 is
provided on the second metal substrate 96. The normally-off
transistor 10 is, for example, bonded on the first metal substrate
95 using a conductive adhesive such as silver paste. In addition,
the normally-on transistor 20 is, for example, bonded on the second
metal substrate 96 using a conductive adhesive such as silver
paste.
[0029] An electrode pad 111 of the first source 11 and an electrode
pad 113 of the first gate 13 are provided on the upper face of the
normally-off transistor 10. An electrode of the first drain 12 is
provided on the lower face of the normally-off transistor 10.
[0030] In addition, an electrode pad 121 of the second source 21,
an electrode pad 122 of the second drain 22, and an electrode pad
123 of the second gate 23 are provided on the upper face of the
normally-on transistor 20.
[0031] Then, a source lead 91, a drain lead 92, and a gate lead 93
are further provided. The source lead 91, the drain lead 92, and
the gate lead 93 are, for example, copper alloys.
[0032] Then, the source lead 91 is electrically connected to the
electrode pad 111 of the first source 11, and the drain lead 92 is
electrically connected to the electrode pad 122 of the second drain
22. The gate lead 93 is electrically connected to the electrode pad
113 of the first gate 13.
[0033] Then, the electrode pad 111 of the first source 11 is
electrically connected to the electrode pad 123 of the second gate
23. In addition, the first metal substrate 95 is electrically
connected to the second metal substrate 96. Further, the second
metal substrate 96 is connected to the electrode pad 121 of the
second source 21.
[0034] The above-mentioned connections are, for example, made by
wire bonding using a bonding wire 99. As the bonding wire 99, for
example, materials such as gold (Au), copper (Cu), and aluminum
(Al) are used.
[0035] Further, the electrode of the first drain 12 disposed on the
lower face of the normally-off transistor 10 is electrically
connected to the first metal substrate 95 using, for example, a
conductive adhesive such as silver paste.
[0036] The normally-off transistor 10 and the normally-on
transistor 20 are sealed with a mold resin 98 into one body. The
mold resin 98 has a thermal conductivity lower than those of the
first metal substrate 95 and the second metal substrate 96. The
mold resin 98 is, for example, an epoxy resin.
[0037] Further, the embodiment has been described as an example in
which the normally-off transistor 10 and the normally-on transistor
20 are sealed with the mold resin 98. However, the normally-off
transistor 10 and the normally-on transistor 20 may not be
necessarily sealed with the mold resin 98. For example, the first
metal substrate 95 and the second metal substrate 96 are provided
on the same ceramic substrate, and the normally-off transistor 10
and the normally-on transistor 20 may be configured to be filled
with the air therebetween.
[0038] At the time when the power module according to the
embodiment operates, a heating value significantly increases in the
normally-on transistor 20 of the nitride semiconductor having large
power consumption more than in the normally-off transistor 10.
Then, the normally-off transistor 10 of the silicon semiconductor
has less resistance against heat compared to the normally-on
transistor 20 of the nitride semiconductor. In other words, an
increase in the leakage current caused by the temperature rise and
a variation in the threshold are remarkable in the normally-off
transistor 10 compared to the normally-on transistor 20. In
addition, also a temperature resulting in the element destruction
is low compared to the normally-on transistor 20.
[0039] In the embodiment, the first metal substrate 95 to be
mounted by the normally-off transistor 10 and the second metal
substrate 96 to be mounted by the normally-on transistor 20 are
physically separated through a material having a low thermal
conductivity. With this configuration, the normally-off transistor
10 is thermally separated from the normally-on transistor 20, so
that a thermal influence due to the heat generated by the
normally-on transistor 20 is suppressed from affecting the
normally-off transistor 10. Therefore, the semiconductor device
which has less characteristics variation and high reliability is
realized.
[0040] In the embodiment, the thermal conductivity of the second
metal substrate 96 is desirably smaller than that of the first
metal substrate 95. With this configuration, the heat of the
normally-on transistor 20 is suppressed from being transferred into
the second metal substrate 96. Therefore, it is possible to further
suppress the thermal influence due to the heat generated by the
normally-on transistor 20 from affecting the normally-off
transistor 10.
[0041] In addition, in the embodiment, the first metal substrate 95
is electrically connected to the first drain 12, and the second
metal substrate 96 is electrically connected to the second source
21. In other words, the second metal substrate 96 and the second
source 21 have the same potential. Then, the second metal substrate
96 is disposed over an area from the second source 21 to the second
drain 22 on the lower face of the normally-on transistor 20.
[0042] Therefore, the second metal substrate 96 serves as a source
field plate of the normally-on transistor 20. The source field
plate weakens the electric field in a source region and a drain
region between the second source 21 and the second drain 22, and
suppresses current collapse.
[0043] As described above, with the semiconductor device according
to the embodiment, the semiconductor device which has less
characteristics variation and high reliability is realized by
thermally separating the normally-off transistor 10 from the
normally-on transistor 20. In addition, with the semiconductor
device according to the embodiment, the current collapse is
suppressed by making the second metal substrate 96 serve as the
source field plate, and thus the semiconductor device having high
reliability is realized.
Second Embodiment
[0044] A semiconductor device according to the embodiment is
different from the first embodiment in that the second metal
substrate is electrically connected to the second drain. A
redundant description overlapping the first embodiment will be
omitted.
[0045] FIG. 4 is a top view schematically illustrating the
semiconductor device according to the embodiment, in which a mold
resin is removed. The circuit configuration according to the
embodiment is similar to the circuit configuration according to the
first embodiment illustrated in FIG. 3.
[0046] In the embodiment, the source lead 91 is electrically
connected to the electrode pad 111 of the first source 11, and the
drain lead 92 is electrically connected to the second metal
substrate 96. The gate lead 93 is electrically connected to the
electrode pad 113 of the first gate 13.
[0047] Then, the electrode pad 111 of the first source 11 is
electrically connected to the electrode pad 123 of the second gate
23. In addition, the first metal substrate 95 is electrically
connected to the electrode pad 121 of the second source 21.
Further, the electrode pad 122 of the second drain 22 is
electrically connected to the second metal substrate 96.
[0048] Further, the electrode of the first drain 12 disposed on the
lower face of the normally-off transistor 10 is electrically
connected to the first metal substrate 95 using, for example, a
conductive adhesive such as silver paste.
[0049] In the embodiment, similarly to the first embodiment, the
normally-off transistor 10 is thermally separated from the
normally-on transistor 20, so that the thermal influence due to the
heat generated by the normally-on transistor 20 is suppressed from
affecting the normally-off transistor 10. Therefore, the
semiconductor device which has less characteristics variation and
high reliability is realized.
[0050] In addition, in the embodiment, unlike the first embodiment,
the second metal substrate 96 has no electrical connection directly
to the first drain 12 and the second source 21. In other words, the
second metal substrate 96 is not electrically connected directly to
the normally-off transistor 10 and a connection portion of the
normally-on transistor 20 (hereinafter, simply referred to as a
connection portion).
[0051] There is a concern that the second metal substrate 96 acts
as an antenna, which is parasitic on the semiconductor device
during a period when the semiconductor device operates. In other
words, there is a concern that the second metal substrate 96
gathers noises outside the semiconductor device to cause an
unstable operation of the semiconductor device. On the contrary,
there is a concern that the second metal substrate 96 transmits
noise from the semiconductor device to the outside of the
semiconductor device to cause an adverse influence on elements
outside the semiconductor device. Therefore, in particular, there
is a strong concern that the operations of the elements become
unstable when the second metal substrate 96 is connected to the
connection portion and the like which are not fixed in
potential.
[0052] In the embodiment, the second metal substrate 96 is fixed at
a drain voltage through the connection to the drain lead 92.
Therefore, it is suppressed that the second metal substrate 96 acts
as an antenna to affect the operation of the semiconductor device
itself or the elements outside the semiconductor device.
[0053] In general, the second metal substrate 96 on which the
normally-on transistor 20 having a large heating value is mounted
is connected to a large-area heat sink or the like compared to the
first metal substrate 95. For this reason, the surface area of the
conductor acting as a parasitic antenna is easily increased.
Therefore, fixing the potential of the second metal substrate 96
having a large surface area to the drain voltage is effective for
the noise suppression.
[0054] Further, as described in the embodiment, the potentials of
the first metal substrate 95 and the second metal substrate 96 can
be differently set by physically separating the first metal
substrate 95 from the second metal substrate 96.
[0055] As described above, with the semiconductor device according
to the embodiment, the semiconductor device which has less
characteristics variation and high reliability is realized by
thermally separating the normally-off transistor 10 from the
normally-on transistor 20. In addition, the semiconductor device
which operates stably and does not make an adverse influence on the
surrounding elements is realized by fixing the second metal
substrate 96 at the drain voltage.
Third Embodiment
[0056] A semiconductor device according to the embodiment is
different from the first embodiment in that there is further
provided a diode on the first metal substrate. A redundant
description overlapping the first embodiment will be omitted.
[0057] The diode according to the embodiment is a zener diode.
[0058] FIG. 5 is a top view schematically illustrating the
semiconductor device according to the embodiment, in which a mold
resin is removed. FIG. 6 is a circuit diagram illustrating the
semiconductor device according to the embodiment. The semiconductor
device according to the embodiment is provided with, for example, a
zener diode 30 made of the silicon semiconductor in parallel with
the normally-off transistor 10.
[0059] As illustrated in FIG. 6, the zener diode 30 includes a
first anode 31 and a first cathode 32. The first anode 31 is
connected to the first source 11. In addition, the first cathode 32
is connected to the first drain 12 and the second source 21.
[0060] Herein, a zener voltage of the zener diode 30 is set to be
lower than an avalanche breakdown voltage of the normally-off
transistor 10. In addition, the zener voltage is set to be lower
than a withstand voltage of the gate insulating film of the
normally-on transistor 20. With this configuration, the withstand
voltage between the first source 11 and the first drain 12 at the
time of turning off the normally-off transistor 10 becomes lower
than the withstand voltage between the second source 21 and the
second gate 23 of the normally-on transistor 20.
[0061] As illustrated in FIG. 5, an electrode pad 131 of the first
anode 31 is provided on the upper face of the zener diode 30. Then,
the electrode pad 111 of the first source 11 and the electrode pad
131 of the first anode 31 are electrically connected, for example,
through the bonding wire 99.
[0062] In addition, an electrode of the first cathode 32 is
provided on the lower face of the zener diode 30. Then, the lower
face of the zener diode 30 is electrically connected to the first
metal substrate 95 using, for example, a conductive adhesive such
as silver paste.
[0063] Then, a distance between the zener diode 30 and the
normally-on transistor 20 is longer than that between the
normally-off transistor 10 and the normally-on transistor 20.
Herein, a distance between two elements means the shortest distance
between the two elements.
[0064] In a circuit configuration in which the normally-off
transistor 10 and the normally-on transistor 20 are connected in
series, there is a concern that an overvoltage is generated during
the operation in a connection portion between the normally-off
transistor 10 and the normally-on transistor 20. For example, when
the semiconductor device transitions from the on state to the off
state, a high voltage applied between the source terminal 100 and
the drain terminal 200 is divided at the ratio of parasitic
capacitances of the normally-off transistor 10 and the normally-on
transistor 20, so that the overvoltage may be generated.
Alternatively, when the semiconductor device is turned off, the
high voltage applied between the source terminal 100 and the drain
terminal 200 is divided at the ratio of leakage currents of the
normally-off transistor 10 and the normally-on transistor 20, so
that the overvoltage may be generated.
[0065] When the overvoltage is generated, the high voltage is
applied between the second source 21 and the second gate 23 of the
normally-on transistor 20. When the overvoltage becomes equal to or
higher than the withstand voltage of the gate insulating film,
there is a concern that the leakage current of the gate insulating
film of the normally-on transistor 20 is increased or the gate
insulating film is broken down. When the leakage current of the
gate insulating film of the normally-on transistor 20 is increased
or the gate insulating film is broken down, the semiconductor
device malfunctions. Therefore, the semiconductor device is reduced
in reliability.
[0066] In addition, even in a case where there is no problems in
the gate insulating film, when the high voltage is applied between
the second source 21 and the second gate 23 of the normally-on
transistor 20, electric charges are trapped in the second source
21. For this reason, a current collapse may be caused. When the
current collapse occurs, the on-state current is reduced to result
in malfunction. Therefore, the semiconductor device is also reduced
in reliability.
[0067] In the semiconductor device according to the embodiment, in
a case where the overvoltage is generated in the connection portion
between the normally-off transistor 10 and the normally-on
transistor 20, the electric charges escape to the zener diode 30
and are pulled out to the source terminal 100 at the time when the
overvoltage reaches the zener voltage. Therefore, a voltage rise in
the connection portion is suppressed, and an increase in the
leakage current of the gate insulating film of the normally-on
transistor 20 and the breakdown of the gate insulating film are
prevented. In addition, the current collapse is also prevented.
Therefore, the semiconductor device is improved in reliability.
[0068] In addition, even in a case where an unexpected high voltage
such as noises or the like is applied to the first drain 12 of the
normally-off transistor 10, the electric charges can escape through
the zener diode 30. Therefore, the semiconductor device will also
contribute to the protection of the normally-off transistor 10.
[0069] In general, the zener diode 30 has less resistance against
heat compared to the normally-on transistor 20 of the nitride
semiconductor. In other words, an increase in the leakage current
caused by the temperature rise and the characteristics variation
such as a variation in the zener voltage are remarkable in the
zener diode 30. In addition, a temperature resulting in the element
destruction is also low compared to the normally-on transistor
20.
[0070] In the embodiment, the first metal substrate 95 to be
mounted by the zener diode 30 and the second metal substrate 96 to
be mounted by the normally-on transistor 20 are physically
separated through a material having a low thermal conductivity.
With this configuration, the zener diode 30 is thermally separated
from the normally-on transistor 20, so that a thermal influence due
to the heat generated by the normally-on transistor 20 is
suppressed from affecting the zener diode 30. Therefore, the
semiconductor device which has less characteristics variation and
high reliability is realized.
[0071] In general, the zener diode 30 is less resistant against
heat compared to the normally-off transistor 10 of the silicon
semiconductor. In other words, an increase in the leakage current
caused by the temperature rise and the characteristics variation
such as a variation in the zener voltage are remarkable in the
zener diode 30 compared to the normally-off transistor 10. In
addition, a temperature resulting in the element destruction is
also low compared to the normally-off transistor 10.
[0072] In the embodiment, a distance between the zener diode 30 and
the normally-on transistor 20 is longer than that between the
normally-off transistor 10 and the normally-on transistor 20. With
this configuration, the temperature rise of the zener diode 30 is
suppressed lower than that of the normally-off transistor 10.
Therefore, the thermal influence due to the heat generated by the
normally-on transistor 20 is suppressed from affecting the zener
diode 30. Therefore, the semiconductor device which has less
characteristics variation and higher reliability is realized.
[0073] As described above, with the semiconductor device according
to the embodiment, an advantage that the resistance is improved in
a case where the overvoltage is generated in the connection portion
is obtained in addition to the advantage of the first embodiment.
In addition, an advantage of suppressing the current collapse is
also obtained. Then, since the zener diode 30 is thermally
separated from the normally-on transistor 20, the characteristics
variation due to the heat is also suppressed. Therefore, the
semiconductor device which has less characteristics variation and
higher reliability is realized.
Fourth Embodiment
[0074] A semiconductor device according to the embodiment is
different from the third embodiment in that there is further
provided a schottky-barrier diode on the first metal substrate. A
redundant description overlapping the first and third embodiments
will be omitted.
[0075] FIG. 7 is a top view schematically illustrating the
semiconductor device according to the embodiment, in which a mold
resin is removed. FIG. 8 is a circuit diagram illustrating the
semiconductor device according to the embodiment.
[0076] The semiconductor device according to the embodiment is
provided with the zener diode 30 and a schottky-barrier diode 60 in
parallel with the normally-off transistor 10.
[0077] As illustrated in FIG. 8, the zener diode 30 includes the
first anode 31 and the first cathode 32. The first anode 31 is
connected to the first source. In addition, the first cathode 32 is
connected to the first drain 12 and the second source 21.
[0078] In addition, the schottky-barrier diode 60 is provided with
a second anode 61 and a second cathode 62. Then, the second anode
61 is connected to the first source 11. In addition, the second
cathode 62 is connected to the first drain 12 and the second source
21.
[0079] A forward drop voltage (Vf) of the schottky-barrier diode 60
is lower than a forward drop voltage (Vf) of a parasitic body diode
(not illustrated) of the normally-off transistor. Then, the
schottky-barrier diode 60 is provided between the first drain 12
and the second source 21, and the first source 11 in parallel with
the zener diode 30.
[0080] As illustrated in FIG. 7, an electrode pad 161 of the second
anode 61 is provided on the upper face of the schottky-barrier
diode 60. Then, the source lead 91 is electrically connected to the
electrode pad 161 of the second anode 61 using, for example, the
bonding wire 99.
[0081] In addition, an electrode of the second cathode 62 is
provided on the lower face of the schottky-barrier diode 60. Then,
the lower face of the schottky-barrier diode 60 is electrically
connected to the first metal substrate 95 using, for example, a
conductive adhesive such as silver paste.
[0082] Then, a distance between the zener diode 30 and the
normally-on transistor 20 and a distance between the
schottky-barrier diode 60 and the normally-on transistor 20 are
longer than that between the normally-off transistor 10 and the
normally-on transistor 20.
[0083] In a case where the schottky-barrier diode 60 is not
provided, the current flows through a parasitic body diode of the
normally-off transistor 10 in a reflux mode in which the source
terminal 100 becomes positive in voltage with respect to the drain
terminal 200. In the embodiment, there is provided the
schottky-barrier diode 60 of which the forward drop voltage (Vf))
is lower than the forward drop voltage (Vf) of the parasitic body
diode of the normally-off transistor 10. Therefore, the current
flows through the schottky-barrier diode 60 in the reflux mode.
[0084] The schottky-barrier diode operates only using a number of
carriers unlike a PIN diode. Therefore, the schottky-barrier diode
has an excellent recovery characteristic compared to the PIN diode.
Therefore, the recovery characteristic can be improved in the
reflux mode. Accordingly, it is possible to realize the
semiconductor device which is excellent in the reliability and the
recovery characteristic. Since the greater part of the withstand
voltage is burdened on the normally-on transistor 20, the
schottky-barrier diode 60 can be selected among diode products
having a low withstand voltage. With this configuration, it is
possible to achieve a body diode operation of a high withstand
voltage while maintaining the same forward drop voltage (Vf)
characteristic and the same recovery characteristic as the low
withstand voltage product.
[0085] In addition, since the forward drop voltage (Vf) is small,
the conduction loss and the switching loss can also be reduced in
the reflux mode. In addition, the overvoltage is suppressed from
being applied to the connection portion by a parasitic capacitance
of the schottky-barrier diode 60. In addition, since the electric
charges can escape from the connection portion by the leakage
current of the schottky-barrier diode 60, the overvoltage is
suppressed from being applied to the connection portion. Therefore,
the semiconductor device more improved in reliability is
realized.
[0086] Further, since the schottky-barrier diode 60 has no
guarantee against the avalanche, the withstand voltage of the
schottky-barrier diode 60 is desirably higher than the avalanche
breakdown voltage of the normally-off transistor 10.
[0087] In general, the schottky-barrier diode 60 has less
resistance against heat compared to the normally-on transistor 20
of the nitride semiconductor. In other words, an increase in the
leakage current caused by the temperature rise and the
characteristics variation such as a variation in the zener voltage
are remarkable in the schottky-barrier diode 60. In addition, also
a temperature resulting in the element destruction is low compared
to the normally-on transistor 20.
[0088] In the embodiment, the first metal substrate 95 to be
mounted by the schottky-barrier diode 60 and the second metal
substrate 96 to be mounted by the normally-on transistor 20 are
physically separated through a material having a low thermal
conductivity. With this configuration, the schottky-barrier diode
60 is thermally separated from the normally-on transistor 20, so
that a thermal influence due to the heat generated by the
normally-on transistor 20 is suppressed from affecting the zener
diode 30.
[0089] In general, the schottky-barrier diode 60 has less
resistance against heat compared to the zener diode 30. In other
words, an increase in the leakage current caused by the temperature
rise and the characteristics variation are remarkable in the
schottky-barrier diode 60 compared to the zener diode 30.
[0090] In the embodiment, a distance between the schottky-barrier
diode 60 and the normally-on transistor 20 which serves as a main
heat source is longer than that between the zener diode 30 and the
normally-on transistor 20. Therefore, it is possible to reduce an
influence on the schottky-barrier diode 60 due to the temperature
rise. Therefore, the semiconductor device which has less
characteristics variation and high reliability is realized.
[0091] As described above, with the semiconductor device according
to the embodiment, an advantage that the resistance is improved in
a case where the overvoltage is generated in the connection portion
is obtained in addition to the advantages of the first and third
embodiments. In addition, an advantage of suppressing the current
collapse is also obtained. Further, the recovery characteristic can
be improved in the reflux mode. In addition, since the zener diode
30 and the schottky-barrier diode 60 are thermally separated from
the normally-on transistor 20, the characteristics variation due to
the heat is also suppressed. Therefore, the semiconductor device
which has less characteristics variation and higher reliability is
realized.
[0092] Further, the embodiment has been described about the circuit
configuration in which the normally-off transistor of the silicon
semiconductor and the normally-on transistor of the nitride
semiconductor are connected in series. However, as long as the
normally-off transistor of the silicon semiconductor and the
normally-on transistor of the nitride semiconductor are mounted on
different metal substrates, the circuit configuration is not
necessarily limited to the embodiment.
[0093] While certain embodiments have been described, these
embodiments have been presented by way of example only, and are not
intended to limit the scope of the inventions. Indeed, the
semiconductor device described herein may be embodied in a variety
of other forms; furthermore, various omissions, substitutions and
changes in the form of the devices and methods described herein may
be made without departing from the spirit of the inventions. The
accompanying claims and their equivalents are intended to cover
such forms or modifications as would fall within the scope and
spirit of the inventions.
* * * * *