U.S. patent application number 14/699414 was filed with the patent office on 2015-08-20 for comparator, solid-state imaging device, electronic apparatus, and driving method.
The applicant listed for this patent is Sony Corporation. Invention is credited to Yuuichi Kaji, Shizunori Matsumoto, Haruhisa Naganokawa, Hideki Tanaka.
Application Number | 20150237285 14/699414 |
Document ID | / |
Family ID | 51600859 |
Filed Date | 2015-08-20 |
United States Patent
Application |
20150237285 |
Kind Code |
A1 |
Tanaka; Hideki ; et
al. |
August 20, 2015 |
COMPARATOR, SOLID-STATE IMAGING DEVICE, ELECTRONIC APPARATUS, AND
DRIVING METHOD
Abstract
A solid-state imaging device that outputs a pixel signal having
a signal level corresponding to charges generated by a
photoelectric conversion includes a comparator. The comparator has
a first amplifying unit with first and second transistors
configured as a differential pair and provides a signal output by
amplifying a difference of signals input to the gate electrodes of
the first and second transistors. It also has a second amplifying
unit that amplifies the signal output, a first condenser disposed
between the gate electrode of the first transistor and a reference
signal supply, a second condenser disposed between the gate
electrode of the second transistor and pixel signal wiring that
reads out the pixel signal, and a switching circuit that connects
the reference signal supply to the pixel signal wiring.
Inventors: |
Tanaka; Hideki; (Fukuoka,
JP) ; Matsumoto; Shizunori; (Kanagawa, JP) ;
Naganokawa; Haruhisa; (Kanagawa, JP) ; Kaji;
Yuuichi; (Kanagawa, JP) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Sony Corporation |
Tokyo |
|
JP |
|
|
Family ID: |
51600859 |
Appl. No.: |
14/699414 |
Filed: |
April 29, 2015 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
14208789 |
Mar 13, 2014 |
9041583 |
|
|
14699414 |
|
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Current U.S.
Class: |
348/300 |
Current CPC
Class: |
H04N 5/3765 20130101;
H04N 5/378 20130101; H04N 5/3745 20130101; H03K 5/2481 20130101;
H03M 1/0607 20130101 |
International
Class: |
H04N 5/378 20060101
H04N005/378; H04N 5/376 20060101 H04N005/376 |
Foreign Application Data
Date |
Code |
Application Number |
Mar 29, 2013 |
JP |
2013-072325 |
Claims
1. A solid-state imaging device comprising: a pixel that outputs a
pixel signal having a signal level corresponding to charges
generated by a photoelectric conversion; a pixel signal wiring that
reads out the pixel signal; and a comparator including: a first
amplifying unit that includes first and second transistors
configured as a differential pair, and amplifies a difference of
signals input to each of the gate electrodes of the first and
second transistors to provide a signal output; a second amplifying
unit that amplifies the signal output from the first amplifying
unit; a first condenser that is disposed between the gate electrode
of the first transistor and a reference signal supply unit which
supplies a reference signal; a second condenser that is disposed
between the gate electrode of the second transistor and the pixel
signal wiring which reads out the pixel signal; a switching circuit
that connects the reference signal supply unit to the pixel signal
wiring.
2. The solid-state imaging device according to claim 1, wherein the
first amplifying unit includes a third transistor that is connected
between the gate electrode of the first transistor and the drain of
the first transistor.
3. The solid-state imaging device according to claim 2, wherein the
first amplifying unit includes a fourth transistor that is
connected between the gate electrode of the second transistor and
the drain of the second transistor.
4. The solid-state imaging device according to claim 3, wherein the
second amplifying unit includes a fifth transistor whose gate
electrode is connected to the first amplifying unit.
5. The solid-state imaging device according to claim 4, wherein the
second amplifying unit includes a sixth transistor whose drain is
connected to a drain of the fifth transistor and a source is
connected to a predetermined voltage.
6. The solid-state imaging device according to claim 5, wherein the
second amplifying unit includes a seventh transistor that is
connected between a gate electrode of the sixth transistor and the
drain of the sixth transistor.
7. The solid-state imaging device according to claim 6, wherein the
second amplifying unit includes a third condenser that is connected
a connection point of the gate electrode of the sixth transistor
and a source of seventh transistor to the predetermined
voltage.
8. An electronic apparatus comprising: a solid-state imaging device
including: a pixel that outputs a pixel signal having a signal
level corresponding to charges generated by a photoelectric
conversion, a pixel signal wiring that reads out the pixel signal,
and a comparator, the comparator including: a first amplifying unit
that includes first and second transistors configured as a
differential pair, and amplifies a difference of signals input to
each of the gate electrodes of the first and second transistors to
provide a signal output; a second amplifying unit that amplifies
the signal output from the first amplifying unit; a first condenser
that is disposed between the gate electrode of the first transistor
and a reference signal supply unit which supplies a reference
signal; a second condenser that is disposed between the gate
electrode of the second transistor and the pixel signal wiring
which reads out the pixel signal; and a switching circuit that
connects the reference signal supply unit to the pixel signal
wiring.
9. The electronic apparatus according to claim 8, wherein the first
amplifying unit includes a third transistor that is connected
between the gate electrode of the first transistor and the drain of
the first transistor.
10. The electronic apparatus according to claim 9, wherein the
first amplifying unit includes a fourth transistor that is
connected between the gate electrode of the second transistor and
the drain of the second transistor.
11. The electronic apparatus according to claim 10, wherein the
second amplifying unit includes a fifth transistor whose gate
electrode is connected to the first amplifying unit.
12. The electronic apparatus according to claim 11, wherein the
second amplifying unit includes a sixth transistor whose drain is
connected to a drain of the fifth transistor and a source is
connected to a predetermined voltage.
13. The electronic apparatus according to claim 12, wherein the
second amplifying unit includes a seventh transistor that is
connected between a gate electrode of the sixth transistor and the
drain of the sixth transistor.
14. The electronic apparatus according to claim 13, wherein the
second amplifying unit includes a third condenser that is connected
a connection point of the gate electrode of the sixth transistor
and a source of seventh transistor to the predetermined voltage.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This is a Continuation application Ser. No. 14/208,789,
filed Mar. 13, 2015, which in turn claims the benefit of Japanese
Priority Patent Application No.: 2013-072325 filed Mar. 29, 2013,
the entire contents of which are incorporated herein by
reference.
BACKGROUND
[0002] The present disclosure relates to a comparator, a
solid-state imaging device, an electronic apparatus, and a driving
method, and particularly to a comparator, a solid-state imaging
device, an electronic apparatus, and a driving method with which
low power consumption and a decrease in size can be achieved.
[0003] In the related art, in an electronic apparatus that includes
an imaging function such as a digital still camera and a digital
video camera, for example, a solid-state imaging device such as a
complementary metal oxide semiconductor (CMOS) image sensor or a
charge coupled device (CCD) is used. The solid-state imaging device
includes a pixel in which a photo diode that performs a
photoelectric conversion and a plurality of transistors are
combined, and an image is built based on pixel signals output from
the plurality of pixels disposed in a plane.
[0004] For example, in the solid-state imaging device, charges
accumulated in the photo diode are transferred to a floating
diffusion (FD) unit that has a predetermined capacitance and is
provided on the connection unit between the photo diode and a gate
electrode of an amplifier transistor. Then, a signal corresponding
to a level of the charges kept in the FD unit is read out from the
pixel, and is analog digital (AD) converted by an AD conversion
circuit which has a comparator, and then, is output.
[0005] In the solid-state imaging device, as a signal processing
for removing a pixel-specific noise, for example, a correlated
double sampling processing is performed with respect to the pixel
signal output from the pixel. In the correlated double sampling
processing, a signal (P-phase) with a level in which the charges
accumulated in the FD unit is reset and a signal (D-phase) with a
level in which the charges generated in the photo diode are kept in
the FD unit, are sampled. Then, the noise can be removed by
obtaining a difference of each sampled value.
[0006] In the CMOS image sensor, in a case where simultaneity of a
shutter closing is retained, the charges are transferred in full
batch from the photo diode to the FD unit, and thereafter, the
pixel signal is sequentially read out. In this case, a driving of
reading the D-phase (signal level) first and the P-phase (reset
level) next (hereafter, appropriately referred to as a D-phase
first-read drive) is performed (for example, refer to Japanese
Unexamined Patent Application Publication No. 2001-238132).
[0007] For example, in Japanese Unexamined Patent Application
Publication No. 2011-229120, in a comparator circuit which performs
the D-phase first-read drive, a solid-state imaging device having a
configuration in which an external initial voltage is applied for
setting (adjusting) an internal node such that the comparator can
operate in accordance with the D-phase signal level, is
disclosed.
SUMMARY
[0008] However, as a solid-state imaging device disclosed in
Japanese Unexamined Patent Application Publication No. 2011-229120,
in a configuration in which an initial voltage for setting an
internal node is applied externally, since a circuit for supplying
the voltage is necessary, power consumption and a circuit size of
the solid-state imaging device increase.
[0009] In the present disclosure, it is desirable to decrease the
power consumption and a circuit size.
[0010] According to an embodiment of the present disclosure, there
is provided a comparator that includes: a first amplifying unit
that includes a differential pair configured with a pair of
transistors which are first and second transistors, and amplifies a
difference of signals input into each of the gate electrodes of the
first and second transistors, to be output; a second amplifying
unit that amplifies the signal output from the first amplifying
unit; a first condenser that is disposed between a gate electrode
of the first transistor and a reference signal supply unit which
supplies a reference signal the voltage value of which drops at a
constant gradient; a second condenser that is disposed between a
gate electrode of the second transistor and a pixel signal wiring
which reads out a pixel signal from a pixel that outputs the pixel
signal having a signal level corresponding to charges generated by
a photoelectric conversion; a third transistor that connects a
connection point of the gate electrode of the first transistor and
the first condenser to the pixel signal wiring; and a fourth
transistor that connects a connection point of the gate electrode
of the second transistor and the second condenser to the pixel
signal wiring.
[0011] According to another embodiment of the present disclosure,
there is provided a solid-state imaging device that includes a
pixel that outputs a pixel signal having a signal level
corresponding to charges generated by a photoelectric conversion;
and a column processing unit in which conversion units that convert
the pixel signal output from the pixel to a digital signal are
arrayed in parallel corresponding to the number of columns of the
pixels. A comparator included in the conversion unit includes: a
first amplifying unit that includes a differential pair configured
with a pair of transistors which are first and second transistors,
and amplifies a difference of signals input to each of the gate
electrodes of the first and second transistors, to output; a second
amplifying unit that amplifies the signal output from the first
amplifying unit; a first condenser that is disposed between a gate
electrode of the first transistor and a reference signal supply
unit which supplies a reference signal the voltage value of which
drops at a constant gradient; a second condenser that is disposed
between a gate electrode of the second transistor and a pixel
signal wiring which reads out a pixel signal from a pixel; a third
transistor that connects a connection point of the gate electrode
of the first transistor and the first condenser to the pixel signal
wiring; and a fourth transistor that connects a connection point of
the gate electrode of the second transistor and the second
condenser to the pixel signal wiring.
[0012] According to still another embodiment of the present
disclosure, there is provided an electronic apparatus that includes
a solid-state imaging device that includes: a pixel that outputs a
pixel signal having a signal level corresponding to charges
generated by a photoelectric conversion, a column processing unit
in which conversion units that convert the pixel signal output from
the pixel to a digital signal are arrayed in parallel corresponding
to the number of columns of the pixels. A comparator included in
the conversion unit includes a first amplifying unit that includes
a differential pair configured with a pair of transistors which are
first and second transistors, and amplifies a difference of signals
input to each of the gate electrodes of the first and second
transistors, to output; a second amplifying unit that amplifies the
signal output from the first amplifying unit; a first condenser
that is disposed between a gate electrode of the first transistor
and a reference signal supply unit which supplies a reference
signal the voltage value of which drops at a constant gradient; a
second condenser that is disposed between a gate electrode of the
second transistor and a pixel signal wiring which reads out a pixel
signal from a pixel; a third transistor that connects a connection
point of the gate electrode of the first transistor and the first
condenser to the pixel signal wiring; and a fourth transistor that
connects a connection point of the gate electrode of the second
transistor and the second condenser to the pixel signal wiring.
[0013] According to still another embodiment of the present
disclosure, there is provided a driving method of a comparator that
includes a first amplifying unit that includes a differential pair
configured with a pair of transistors which are first and second
transistors, and amplifies a difference of signals input to each of
the gate electrodes of the first and second transistors, to output;
a second amplifying unit that amplifies the signal output from the
first amplifying unit; a first condenser that is disposed between a
gate electrode of the first transistor and a reference signal
supply unit which supplies a reference signal the voltage value of
which drops at a constant gradient; a second condenser that is
disposed between a gate electrode of the second transistor and a
pixel signal wiring which reads out a pixel signal from a pixel
that outputs the pixel signal having a signal level corresponding
to charges generated by a photoelectric conversion; a third
transistor that connects a connection point of the gate electrode
of the first transistor and the first condenser to the pixel signal
wiring; and a fourth transistor that connects a connection point of
the gate electrode of the second transistor and the second
condenser to the pixel signal wiring, and the method includes
supplying a voltage of a pixel signal supplied via the pixel signal
wiring to each of the gate electrodes of the first transistor and
the second transistor, with the third transistor and the fourth
transistor being in an ON state, in a case where a drive of reading
out a pixel signal having a reset level in which the charges are
reset is performed after firstly the reading out the pixel signal
having the signal level from the pixel when the auto-zero operation
of the first amplifying unit for setting an initial voltage in the
first amplifying unit circuit is performed.
[0014] In the embodiments of the present disclosure, a comparator
includes a first amplifying unit that has a differential pair
configured with a pair of transistors which are first and second
transistors and amplifies a difference of signals input to each of
the gate electrodes of the first and second transistors, to output;
and a second amplifying unit that amplifies the signal output from
the first amplifying unit. A first condenser is disposed between a
gate electrode of the first transistor and a reference signal
supply unit which supplies a reference signal the voltage value of
which drops at a constant gradient, and a second condenser is
disposed between a gate electrode of the second transistor and a
pixel signal wiring which reads out a pixel signal from a pixel
that outputs the pixel signal having a signal level corresponding
to charges generated by a photoelectric conversion. A third
transistor connects a connection point of the gate electrode of the
first transistor and the first condenser to the pixel signal
wiring, and a fourth transistor connects a connection point of the
gate electrode of the second transistor and the second condenser to
the pixel signal wiring.
[0015] According to the embodiments the present disclosure, the
decrease in power consumption and circuit size can be achieved.
BRIEF DESCRIPTION OF THE DRAWINGS
[0016] FIG. 1 is a block diagram illustrating a configuration
example of a solid-state imaging device to which the present
technology is adapted according to an embodiment;
[0017] FIG. 2 is a diagram explaining a configuration of a
pixel;
[0018] FIG. 3 is a diagram explaining a D-phase first-read
drive;
[0019] FIG. 4 is a circuit diagram illustrating a configuration
example of a comparator to which the present technology is adapted
according to a first embodiment;
[0020] FIG. 5 is a diagram illustrating a timing chart in a first
driving method of the comparator;
[0021] FIG. 6 is a diagram explaining a voltage waveform in the
comparator;
[0022] FIG. 7 is a diagram explaining a voltage waveform in the
comparator in the related art;
[0023] FIG. 8 is a diagram explaining an external apply voltage
generation circuit necessary for the comparator in the related
art;
[0024] FIG. 9 is a circuit diagram illustrating a configuration
example of the comparator in the related art;
[0025] FIG. 10 is a diagram explaining a voltage waveform in the
comparator in the related art that uses the external apply voltage
generation circuit;
[0026] FIG. 11 is a diagram illustrating a timing chart in a second
driving method of the comparator;
[0027] FIG. 12A and FIG. 12B are diagrams explaining a difference
between the first driving method and the second driving method of
the comparator;
[0028] FIG. 13 is a circuit diagram illustrating a configuration
example of a comparator to which the present technology is adapted
according to a second embodiment;
[0029] FIG. 14 is a diagram illustrating a timing chart of the
comparator;
[0030] FIG. 15 is a circuit diagram illustrating a configuration
example of a comparator to which the present technology is adapted
according to a third embodiment;
[0031] FIG. 16 is a circuit diagram illustrating a configuration
example of a comparator to which the present technology is adapted
according to a fourth embodiment;
[0032] FIG. 17 is a diagram illustrating an internal voltage
waveform of the comparator in a case where a P-phase first-read
drive is performed; and
[0033] FIG. 18 is a block diagram illustrating a configuration
example of an imaging apparatus that is mounted on an electronic
apparatus.
DETAILED DESCRIPTION OF EMBODIMENTS
[0034] Hereinafter, a specific embodiment to which the present
disclosure is adapted will be described in detail with reference to
drawings.
[0035] FIG. 1 is a block diagram illustrating a configuration
example of a solid-state imaging device to which the present
technology is adapted according to an embodiment.
[0036] As illustrated in FIG. 1, the solid-state imaging device 11
is a CMOS image sensor, and is configured to include a pixel array
unit 12, a timing control unit 13, a reference signal generation
circuit 14, a row scanning unit 15, a column scanning unit 16, and
a column processing unit 17.
[0037] In the pixel array unit 12, a plurality of pixels 21 is
arrayed. In the example in FIG. 1, the pixels 21.sub.11 to
21.sub.mn in row m.times.column n are arrayed in a matrix shape,
and the pixels 21 in each row are connected to the row scanning
unit 15 via m horizontal signal lines 22.sub.1 to 22.sub.m, and are
connected to the column processing unit 17 via n vertical signal
lines 23.sub.1 to 23.sub.n. In the pixel array unit 12, the pixels
21.sub.11 to 21.sub.mn operate according to a control signal
supplied from the row scanning unit 15 via the horizontal signal
lines 22.sub.1 to 22.sub.m, and output a pixel signal having a
level corresponding to an amount of received light via the vertical
signal lines 23.sub.1 to 23.sub.n.
[0038] The timing control unit 13 generates a signal based on a
master clock signal MCK, and controls the operation timing of the
reference signal generation circuit 14, the row scanning unit 15,
the column scanning unit 16, and the column processing unit 17. For
example, the timing control unit 13 generates a clock signal CLK
which is a reference for the operations of the reference signal
generation circuit 14 and column processing unit 17, and supplies
the clock signal CLK to the reference signal generation circuit 14
and column processing unit 17. The timing control unit 13 generates
a control signal CS1 that controls the operation of the reference
signal generation circuit 14 and supplies the control signal CS1 to
the reference signal generation circuit 14, and generates control
signals CS2 and CS3 that control the operation of the column
processing unit 17 and supplies the control signals CS2 and CS3 to
the column processing unit 17.
[0039] The reference signal generation circuit 14 generates a
reference signal Vramp (so-called ramp signal) of which the voltage
drops at a certain gradient according to the clock signal CLK and
the voltage value starts to drop at the timing depending on the
control signal CS1, and supplies the reference signal Vramp to the
column processing unit 17 via a reference signal wiring.
[0040] The row scanning unit 15 supplies a control signal (for
example, a transfer signal, a selection signal, a reset signal, or
the like) that controls the driving of the pixels 21.sub.11 to
21.sub.mn of the pixel array unit 12 for each row, to the pixels
21.sub.11 to 21.sub.mn at the timing depending on the control from
the timing control unit 13.
[0041] The column scanning unit 16 supplies a control signal that
outputs the pixel signal which is AD converted by the column
processing unit 17 to the horizontal output line in an order of
each row from the pixels 21.sub.11 to 21.sub.mn, to the column
processing unit 17 at the timing depending on the control from the
timing control unit 13.
[0042] The column processing unit 17 includes n AD conversion
circuits 30.sub.1 to 30.sub.n corresponding to the number of
columns of the pixels 21.sub.11 to 21.sub.mn that are arrayed in
the pixel array unit 12. The pixels 21.sub.11 to 21.sub.mn are
connected to the column processing unit 17 via the vertical signal
line 23.sub.1 to 23.sub.n. Then, in the column processing unit 17,
the AD conversion circuits 30.sub.1 to 30.sub.n AD convert and
output the pixel signal output from the pixels 21.sub.11 to
21.sub.mn for each row of the pixels 21.sub.11 to 21.sub.mn in
parallel.
[0043] The AD conversion circuits 30.sub.1 to 30.sub.n are
configured to include comparators 31.sub.1 to 31.sub.n, counters
32.sub.1 to 32.sub.n, switches 33.sub.1 to 33.sub.n, and memories
34.sub.1 to 34.sub.n, respectively. The AD conversion circuits
30.sub.1 to 30.sub.n are configured to be the same. Thus,
hereinafter, in a case where they are not distinguished from each
other, the AD conversion circuits 30.sub.1 to 30.sub.n will be
referred to as AD conversion circuit 30. The above description will
also be applied to each part of the AD conversion circuit 30.
[0044] In the comparator 31, one input terminal is connected to the
pixel 21 via the vertical signal line 23, the other input terminal
is connected to the reference signal generation circuit 14 via the
reference signal wiring, and the output terminal is connected to
the counter 32. Then, the comparator 31 compares the voltage of the
pixel signal input via the vertical signal line 23 and the voltage
of the reference signal Vramp supplied from the reference signal
generation circuit 14, for example, in a case where the voltage of
the reference signal Vramp is higher than the voltage of the pixel
signal, then outputs the high level signal, and in a case where the
reference signal Vramp is equal to or lower than the voltage of the
pixel signal, then outputs the low level signal.
[0045] The counter 32 performs the counting in synchronization with
the clock signal CLK supplied from the timing control unit 13
according to the control signal CS2 supplied from the timing
control unit 13. For example, the counter 32 measures a comparing
duration from the starting of the comparing operation in the
comparator 31 to the end of the comparing operation (for example,
D-phase inversion time and P-phase inversion time described below
in FIG. 6) by performing the down counting or up counting in
synchronization with the clock signal CLK.
[0046] The switch 33 is in an ON state (closed) at the time point
when the counting operation of the counter 32 regarding the pixel
21 in the predetermined row is completed, according to the control
signal CS3 supplied from the timing control unit 13. Then, the
switch 33 transfers the counted result of the counter 32, that is,
the pixel signal which is converted to a digital signal from an
analog signal, to the memory 34.
[0047] The memory 34 outputs the kept pixel signal to the
horizontal output line according to the control signal supplied
from the column scanning unit 16.
[0048] Next, the configuration of the pixel 21 will be described
with reference to FIG. 2.
[0049] As illustrated in FIG. 2, the pixel 21 is configured to
include a photo diode 41, a transfer transistor 42, an electric
charge accumulation unit 43, an FD unit 44, an amplifier transistor
45, a selection transistor 46, and a reset transistor 47.
[0050] The photo diode 41 is a photoelectric conversion unit that
converts a light to an electric charge, and generates and
accumulates the charges according to the amount of the received
light. An anode electrode of the photo diode 41 is grounded, and
the cathode electrode of the photo diode 41 is connected to a gate
electrode of the amplifier transistor 45 via the transfer
transistor 42.
[0051] The transfer transistor 42 drives according to a transfer
signal Tx supplied from the row scanning unit 15 in FIG. 1. When
the transfer signal Tx supplied to the gate electrode of the
transfer transistor 42 is at a high level, the transfer transistor
42 is in the ON state, and the charges accumulated in the photo
diode 41 are transferred to the FD unit 44 via the transfer
transistor 42.
[0052] The electric charge accumulation unit 43 is a capacitance
provided between the FD unit 44 and the ground level, and
accumulates the charges transferred from the photo diode 41 to the
FD unit 44 via the transfer transistor 42.
[0053] The FD unit 44 is an electric charge detection unit that
converts the charges to the voltage; the charges kept in the FD
unit 44 are converted into the voltage in the amplifier transistor
45.
[0054] The amplifier transistor 45 is an input unit of a source
follower that is a read-out circuit which reads out the signal
obtained by the photoelectric conversion in the photo diode 41, and
outputs the pixel signal having the level corresponding to the
charges accumulated in the FD unit 44 to the vertical signal line
23. That is, the amplifier transistor 45 configures a current
source which is connected to one end of the vertical signal line 23
and the source follower by the source electrode of the amplifier
transistor 45 being connected to the vertical signal line 23 via
the selection transistor 46.
[0055] The selection transistor 46 drives according to a selection
signal SEL supplied from the row scanning unit 15 in FIG. 1. For
example, when the selection signal SEL supplied to the gate
electrode of the selection transistor 46 is at the high level, the
selection transistor 46 is in the ON state and connects the
amplifier transistor 45 and the vertical signal line 23, and then,
makes the output signal VSL output from the amplifier transistor 45
be in a state that can be output to the vertical signal line
23.
[0056] The reset transistor 47 operates according to a reset signal
RST supplied from the row scanning unit 15 in FIG. 1. For example,
when the reset signal RST supplied to the gate electrode of the
reset transistor 47 is at the high level, the reset transistor 47
is in the ON state and discharges the charges accumulated in the FD
unit 44 to the power source voltage VDD, and then resets the FD
unit 44.
[0057] The vertical signal line 23 is connected to one input
terminal of the comparator 31 via a condenser 51-2, and the other
input terminal of the comparator 31 is connected to the reference
signal generation circuit 14 that supplies the reference signal
Vramp via the condenser 51-1.
[0058] In the solid-state imaging device 11 configured in this way,
by the charges accumulated in the photo diode 41 being batch
transferred to the FD unit 44, and being read out sequentially for
each column, the simultaneity of a shutter closing is retained.
[0059] In the solid-state imaging device 11, the D-phase first-read
drive is performed, in which the signal level (D-phase) in a state
in which the charges generated in the photo diode 41 are kept in
the FD unit 44 is read out first, and then the reset level
(P-phase) in a state in which the charges in the FD unit 44 are
discharged via the reset transistor 47 is read out.
[0060] The D-phase first-read drive will be described with
reference to FIG. 3. In FIG. 3, from top to bottom in an order, the
reset signal RST, the transfer signal Tx, the selection signal SEL,
the reference signal Vramp, and the output signal VSL are
illustrated.
[0061] First, at the point in time t1, by the reset signal RST and
the transfer signal Tx being at the high level, the shutter
operation is performed, in which the charges of the photo diode 41
are discharged. At this time, by performing the shutter operation
in all of the pixels 21 arrayed in the pixel array unit 12
simultaneously, a global shutter is realized, in which accumulation
duration is to be in the same timing for all of the pixels 21.
[0062] Next, at the point in time t2, when the reset signal RST and
the transfer signal Tx are at a low level, the shutter operation is
completed, and the accumulation duration starts, in which the
charges generated by the photoelectric conversion in the photo
diode 41 are accumulated.
[0063] Then, at the point in time t3, by the transfer signal Tx
being at the high level, the accumulation duration ends, and the
transfer operation is performed, in which the charges accumulated
in the photo diode 41 are transferred to the FD unit 44. Before the
accumulation duration ends, by the reset signal RST being at the
high level in a pulse shape, the charges accumulated in the FD unit
44 during the accumulation duration are discharged. In order to
realize the global shutter, the full-batch transfer is performed,
during which the transfer operation is performed simultaneously in
all of the pixels 21 arrayed in the pixel array unit 12. At the
point in time t4, when the transfer signal Tx is in the low level,
the transfer operation is completed.
[0064] Then, the AD conversion is performed in an order from the
pixels 21 of the first row. First, at the point in time t5, by the
selection signal SEL of the pixels 21 of the first row being at the
high level, the pixels 21 of the first row are selected, and then
the amplifier transistors 45 are connected to the vertical signal
lines 23. After the point in time t5, in a state in which the level
of the output signal VSL output via the vertical signal line 23 is
stable, the signal level (D-phase) corresponding to the charges
generated in the photo diode 41 is read out.
[0065] Next, from the point in time t6 to t7, the rest signal RST
is at the high level, the charges accumulated in the FD unit 44 are
discharged via the reset transistor 47, and then the FD unit 44 is
reset. Then, after the point in time t7, in a state in which the
level of the output signal VSL is stable, the reset level (P-phase)
in the state in which the charges of the FD unit 44 are discharged
is read out. Then, in the point in time t8, by the selection signal
SEL of the pixels 21 of the first row being in the low level, the
selection of the pixels 21 of the first row is released, and then
the AD conversion processing of the pixels 21 of the first row is
completed.
[0066] Then, in the point in time t9 to t12, similar to the case in
the point in time t5 to t8, the AD conversion processing of the
pixels 21 of the second row is performed, and thereafter, the AD
conversion processing of the pixels 21 of each row up to an
m.sub.th row is sequentially and repeatedly performed.
[0067] Next, FIG. 4 is a circuit diagram illustrating a
configuration example of a comparator 31 to which the present
technology is adapted according to the first embodiment.
[0068] As illustrated in FIG. 4, the comparator 31 is configured in
combination of condensers 51-1 to 51-3, transistors 61-1 to 61-11,
and a current source 62.
[0069] In the comparator 31, the source electrodes of the
transistors 61-6 and 61-7 are connected in common and configure a
differential pair, and the current source 62 is connected between
the common source electrodes.
[0070] The gate electrode of the transistor 61-6 is connected to
the reference signal generation circuit 14 (FIG. 1) that supplies
the reference signal Vramp via the condenser 51-1, and an internal
node Vramp_i in the gate electrode of the transistor 61-6 is the
voltage corresponding to the reference signal Vramp. The gate
electrode of the transistor 61-7 is connected to the vertical
signal line 23 (FIG. 1) that supplies the output signal VSL via the
condenser 51-2, and an internal node VSL_i in the gate electrode of
the transistor 61-7 is the voltage corresponding to the output
signal VSL.
[0071] The transistor 61-8 is connected between the drain electrode
of the transistor 61-6 and the power source voltage VDD in a diode
connection configuration, that is, in a configuration in which the
gate electrode and the drain electrode become common. The
transistor 61-9 is connected between the drain electrode of the
transistor 61-7 and the power source voltage VDD. The gate
electrode of the transistor 61-8 and the gate electrode of the
transistor 61-9 are commonly connected to each other.
[0072] The transistor 61-1 is connected between the gate electrode
and the drain electrode of the transistor 61-6, and a control
signal x.phi.1 from the row scanning unit 15 (FIG. 1) is supplied
to the gate electrode of the transistor 61-1. The transistor 61-2
is connected between the gate electrode and drain electrode of the
transistor 61-7, and a control signal x.phi.2 from the row scanning
unit 15 is supplied to the gate electrode of the transistor
61-2.
[0073] The transistor 61-3 is connected between gate electrode of
the transistor 61-6 and the vertical signal line 23, and a control
signal x.phi.3 from the row scanning unit 15 is supplied to the
gate electrode of the transistor 61-3. The transistor 61-4 is
connected between gate electrode of the transistor 61-7 and the
vertical signal line 23, and a control signal x.phi.4 from the row
scanning unit 15 is supplied to the gate electrode of the
transistor 61-4. That is, the source electrode of the transistors
61-3 and 61-4 are commonly connected to the vertical signal line
23.
[0074] The transistor 61-11 is connected between the output
terminal of the comparator 31 and the power source voltage VDD, and
the gate electrode of the transistor 61-11 is connected to the
connection point of the transistors 61-7 and 61-9.
[0075] The transistor 61-10 is connected between the source
electrode of the transistor 61-11 and the ground, and the gate
electrode of the transistor 61-10 is connected to the connection
point of the transistors 61-5 and 51-3.
[0076] The drain electrode of the transistor 61-5 is connected to
the output terminal of the comparator 31, and the source electrode
of the transistor 61-5 is grounded via the condenser 51-3, and a
control signal .phi.5 from the row scanning unit 15 is supplied to
the gate electrode of the transistor 61-5.
[0077] The comparator 31 is configured in this way. Accordingly, by
a differential amplifier in which the transistors 61-6 and 61-7 are
configured to be a pair, a difference between the reference signal
Vramp input to the gate electrode of the transistor 61-6 and the
output signal VSL input to the gate electrode of the transistor
61-7 is amplified and output. The output from the differential
amplifier is amplified by a source-grounded amplifier configured
with the transistors 61-10 and 61-11, and is output from the output
terminal of the comparator 31.
[0078] Hereinafter, the source-ground amplifier configured with the
transistors 61-6 to 61-9 and the current source 62 is called a
first-stage amplifier 81, and the output of the first-stage
amplifier 81 is set to amplifier output VOUT1. The differential
amplifier configured with the transistors 61-10 to 61-11 is called
a post-stage amplifier 82, and the output of the post-stage
amplifier 82 is set to amplifier output Vout2. The transistors 61-1
to 61-5 are used for operation of setting the initial voltage in
the comparator 31 circuit (hereafter referred to as auto-zero
operation). The condensers 51-1 to 51-3 are capacitance devices for
keeping the internal voltage (operating point) of the
amplifier.
[0079] In FIG. 5, a timing chart in a first driving method of the
comparator 31 is illustrated.
[0080] In FIG. 5, from top to bottom in an order, the control
signal x.phi.1 for controlling the transistor 61-1, the control
signal x.phi.2 for controlling the transistor 61-2, the control
signal x.phi.3 for controlling the transistor 61-3, the control
signal x.phi.4 for controlling the transistor 61-4, the control
signal .phi.5 for controlling the transistor 61-5, the reference
signal Vramp for the reference in comparing the voltage level, and
the output signal VSL output from the pixel 21 to the vertical
signal line 23 are illustrated.
[0081] First, at the point in time t21, the control signals x.phi.1
and x.phi.2 are shifted to the low level from the high level, and
the control signal .phi.5 is shifted to the high level from the low
level. At this time, the control signals x3 and x.phi.4 remain at
the high level. Accordingly, since an inverted control signal is
input to the transistors 61-1 and 61-2, the transistors 61-1 and
61-2 are in the ON state according to the control signals x.phi.1
and x.phi.2, respectively, and the transistor 61-5 is in the ON
state according to the control signal .phi.5. In this way, the
auto-zero operation of the post-stage amplifier 82 starts.
[0082] That is, in the auto-zero operation of the post-stage
amplifier 82, the initial voltage set by the transistors 61-1 and
61-2 being in the ON state is kept as the internal node Vramp_i in
the gate electrode of the transistor 61-6 and is kept as the
internal node VSL_i in the gate electrode of the transistor 61-7.
At the same time, in the post-stage amplifier 82, by the transistor
61-5 being in the ON state, the current corresponding to the
amplifier output VOUT1 of the first-stage amplifier 81 flows in the
transistor 61-10 and 61-11. Then, at the time point (t22) when the
transistor 61-5 is in an OFF state, the voltage value corresponding
to the amount of current in the transistor 61-10 is kept in the
condenser 51-3.
[0083] At the point in time t22, by the control signal .phi.5 being
shifted to low level and the transistor 61-5 being in the OFF
state, the auto-zero operation of the post-stage amplifier 82 is
completed. Subsequently, the control signals x.phi.1 and x.phi.2
are shifted to the high level and the transistors 61-1 and 61-2 are
in the OFF state.
[0084] Next, at the point in time t23, the control signals x.phi.3
and x.phi.4 are shifted to the low level from the high level.
Accordingly, since an inverted control signal is input to the
transistors 61-3 and 61-4, the transistors 61-3 and 61-4 are in the
ON state according to the control signals x.phi.3 and x.phi.4,
respectively. In this way, the auto-zero operation of the
first-stage amplifier 81 starts.
[0085] That is, in the auto-zero operation of the first-stage
amplifier 81, the signal level of the output signal VSL supplied
via the vertical signal line 23 is directly input to the gate
electrode of the transistors 61-6 and 61-7. In this way, the signal
level of the output signal VSL is set as initial voltages of the
internal node Vramp_i in the gate electrode of the transistor 61-6
and the internal node VSL_i in the gate electrode of the transistor
61-7.
[0086] At the point in time t24, the control signals x.phi.3 and
x.phi.4 being shifted to the high level and the transistors 61-3
and 61-4 being in the OFF state, the auto-zero operation of the
first-stage amplifier 81 is completed.
[0087] Subsequently, the reference signal Vramp drops at a constant
gradient during the period of the time from t25 to t26, and AD
conversion for D-phase is performed. Then, as described with
reference to FIG. 3, after the FD unit 44 being reset, the
reference signal Vramp drops at a constant gradient during the
period of the time from t27 to t28, and AD conversion for P-phase
is performed.
[0088] In this way, in the auto-zero operation of the first-stage
amplifier 81 in the comparator 31, it is possible to automatically
set (adjust) the signal level of the output signal VSL as the
initial voltage of the internal node Vramp_i in the gate electrode
of the transistor 61-6 and the internal node VSL_i in the gate
electrode of the transistor 61-7.
[0089] Next, in FIG. 6, a voltage waveform in the comparator 31 is
illustrated.
[0090] As described with reference to FIG. 5, by the auto-zero
operation of the first-stage amplifier 81, the initial voltages of
the internal node Vramp_i and the internal node VSL_i are set as
the signal level of the output signal VSL supplied via the vertical
signal line 23.
[0091] At this time, since the output signal VSL corresponds to the
level of the charges kept in the FD unit 44, that is, the level of
charges generated in the photo diode 41, the electric potential
level of the output signal VSL depends upon the illuminance of the
light irradiated to the photo diode 41. Therefore, as illustrated
in FIG. 6, in the auto-zero operation of the first-stage amplifier
81, the electric potential level is low in a case where the
illuminance of the light irradiated to the photo diode 41 is high,
and the electric potential level is high in a case where the
illuminance of the light irradiated to the photo diode 41 is
low.
[0092] In this way, after the initial voltages of the internal node
Vramp_i and the internal node VSL_i are set as the signal level of
the output signal VSL supplied via the vertical signal line 23, the
internal node Vramp_i drops according to the reference signal Vramp
which drops at a constant gradient. Then, at the voltage where the
internal node Vramp_i in the gate electrode of the transistor 61-6
and the internal node VSL_i in the gate electrode of the transistor
61-7 are matched, the amplifier outputs VOUT1 and VOUT2 are
inverted, and the D-phase conversion is performed.
[0093] Subsequently, in accordance with resetting of the FD unit 44
of the pixel 21, the reference signal Vramp is reset to a high
voltage level, and the reference signal Vramp is dropped again.
Then, at the voltage where the internal node Vramp_i in the gate
electrode of the transistor 61-6 and the internal node VSL_i in the
gate electrode of the transistor 61-7 are matched again, the
amplifier outputs VOUT1 and VOUT2 are inverted, and the P-phase
conversion is performed.
[0094] In this way, since the initial voltages of the internal node
Vramp_i and the internal node VSL_i are set as the signal level of
the output signal VSL supplied via the vertical signal line 23, the
operation point (a point illustrated by o in Figure) of the
comparator 31 in the D-phase conversion changes according to the
voltage level of the vertical signal line 23. In contrast, since
the reset level of the vertical signal line 23 for each pixel 21 is
substantially the same having some variations, the operating point
(the point illustrated by o in Figure) of the comparator 31 in the
P-phase conversion is substantially the same.
[0095] For this reason, by designing the comparator 31 in such a
manner that the reset level (the voltage level of P-phase) fits
within the operable input range, the initial voltage is
automatically determined according to the voltage level of D-phase.
Therefore, the comparator 31 can perform the AD conversion without
performing the adjustment of initial voltage.
[0096] In the comparator 31, by setting the initial voltages of the
internal node Vramp_i and the internal node VSL_i to the signal
level of the output signal VSL supplied via the vertical signal
line 23, the external power source for setting those initial
voltages is not necessary, and thus, it is possible to achieve a
reduction in power consumption and in size.
[0097] The comparator in the related art will be described with
reference to FIG. 7 to FIG. 9.
[0098] For example, in the D-phase first-read drive as described
with reference to FIG. 3, in a case where the AD conversion is
performed in the post-stage comparator circuit having the auto-zero
function, in the related art, the auto-zero operation is performed
with reference to the D-phase which is read out first, and thus the
operating point is set inside the circuit.
[0099] In FIG. 7, a voltage waveform inside the comparator circuit
in such case is illustrated.
[0100] As illustrated in FIG. 7, the voltage level of the vertical
signal line that connects the pixel and the comparator circuit is
low at the time of D-phase conversion, and is high at the time of
P-phase conversion due to the FD unit 44 of the pixel 21 being
reset. For this reason, if the auto-zero operation is performed
with reference to the D-phase, the internal voltage of the
comparator circuit (that is, the internal node Vramp_i and the
internal node VSL_i) exceeds the operable voltage range of the
first-stage amplifier 81. As a result, it is difficult to perform
the AD conversion processing as normal.
[0101] As disclosed in Japanese Unexamined Patent Application
Publication No. 2011-229120 described above, it has been necessary
for an initial voltage to be externally applied from the outside
for setting (adjusting) the internal node such that the comparator
is operable in accordance with the signal level of the D-phase
signal.
[0102] That is, as illustrated in FIG. 8, in order to operate the
comparator 31A as normal in the related art, an external apply
voltage generation circuit 71 has been necessary to generate an
arbitrary external apply voltage Vext and supply the arbitrary
external apply voltage Vext to the comparator 31A via the reference
signal wiring.
[0103] FIG. 9 is a circuit diagram illustrating a configuration of
the comparator 31A in the related art. In the comparator 31A in
FIG. 9, the configurations in common with the comparator 31 in FIG.
4 will be referenced by the same numerals, and the descriptions
will not be repeated.
[0104] As illustrated in FIG. 9, the comparator 31A in the related
art has a configuration different from the comparator 31 in FIG. 4
in the point that the external apply voltage Vext is applied to the
source electrodes of the transistors 61-3 and 61-4. That is, the
source electrodes of the transistors 61-3 and 61-4 are connected to
the external apply voltage generation circuit 71 (FIG. 8) in the
comparator 31A in the related art while the source electrodes of
the transistors 61-3 and 61-4 are commonly connected to the
vertical signal line 23 in the comparator 31 in FIG. 4.
[0105] In the comparator 31A in the related art, in the auto-zero
operation of the first-stage amplifier 81, the arbitrary external
apply voltage Vext generated in the external apply voltage
generation circuit 71 is directly input to the gate electrodes of
the transistors 61-6 and 61-7 that configure the first-stage
amplifier 81. In this way, the initial voltages of the internal
node Vramp_i and the internal node VSL_i are set.
[0106] In FIG. 10, the voltage waveform in the comparator 31A that
uses the external apply voltage generation circuit 71 is
illustrated. The operation timing chart of the comparator 31A is
similar to the timing chart of the comparator 31 described with
reference to FIG. 5.
[0107] First, by the auto-zero operation of the first-stage
amplifier 81, after the internal node Vramp_i and the internal node
VSL_i being set to apply voltage Vext, the internal node Vramp_i in
the gate electrode of the transistor 61-6 drops according to the
changing reference signal Vramp as illustrated in FIG. 5. Then, at
the voltage where the internal node Vramp_i and the internal node
VSL_i are matched, the amplifier outputs VOUT1 and VOUT2 are
inverted, and the D-phase conversion is performed.
[0108] Subsequently, in accordance with resetting of the FD unit 44
of the pixel 21, the reference signal Vramp is reset to the high
voltage level, and the reference signal Vramp is dropped again.
Then, at the voltage where the internal node Vramp_i and the
internal node VSL_i are matched again, the amplifier outputs VOUT1
and VOUT2 are inverted, and the P-phase conversion is
performed.
[0109] As illustrated in FIG. 10, in the comparator 31A in the
related art, the initial voltages of the internal node Vramp_i and
the internal node VSL_i are set by the external apply voltage Vext
in such a manner that the operating point in the D-phase conversion
and the operating point in the P-phase conversion at a high
illuminance and low illuminance are within the operating range of
the comparator. That is, in the comparator 31A in the related art,
by appropriately setting the external apply voltage Vext, the
internal voltage of the comparator circuit exceeding the operable
voltage range of the first-stage amplifier 81 described with
reference to FIG. 7 has been avoided.
[0110] However, in the imaging device, generally, the voltage
applied from the outside is the power source voltage and the
control signal for driving. For this reason, in order to set the
initial voltages of the internal node Vramp_i and the internal node
VSL_i by the external apply voltage Vext, the external apply
voltage generation circuit 71 (FIG. 8) for generating the external
apply voltage Vext is necessary in the imaging device. Furthermore,
since it is necessary that the external apply voltage Vext is set
(adjust) according to the output signal of the pixel 21 in such a
manner that the internal voltage fits within the operable voltage
range, a control circuit for performing such a setting is
necessary. Therefore, the power consumption in the imaging device
increases and the size of the imaging device increases.
[0111] In contrast, in the comparator 31 to which the present
technology is applied, it is possible to set the initial voltages
of the internal node Vramp_i and the internal node VSL_i to the
signal level of output signal VSL supplied via the vertical signal
line 23 as described above. In this way, since it is not necessary
to provide the external apply voltage generation circuit 71, it is
possible to achieve a reduction in power consumption and a
size.
[0112] In the comparator 31 to which the present technology is
applied, the initial voltages of the internal node Vramp_i and the
internal node VSL_i are automatically determined to be in the
operable voltage range of the first-stage amplifier 81. Therefore,
since it is not necessary to provide the control circuit for
setting the initial voltage, the simple configuration of the
comparator 31 can be realized.
[0113] Incidentally, in the driving illustrated in FIG. 6, the
output signal VSL is input via vertical signal line 23 to the
transistors 61-6 and 61-7 that configure the first-stage amplifier
81, and the internal node Vramp_i and the internal node VSL_i are
set to the same initial voltages. For this reason, a mismatch in
the differential amplifier is output as it is as the inversion
error of the comparator 31. As the column processing unit 17 in
FIG. 1, in the configuration in which a number of comparators 31
are disposed in parallel, the value of mismatch in the differential
amplifier becomes difficult to ignore as the resolution of the AD
conversion decreases. Therefore, it is necessary to solve the
problem of mismatch in the differential amplifier.
[0114] In FIG. 11, a timing chart in a second driving method of the
comparator 31 is illustrated.
[0115] First, at the point in time t31, the control signals x.phi.1
and x.phi.2 are shifted to the low level from the high level, and
the control signal .phi.5 is shifted to the high level from the low
level. At this time, the control signals x.phi.3 and x.phi.4 remain
at the high level. Accordingly, since an inverted control signal is
input to the transistors 61-1 and 61-2, the transistors 61-1 and
61-2 are in the ON state according to the control signals x.phi.1
and x.phi.2, respectively, and the transistor 61-5 is in the ON
state according to the control signal .phi.5. In this way, the
auto-zero operation of the post-stage amplifier 82 starts.
[0116] At the point in time t32, by the control signal .phi.5 being
shifted to the low level and the transistor 61-5 being in the OFF
state, the auto-zero operation of the post-stage amplifier 82 is
completed. Subsequently, only the control signals x.phi.1 are
shifted to the high level and the transistor 61-1 is in the OFF
state, and the control signal x.phi.2 remains at the low level.
[0117] Subsequently, at the point in time t33, the control signal
x.phi.3 is shifted to the low level from the high level.
Accordingly, since an inverted control signal is input to the
transistors 61-3, the transistors 61-3 is in the ON state according
to the control signal x.phi.3. At this time, since the control
signal x.phi.2 remains in the state of the low level, the
transistor 61-2 remains in the ON state. Accordingly, the auto-zero
operation of the first-stage amplifier 81 starts. At the point in
time t34, the control signals x.phi.2 and x.phi.3 being shifted to
the high level and the transistors 61-2 and 61-3 being in the OFF
state, and thus, the auto-zero operation of the first-stage
amplifier 81 is completed. Subsequently, during the period of the
time from t35 to t36, D-phase conversion is performed, and during
the period of the time from t37 to t38, P-phase conversion is
performed.
[0118] In this way, in the auto-zero operation of the comparator 31
in the second driving method, at the time of the auto-zero
operation of the first-stage amplifier 81 configured from
transistors 61-6 to 61-9, the transistors 61-2 and 61-3 are in the
ON state and transistors 61-1 and 61-4 are in the OFF state.
Therefore, the first-stage amplifier 81 comes to have a voltage
follower configuration in which the amplifier output VOUT1 and the
output signal VSL are in a feedback loop only during the auto-zero
operation of the first-stage amplifier 81. For this reason, a
voltage that compensates for the mismatch of the first-stage
amplifier 81 is kept in the condenser 51-2, and thus, it is
possible to suppress the inversion error in the comparator 31 due
to the mismatch such that the inversion error is decreased.
[0119] The difference between the first driving method and the
second driving method of the comparator 31 will be described with
reference to FIG. 12A and FIG. 12B.
[0120] In FIG. 12A, a state of performing the auto-zero operation
of the first-stage amplifier 81 in the first driving method of the
comparator 31 is illustrated, and in FIG. 12B, a state of
performing the auto-zero operation of the first-stage amplifier 81
in the second driving method of the comparator 31 is
illustrated.
[0121] As illustrated in FIG. 12A, in the auto-zero operation of
the first-stage amplifier 81 of the comparator 31 in the first
driving method, the transistors 61-3 and 61-4 are in the ON state.
For this reason, the mismatch .DELTA.Vth of the differential
amplifier appears as the inversion error .DELTA.Vt in the output
Vout of the comparator 31.
[0122] Meanwhile, as illustrated in FIG. 12B, in the auto-zero
operation of the first-stage amplifier 81 of the comparator 31 in
the second driving method, the transistors 61-2 and 61-3 are in the
ON state, and the voltage that compensates for the mismatch
.DELTA.Vth of the first-stage amplifier 81 is kept in the condenser
51-2. Therefore, it is possible to avoid the influence of the
mismatch .DELTA.Vth of the first-stage amplifier 81 to the output
Vout of the comparator 31.
[0123] Next, FIG. 13 is a circuit diagram illustrating a
configuration example of the comparator 31 to which the present
technology is adapted according to the second embodiment. In the
comparator 31B illustrated in FIG. 13, the configurations in common
with the comparator 31 in FIG. 4 will be referenced by the same
numerals, and the detailed descriptions will not be repeated.
[0124] That is, the comparator 31B has a configuration in common
with the comparator 31 in FIG. 4 in the point that the comparator
31B includes the condensers 51-1 to 51-3, the transistors 61-1 to
61-11, and the current source 62. The comparator 31B has a
different configuration from that of the comparator 31 in FIG. 4 in
the point that transistors 61-12 and 61-13 are added and the
external apply voltage Vext is supplied to the source electrodes of
the transistors 61-3 and 61-4. That is, in driving the comparator
31B, the external apply voltage generation circuit 71 illustrated
in FIG. 8 is used.
[0125] The transistor 61-12 is connected between the gate electrode
and the drain electrode of the transistor 61-8 and a control signal
x.phi.6 from the row scanning unit 15 (FIG. 1) is supplied to the
gate electrode of the transistor 61-12. The transistor 61-13 is
connected between the gate electrode and drain electrode of the
transistor 61-9, and a control signal x.phi.7 from the row scanning
unit 15 is supplied to the gate electrode of the transistor
61-13.
[0126] In the comparator 31B configured in this way, it is possible
to switch the connection of the gate electrodes of the transistors
61-8 and 61-9 which are active loads of the first-stage amplifier
81 to either of the drain electrode on both sides of the
differential amplifier by the transistors 61-12 and 61-13. That is,
it is possible to perform the driving of switching the connection
by the transistors 61-12 and 61-13 during the auto-zero operation
and during the D-phase conversion and P-phase conversion.
[0127] In FIG. 14, a diagram illustrating a timing chart of the
comparator 31B is illustrated.
[0128] In FIG. 14, from top to bottom in an order, the control
signal x.phi.1 for controlling the transistor 61-1, the control
signal x.phi.2 for controlling the transistor 61-2, the control
signal x.phi.3 for controlling the transistor 61-3, the control
signal x.phi.4 for controlling the transistor 61-4, the control
signal .phi.5 for controlling the transistor 61-5, the control
signal .phi.6 for controlling the transistor 61-12, the control
signal .phi.7 for controlling the transistor 61-13, the reference
signal Vramp for the reference in comparing the voltage level, and
the output signal VSL output from the pixel 21 to the vertical
signal line 23 are illustrated.
[0129] First, at the point in time t41 before performing the
auto-zero operation, the control signal .phi.6 is shifted to the
high level from the low level and the control signal .phi.7 is
shifted to the low level from the high level. Accordingly, since an
inverted control signal is input to the transistors 61-12 and
61-13, the transistors 61-12 is in the OFF state according to the
control signals x.phi.6 and the transistor 61-13 is in the ON state
according to the control signals x.phi.7. In this way, the gate
electrodes of the transistors 61-8 and 61-9 are connected to the
drain electrode of the transistor 61-9. Therefore, the amplifier
output VOUT1 output to the post-stage amplifier 82 is supplied to
the gate electrode of the transistors 61-8 and 61-9 which are the
active follower of the first-stage amplifier 81 via the transistor
61-13.
[0130] At the point in time t42, the control signal x.phi.1 and
x.phi.4 are shifted to the low level from the high level, and the
control signal .phi.5 is shifted to the high level from the low
level. At this time, the control signals x.phi.2 and x.phi.4 remain
at the high level. Accordingly, since an inverted control signal is
input to the transistors 61-1 and 61-4, the transistors 61-2 and
61-3 are in the ON state according to the control signals x.phi.1
and x.phi.4, respectively, and the transistor 61-5 is in the ON
state according to the control signal .phi.5. In this way, the
auto-zero operations of the post-stage amplifier 82 and the
first-stage amplifier 81 simultaneously start.
[0131] That is, the first-stage amplifier 81 comes to have the
voltage follower configuration in which the amplifier output VOUT0
by the transistors 61-6 and 61-8, and the internal node Vramp_i in
the gate electrode of the transistor 61-6 are in the feedback loop.
Here, since the connection of the transistor 61-9 which is the
active load of the first-stage amplifier 81 becomes a diode
connection, the amplifier output VOUT1 has a value in which the
threshold voltage Vthp of the PMOS transistor and the over drive
voltage .DELTA.V of the PMOS transistor are subtracted from the
power source voltage VDD, that is, VOUT1=VDD-Vthp-.DELTA.V.
[0132] Since the amplifier output VOUT1 here has a substantially
constant voltage without depending on the internal node VSL_i
(=VSL) of the first-stage amplifier 81, a voltage suitable for
performing the auto-zero operation of the post-stage amplifier 82
is supplied to the gate electrode of the transistor 61-11.
Therefore, it becomes possible that the auto-zero operation of the
post-stage amplifier 82 can be performed in parallel with the
auto-zero operation of the first-stage amplifier 81.
[0133] At the point in time t43, by the control signal .phi.5 being
shifted to low level and the transistor 61-5 being in the OFF
state, the auto-zero operation of the post-stage amplifier 82 is
completed. At the point in time t44, by the control signal x.phi.1
and x.phi.4 being shifted to the high level and the transistors
61-1 and 61-4 being in the OFF state, the auto-zero operation of
the first-stage amplifier 81 is completed. During the points in
time t43 to t45, the control signal .phi.6 is shifted to the low
level from the high level, and the control signal .phi.7 is shifted
to the high level from the low level. Accordingly, the gate
electrode of the transistors 61-8 and 61-9 are switched so as to be
connected to the drain electrode of the transistor 61-8.
Thereafter, during the points in time t45 to t46, D-phase
conversion is performed, and during the period of the points in
time t47 to t48, P-phase conversion is performed.
[0134] In this way, in the comparator 31B, the auto-zero operation
of the first-stage amplifier 81 and the auto-zero operation of the
post-stage amplifier 82 are performed in parallel, and thus it is
possible to complete the auto-zero operations at one time.
Therefore, it is possible for comparator 31B to increase the speed
of processing compared to the configuration in which it is
necessary to perform the auto-zero operation two times: the
auto-zero operation in the first-stage amplifier 81 and then in the
post-stage amplifier 82 as described with reference to FIG. 11, for
example.
[0135] Next, FIG. 15 is a circuit diagram illustrating a
configuration example of the comparator 31 to which the present
technology is adapted according to the third embodiment. In the
comparator 31C illustrated in FIG. 15, the configurations in common
with the comparator 31B in FIG. 13 will be referenced by the same
numerals, and the detailed descriptions will not be repeated.
[0136] That is, the comparator 31C has a configuration in common
with the comparator 31B in FIG. 13 in the point that the comparator
31C includes the condensers 51-1 to 51-3, the transistors 61-1 to
61-13, and the current source 62. The comparator 31C has a
different configuration from that of the comparator 31B in FIG. 13
in the point that the source electrode of the transistors 61-3 and
61-4 are connected to the vertical signal line 23, and has a
configuration in common with the comparator 31 in FIG. 4.
[0137] In this way, in the comparator 31C, the signal level of the
output signal VSL supplied via the vertical signal line 23 can be
set as the initial voltages of the internal node Vramp_i and the
internal node VSL_i in the D-phase first-read drive, as similar to
the comparator 31 in FIG. 4. That is, it is possible to configure
the comparator 31C so as to have a configuration in which the
external apply voltage generation circuit 71 (FIG. 8) is not
necessary while the comparator 31B in FIG. 13 has a configuration
in which the external apply voltage generation circuit 71 is
necessary.
[0138] The comparator 31C, as similar to the comparator 31B in FIG.
13, can operate according to the timing chart illustrated in FIG.
14. That is, the comparator 31C has a configuration to include the
transistors 61-12 and 61-13, and thus can perform the auto-zero
operations of the first-stage amplifier 81 and the auto-zero
operation of the post-stage amplifier 82 in parallel, as similar to
the comparator 31B in FIG. 13.
[0139] Therefore, in the comparator 31C, it is possible to achieve
a reduction in power consumption and a size since the external
power source is necessary, and to increase the speed by completing
the auto-zero operations at one time.
[0140] The comparator 31C has a configuration suitable for the
purpose of suppressing a gain error in the AD conversion
processing. Here, if the capacitance of the condenser 51-1 is C1
and the parasitic capacitance (a parasitic capacitance on wiring, a
gate capacitance of the transistor 61-6, a diffusion layer
capacitance of the transistor 61-1, and the like) to the internal
node Vramp_i of the first-stage amplifier 81 is Cp1, the amplitude
of the internal node Vramp_i attenuates at the rate of C1/(C1+Cp1)
with respect to the reference voltage Vramp (the amplitude
decreases). Similarly, if the capacitance of the condenser 51-2 is
C2 and the parasitic capacitance to the internal node VSL_i of the
first-stage amplifier 81 is Cp2, the attenuation rate of the output
signal VSL is C2/(C2+Cp2).
[0141] The capacitance C1 of the condenser 51-1, the capacitance C2
of the condenser 51-2, the parasitic capacitance Cp1 to the
internal node Vramp_i of the first-stage amplifier 81, and the
parasitic capacitance Cp2 to the internal node VSL_i of the
first-stage amplifier 81 depend on the film thickness of the gate
oxide film of the transistor 61, the inter-layer film thickness of
the metal layer, and the like. Therefore, since the attenuation
rate of the reference signal Vramp and the output signal VSL has a
uniform distribution in the chip or in the wafer surface, if a
difference between the internal node Vramp_i and the internal node
VSL_i in one comparator occurs, then the difference becomes the
gain error of the comparator. Particularly, in the structure of the
column processing unit 17 (FIG. 1) in which a multiple number of
comparators are arrayed in parallel, the difference causes a
shading of the image in the horizontal direction.
[0142] In contrast, the configuration of the comparator 31C adopts
a circuit configuration such that the configuration of the internal
node Vramp_i and the internal node VSL_i in the gate electrode of
the transistors 61-6 and 61-7 that configure the first-stage
amplifier 81 becomes bilaterally symmetrical. In this way, even if
the capacitance C1 of the condenser 51-1, the capacitance C2 of the
condenser 51-2, the parasitic capacitance Cp1 to the internal node
Vramp_i of the first-stage amplifier 81, and the parasitic
capacitance Cp2 to the internal node VSL_i of the first-stage
amplifier 81 have a uniform distribution on the surface, the
difference in local (in the same comparator) attenuation rate
between the reference signal Vramp and the output signal VSL is a
component of mismatch of each capacitance. Therefore, it is
possible to decrease the gain error of the comparator 31C in the
column processing unit 17.
[0143] In this way, in the comparator 31C, it is possible to
suppress the gain error in the AD conversion processing.
[0144] Next, FIG. 16 is a circuit diagram illustrating a
configuration example of a comparator 31 to which the present
technology is adapted according to the fourth embodiment. In the
comparator 31D illustrated in FIG. 16, the configurations in common
with the comparator 31C in FIG. 15 will be referenced by the same
numerals, and the detailed descriptions will not be repeated.
[0145] That is, the comparator 31D has a configuration in common
with the comparator 31C in FIG. 15 in the point that the comparator
31D includes the condensers 51-1 and 51-3, the transistors 61-1 and
61-5 to 61-13, and the current source 62. That is, the comparator
31D has a configuration in which the condenser 51-2 and transistors
61-2 to 61-4 are removed from the comparator 31C in FIG. 15.
[0146] In the comparator 31D configured in this way, the output
signal VSL is directly supplied to the transistor 61-7 via the
vertical signal line 23. Therefore, it is possible to configure the
comparator 31D so as to have a configuration in which the external
apply voltage generation circuit 71 is not necessary in the D-phase
first-read drive, as similar to the comparator 31 in FIG. 4.
[0147] The comparator 31D, as similar to the comparator 31B in FIG.
13, can drive according to the timing chart illustrated in FIG. 14.
That is, the comparator 31D has a configuration including the
transistors 61-12 and 61-13, and thus can perform the auto-zero
operations of the first-stage amplifier 81 and the auto-zero
operation of the post-stage amplifier 82 in parallel, as similar to
the comparator 31B in FIG. 13.
[0148] Therefore, in the comparator 31D, it is possible to achieve
a reduction in power consumption and a size since the external
power source is necessary, and to increase the speed by completing
the auto-zero operations at one time.
[0149] The comparator 31D has a configuration suitable for the
purpose of decreasing the circuit area. That is, the comparator
31D, as described above, has a configuration in which the condenser
51-2 and transistors 61-2 to 61-4 are removed from the
configuration of the comparator 31C.
[0150] In the configuration of the column processing unit 17 in
which a plural number of comparators 31 are arrayed in parallel,
and particularly, the ratio of the area occupied by the condenser
51-1 and 51-2 connected to the input terminal of the comparator 31
becomes comparatively large in the entire circuit of the column
processing unit 17. Therefore, by adopting configuration of the
comparator 31D to remove the condenser 51-2, it is possible to
contribute greatly to reducing the overall area of the solid-state
imaging device 11.
[0151] The comparator 31C in FIG. 15 and the comparator 31D in FIG.
16 can perform not only the D-phase first-read drive as described
above with reference to FIG. 3, but also the drive of reading the
D-phase (signal level) after reading the P-phase (reset level)
first (hereinafter, appropriately referred to as P-phase first-read
drive).
[0152] In FIG. 17, an internal voltage waveform of the comparator
31C or the comparator 31D in a case where the P-phase first-read
drive is performed is illustrated.
[0153] As illustrated in FIG. 17, in the P-phase first-read drive,
the initial voltages of the internal node Vramp_i and the internal
node VSL_i of the comparator 31C or the comparator 31D are
automatically determined according to the signal level of the
output signal VSL supplied via the vertical signal line 23.
Therefore, the range of the output signal VSL supplied via the
vertical signal line 23 automatically fits the operable range of
the comparator 31C or the comparator 31D, and the AD conversion can
be performed as normal.
[0154] In this way, in the comparator 31C or the comparator 31D,
the AD conversion can be performed by the same drive with respect
to both the D-phase first-read drive and the P-phase first-read
drive. Therefore, it is possible to simplify the drive control of
the comparator 31C or the comparator 31D.
[0155] The solid-state imaging device 11 as described above can be
adapted to various electronic apparatuses including, for example,
an imaging system such as a digital still camera and a digital
video camera, a mobile phone having an imaging function, or another
apparatus having an imaging function.
[0156] FIG. 18 is a block diagram illustrating a configuration
example of the imaging apparatus that is mounted on the electronic
apparatus.
[0157] As illustrated in FIG. 18, an imaging apparatus 101 is
configured to include an optical system 102, an imaging device 103,
a signal processing circuit 104, a monitor 105, and a memory 106,
and can capture a still image and a moving image.
[0158] The optical system 102 is configured to have one or a
plurality of lenses, and guides an image light (incident light)
from the subject to the imaging device 103, and forms an image on
the light receiving surface (sensor unit) of the imaging device
103.
[0159] As the imaging device 103, the solid-state imaging device 11
described above is adapted. In the imaging device 103, electrons
are accumulated according to the image formed on the light
receiving surface via the optical system 102 for a certain period.
Then, a signal according to the electrons accumulated in the
imaging device 103 is supplied to the signal processing circuit
104.
[0160] The signal processing circuit 104 implements various signal
processing with respect to the pixel signals output from the
imaging device 103. An image (image data) obtained by the signal
processing implemented by the signal processing circuit 104 is
supplied to the monitor 105 to be displayed or supplied to the
memory 106 to be stored (recorded).
[0161] In the imaging apparatus 101 configured in this way, by
adapting the configuration of the solid-state imaging device 11,
the decrease in power consumption and in the circuit size can be
achieved.
[0162] The present technology may also have a configuration as
follows.
[0163] (1) A comparator including: a first amplifying unit that
includes a differential pair configured with a pair of transistors
which are first and second transistors, and amplifies a difference
of signals input to each of the gate electrodes of the first and
second transistors, to output; a second amplifying unit that
amplifies the signal output from the first amplifying unit; a first
condenser that is disposed between a gate electrode of the first
transistor and a reference signal supply unit which supplies a
reference signal the voltage value of which drops at a constant
gradient; a second condenser that is disposed between a gate
electrode of the second transistor and a pixel signal wiring which
reads out a pixel signal from a pixel that outputs the pixel signal
having a signal level corresponding to charges generated by a
photoelectric conversion; a third transistor that connects a
connection point of the gate electrode of the first transistor and
the first condenser to the pixel signal wiring; and a fourth
transistor that connects a connection point of the gate electrode
of the second transistor and the second condenser to the pixel
signal wiring.
[0164] (2) The comparator according to (1), in which, in a case
where a drive of reading out a pixel signal having a reset level is
performed, in which the charges are reset after the reading out of
the pixel signal having the signal level from the pixel first, when
the auto-zero operation of the first amplifying unit for setting an
initial voltage in the first amplifying unit circuit is performed,
a voltage of a pixel signal supplied via the pixel signal wiring is
supplied to each of the gate electrodes of the first and the second
transistors, with the third and the fourth transistors being in the
ON state.
[0165] (3) The comparator according to any one of (1) or (2),
further including: a fifth transistor that connects the first
transistor to a power source voltage; a sixth transistor that
connects the second transistor to the power source voltage; a
seventh transistor that connects the gate electrode of the first
transistor to a connection point of the first transistor and the
fifth transistor; and an eighth transistor that connects the gate
electrode of the second transistor to a connection point of the
second transistor and the sixth transistor, in which, in a case
where a drive of reading out a pixel signal having a reset level in
which the charges are reset is performed after firstly the reading
out the pixel signal having the signal level from the pixel first,
when the auto-zero operation by the first amplifying unit is
performed, the voltage of the pixel signal supplied via the pixel
signal wiring is supplied to each gate of the gate electrodes of
the first and the second transistors, with the third and the eighth
transistors being in the ON state.
[0166] (4) The comparator according to any one of (1) to (3),
further including: a fifth transistor that connects the first
transistor to a power source voltage; a sixth transistor that
connects the second transistor to the power source voltage; a ninth
transistor that connects a connection point of gate electrodes of
the fifth transistor and the sixth transistor to a drain of the
fifth transistor; and a tenth transistor that connects a connection
point of gate electrodes of the fifth transistor and the sixth
transistor to a drain of the sixth transistor.
[0167] (5) The comparator according to (4), in which auto-zero
operations of the first amplifying unit and the second amplifying
unit are performed in parallel.
[0168] (6) The comparator according to (4), in which the connection
by the ninth transistor and the tenth transistor is switched to any
of the connections to the drain of the fifth transistor or to a
drain of the sixth transistor, during a period of performing the
auto-zero operations of the first amplifying unit and the second
amplifying in parallel and during a period of converting the pixel
signal having the signal level to a digital signal and converting
the pixel signal having the reset level to the digital signal.
[0169] It should be understood by those skilled in the art that
various modifications, combinations, sub-combinations and
alterations may occur depending on design requirements and other
factors insofar as they are within the scope of the appended claims
or the equivalents thereof.
* * * * *