U.S. patent application number 14/422410 was filed with the patent office on 2015-08-20 for array substrate, display panel and display device.
This patent application is currently assigned to BOE TECHNOLOGY GROUP CO., LTD. The applicant listed for this patent is BEIJING BOE DISPLAY TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.. Invention is credited to Jieqiong Wang.
Application Number | 20150235601 14/422410 |
Document ID | / |
Family ID | 49244591 |
Filed Date | 2015-08-20 |
United States Patent
Application |
20150235601 |
Kind Code |
A1 |
Wang; Jieqiong |
August 20, 2015 |
ARRAY SUBSTRATE, DISPLAY PANEL AND DISPLAY DEVICE
Abstract
The present disclosure provides an array substrate, a display
panel and a display device. The array substrate includes: a
plurality of data lines and a plurality of gate lines configured to
divide a display region into a plurality of display sub-regions; a
pixel electrode arranged at each display sub-region; and a TFT
arranged at each display sub-region, a source electrode of the TFT
being electrically connected to the data line, a drain electrode
thereof being electrically connected to the pixel electrode and a
gate electrode thereof being electrically connected to the gate
line, wherein a parasitic capacitor is formed between the gate
electrode and the drain electrode of the TFT. The array substrate
further includes a switch circuit configured to enable both ends of
the parasitic capacitor to be electrically connected when a gate
driving signal of the TFT is changed from a high level to a low
level.
Inventors: |
Wang; Jieqiong; (Beijing,
CN) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
BOE TECHNOLOGY GROUP CO., LTD.
BEIJING BOE DISPLAY TECHNOLOGY CO., LTD. |
BEIJING
BEIJING |
|
CN
CN |
|
|
Assignee: |
BOE TECHNOLOGY GROUP CO.,
LTD
BEIJING
CN
BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.
BEIJING
CN
|
Family ID: |
49244591 |
Appl. No.: |
14/422410 |
Filed: |
December 17, 2013 |
PCT Filed: |
December 17, 2013 |
PCT NO: |
PCT/CN2013/089660 |
371 Date: |
February 19, 2015 |
Current U.S.
Class: |
345/690 ;
345/89 |
Current CPC
Class: |
G02F 2001/13606
20130101; G09G 2320/0233 20130101; G09G 3/3655 20130101; G02F
1/13624 20130101; G09G 3/3607 20130101; G09G 2300/0876 20130101;
G09G 2300/0819 20130101 |
International
Class: |
G09G 3/36 20060101
G09G003/36 |
Foreign Application Data
Date |
Code |
Application Number |
Jul 1, 2013 |
CN |
201310271807.4 |
Claims
1. An array substrate, comprising: a plurality of data lines and a
plurality of gate lines, configured to divide a display region into
a plurality of display sub-regions; a pixel electrode arranged at
each display sub-region; and a TFT arranged at each display
sub-region, a source electrode of the TFT being electrically
connected to the data line, a drain electrode of the TFT being
electrically connected to the pixel electrode and a gate electrode
of the TFT being electrically connected to the gate line, wherein a
parasitic capacitor is formed between the gate electrode and the
drain electrode of the TFT, and the array substrate further
comprises: a switch circuit configured to enable both ends of the
parasitic capacitor to be electrically connected when a gate
driving signal of the TFT is changed from a high level to a low
level.
2. The array substrate according to claim 1, wherein the switch
circuit comprises: a first switch unit arranged at at least one
display sub-region, and connected in parallel to the parasitic
capacitor formed on the TFT at the corresponding display
sub-region, wherein one end of a parallel circuit formed by the
parasitic capacitor and the first switch unit is electrically
connected to the drain electrode of the TFT, and another end of the
parallel circuit is electrically connected to the gate electrode of
the TFT, and the first switch unit is in an ON state when the gate
driving signal of the TFT at the corresponding display sub-region
is changed from a high level to a low level, and otherwise the
first switch unit is in an OFF state.
3. The array substrate according to claim 2, wherein an external
controller is used to control the first switch unit to be in the ON
state when the gate driving signal is changed from a high level to
a low level, and otherwise control the first switch unit to be in
the OFF state.
4. The array substrate according to claim 3, wherein the external
controller is provided with respect to each row of gate lines, and
a signal from the external controller is in synchronization with
the gate driving signal of the corresponding gate line.
5. The array substrate according to claim 4, wherein the first
switch unit is a TFT element, a gate electrode of which is
connected to the external controller, a source electrode of which
is connected to the gate electrode of the TFT, and a drain
electrode of which is connected to the drain electrode of the
TFT.
6. The array substrate according to claim 1, wherein the switch
circuit comprises: a first switch unit arranged at at least one
display sub-region, and connected in parallel to the parasitic
capacitor formed on the TFT at the corresponding display
sub-region; and a second switch unit arranged in correspondence
with the first switch unit, wherein one end of a parallel circuit
formed by the parasitic capacitor and the first switch unit is
electrically connected to the drain electrode of the TFT, and
another end of the parallel circuit is electrically connected to
the gate electrode of the TFT via the second switch unit, and the
first switch unit is in the ON state and the second switch unit is
in the OFF state when the gate driving signal of the TFT at the
corresponding display sub-region is changed from a high level to a
low level.
7. The array substrate according to claim 6, wherein the first
switch element is a first TFT which is in an OFF state when its
gate electrode is at a high level, the second switch unit is a
second TFT which is in an ON state when its gate electrode is at a
high level, and the gate electrodes of the first TFT and the second
TFT are electrically connected to the gate line.
8. The array substrate according to claim 6, wherein an external
controller is provided with respect to each row of gate lines, a
signal from the external controller is in synchronization with the
gate driving signal of the corresponding gate lines, the first
switch unit is a first TFT which is in an OFF state when its gate
electrode is at a high level, the second switch unit is a second
TFT which is in an ON state when its gate electrode is at a high
level, and the gate electrodes of the first TFT and the second TFT
are electrically connected to the external controller.
9. A display panel comprising the array substrate according to
claim 1.
10. A display device comprising the display panel according to
claim 9.
11. The display panel according to claim 9, wherein the switch
circuit comprises: a first switch unit arranged at at least one
display sub-region, and connected in parallel to the parasitic
capacitor formed on the TFT at the corresponding display
sub-region, wherein one end of a parallel circuit formed by the
parasitic capacitor and the first switch unit is electrically
connected to the drain electrode of the TFT, and another end of the
parallel circuit is electrically connected to the gate electrode of
the TFT, and the first switch unit is in an ON state when the gate
driving signal of the TFT at the corresponding display sub-region
is changed from a high level to a low level, and otherwise the
first switch unit is in an OFF state.
12. The display panel according to claim 10, wherein an external
controller is used to control the first switch unit to be in the ON
state when the gate driving signal is changed from a high level to
a low level, and otherwise control the first switch unit to be in
the OFF state.
13. The display panel according to claim 11, wherein the external
controller is provided with respect to each row of gate lines, and
a signal from the external controller is in synchronization with
the gate driving signal of the corresponding gate line.
14. The display panel according to claim 12, wherein the first
switch unit is a TFT element, a gate electrode of which is
connected to the external controller, a source electrode of which
is connected to the gate electrode of the TFT, and a drain
electrode of which is connected to the drain electrode of the
TFT.
15. The display panel according to claim 9, wherein the switch
circuit comprises: a first switch unit arranged at at least one
display sub-region, and connected in parallel to the parasitic
capacitor formed on the TFT at the corresponding display
sub-region; and a second switch unit arranged in correspondence
with the first switch unit, wherein one end of a parallel circuit
formed by the parasitic capacitor and the first switch unit is
electrically connected to the drain electrode of the TFT, and
another end of the parallel circuit is electrically connected to
the gate electrode of the TFT via the second switch unit, and the
first switch unit is in the ON state and the second switch unit is
in the OFF state when the gate driving signal of the TFT at the
corresponding display sub-region is changed from a high level to a
low level.
16. The display panel according to claim 14, wherein the first
switch element is a first TFT which is in an OFF state when its
gate electrode is at a high level, the second switch unit is a
second TFT which is in an ON state when its gate electrode is at a
high level, and the gate electrodes of the first TFT and the second
TFT are electrically connected to the gate line.
17. The display panel according to claim 14, wherein an external
controller is provided with respect to each row of gate lines, a
signal from the external controller is in synchronization with the
gate driving signal of the corresponding gate lines, the first
switch unit is a first TFT which is in an OFF state when its gate
electrode is at a high level, the second switch unit is a second
TFT which is in an ON state when its gate electrode is at a high
level, and the gate electrodes of the first TFT and the second TFT
are electrically connected to the external controller.
Description
TECHNICAL FIELD
[0001] The present disclosure relates to the field of display
technology, in particular to an array substrate, a display panel
and a display device.
BACKGROUND
[0002] A liquid crystal display device has currently been widely
used as a flat-panel display device due to such advantages as low
power consumption, being light and free of radiation as compared
with the other display devices.
[0003] Usually, the liquid crystal display device includes an array
substrate, a color filter substrate and a liquid crystal layer. As
shown in FIG. 1, a display region on the array substrate includes a
plurality of display sub-regions, and each display sub-region is
usually surrounded by two gate lines 101 (scanning lines) and two
data lines 102.
[0004] As shown in FIG. 1, a thin film transistor (TFT) 103 and a
pixel electrode 104 are arranged inside the display sub-region. A
voltage applied to a common electrode and/or the pixel electrode
104 on the color filter substrate may be controlled so as to
control an intensity of an electric field between the color filter
substrate and the array substrate, thereby to control a deflection
direction of liquid crystal molecules.
[0005] During the operation, the TFT is turned on under the control
of a gate driving signal, and a data voltage at a corresponding row
is applied to the corresponding pixel electrode 104 by a source
electrode, so as to change the intensity of the electric field
between the color filter substrate and the array substrate, thereby
to affect the deflection of the liquid crystal molecules.
[0006] However, in the array substrate, a gate electrode 1031 and a
drain electrode 1032 of the TFT 103 are arranged opposite to each
other at some regions, and when a voltage between the gate
electrode 1031 and the drain electrode 1032 changes, a parasitic
capacitor C.sub.gd will occur. FIG. 1 shows its equivalent
circuit.
[0007] At a moment when the voltage applied to the gate electrode
is changed from a turn-on voltage V.sub.gh to a turn-off voltage
V.sub.gl, charges inside the parasitic capacitor C.sub.gd will move
due to a sudden change in the voltage applied to the gate
electrode. Once the charges move, a voltage across C.sub.gd will be
changed. The change of the voltage will be transferred to the pixel
electrode 104 via the drain electrode, resulting in a change in the
intensity of the electric field between the color filter substrate
and the array substrate, and thereby resulting in a change in a
deflection angle of the liquid crystal molecules. As a result, the
transmittance will be adversely affected and thereby the grayscale
display of an image will be inaccurate.
SUMMARY
[0008] An object of the present disclosure is to provide an array
substrate, a display panel and a display device, so as to reduce
the influence of a parasitic capacitor between a gate electrode and
a drain electrode on the display.
[0009] In one aspect, the present disclosure provides an array
substrate, including:
[0010] a plurality of data lines and a plurality of gate lines,
configured to divide a display region into a plurality of display
sub-regions;
[0011] a pixel electrode arranged at each display sub-region;
and
[0012] a TFT arranged at each display sub-region, a source
electrode of the TFT being electrically connected to the data line,
a drain electrode of the TFT being electrically connected to the
pixel electrode and a gate electrode of the TFT being electrically
connected to the gate line.
[0013] A parasitic capacitor is formed between the gate electrode
and the drain electrode of the TFT. The array substrate further
includes a switch circuit configured to enable both ends of the
parasitic capacitor to be electrically connected when a gate
driving signal of the TFT is changed from a high level to a low
level.
[0014] In the array substrate, the switch circuit may include:
[0015] a first switch unit arranged at at least one display
sub-region, and connected in parallel to the parasitic capacitor
formed on the TFT at the corresponding display sub-region,
[0016] wherein one end of a parallel circuit formed by the
parasitic capacitor and the first switch unit is electrically
connected to the drain electrode of the TFT, and another end of the
parallel circuit is electrically connected to the gate electrode of
the TFT, and
[0017] the first switch unit is in an ON state when the gate
driving signal of the TFT at the corresponding display sub-region
is changed from a high level to a low level, and otherwise the
first switch unit is in an OFF state.
[0018] In the array substrate, an external controller may be used
to control the first switch unit to be in the ON state when the
gate driving signal is changed from a high level to a low level,
and otherwise control the first switch unit to be in the OFF
state.
[0019] In the array substrate, the external controller may be
provided with respect to each row of gate lines, and a signal from
the external controller may be in synchronization with the gate
driving signal of the corresponding gate line.
[0020] In the array substrate, the first switch unit may be a TFT
element, a gate electrode of which is connected to the external
controller, a source electrode of which is connected to the gate
electrode of the TFT, and a drain electrode of which is connected
to the drain electrode of the TFT.
[0021] In the array substrate, the switch circuit may include:
[0022] a first switch unit arranged at at least one display
sub-region, and connected in parallel to the parasitic capacitor
formed on the TFT at the corresponding display sub-region; and
[0023] a second switch unit arranged in correspondence with the
first switch unit,
[0024] wherein one end of a parallel circuit formed by the
parasitic capacitor and the first switch unit is electrically
connected to the drain electrode of the TFT, and another end of the
parallel circuit is electrically connected to the gate electrode of
the TFT via the second switch unit, and
[0025] the first switch unit is in an ON state and the second
switch unit is in an OFF state when the gate driving signal of the
TFT at the corresponding display sub-region is changed from a high
level to a low level.
[0026] In the array substrate, the first switch element may be a
first TFT which is in an OFF state when its gate electrode is at a
high level, the second switch unit may be a second TFT which is in
an ON state when its gate electrode is at a high level, and the
gate electrodes of the first TFT and the second TFT are
electrically connected to the gate line.
[0027] In the array substrate, an external controller may be
provided with respect to each row of gate lines, and a signal from
the external controller may be in synchronization with the gate
driving signal of the corresponding gate line. The first switch
unit may be a first TFT which is in an OFF state when its gate
electrode is at a high level, the second switch unit may be a
second TFT which is in an ON state when its gate electrode is at a
high level, and the gate electrodes of the first TFT and the second
TFT are electrically connected to the external controller.
[0028] In another aspect, the present disclosure provides a display
panel including the above-mentioned array substrate.
[0029] In yet another aspect, the present disclosure provides a
display device including the above-mentioned display panel.
[0030] The present disclosure at least has the following
advantageous effects. Due to the existence of the switch circuit,
both ends of the parasitic capacitor will be electrically connected
when the gate driving signal of the TFT is changed from a high
level to a low level. Once both ends of the parasitic capacitor are
electrically connected, they will be at an identical potential. In
this case, the parasitic capacitor will be neither discharged nor
charged, i.e., charges will not move within the parasitic
capacitor. Because the parasitic capacitor will not be affected
when the gate driving signal of the TFT is changed from a high
level to a low level, no influence will be impacted on voltages
applied to the drain electrode and the pixel electrode electrically
connected to the drain electrode, i.e., the pixel electrode may be
maintained at a voltage after a charging. As a result, it is able
to reduce the influence of the parasitic capacitor between the gate
electrode and the drain electrode on the voltage of the pixel
electrode, thereby to improve a display effect.
BRIEF DESCRIPTION OF THE DRAWINGS
[0031] FIG. 1 is an equivalent circuit diagram of an existing array
substrate;
[0032] FIG. 2 is an equivalent circuit diagram of an array
substrate according to an embodiment of the present disclosure;
and
[0033] FIG. 3 is another equivalent circuit diagram according to an
embodiment of the present disclosure.
DETAILED DESCRIPTION
[0034] According to an array substrate, a display panel and a
display device of the present disclosure, a switch circuit is
provided so as to enable both ends of a parasitic capacitor to be
electrically connected when a gate driving signal of a TFT is
changed from a high level to a low level, so that such a phenomenon
as charge movement will not occur within the parasitic capacitor.
As a result, it is able to reduce the influence of the parasitic
capacitor between a gate electrode and a drain electrode on a
voltage across a pixel electrode, thereby to improve a display
effect.
[0035] An array substrate in an embodiment of the present
disclosure includes:
[0036] a plurality of data lines and a plurality of gate lines
configured to divide a display region into a plurality of display
sub-regions;
[0037] a pixel electrode arranged at each display sub-region;
and
[0038] a TFT arranged at each display sub-region, a source
electrode of the TFT being electrically connected to the data line,
a drain electrode thereof being electrically connected to the pixel
electrode and a gate electrode thereof being electrically connected
to the gate line.
[0039] A parasitic capacitor is formed between the gate electrode
and the drain electrode of the TFT. The array substrate further
includes a switch circuit configured to enable both ends of the
parasitic capacitor to be electrically connected when a gate
driving signal of the TFT is changed from a high level to a low
level.
[0040] According to the array substrate in this embodiment, due to
the existence of the switch circuit, both ends of the parasitic
capacitor will be electrically connected when the gate driving
signal of the TFT is changed from a high level to a low level. Once
both ends of the parasitic capacitor are electrically connected,
they will be at an identical potential. In this case, the parasitic
capacitor will be neither discharged nor charged, i.e., charges
will not move within the parasitic capacitor.
[0041] As mentioned above, because the parasitic capacitor will not
be affected when the gate driving signal of the TFT is changed from
a high level to a low level, no influence will be impacted on
voltages applied to the drain electrode and the pixel electrode
electrically connected to the drain electrode, i.e., the pixel
electrode which has been charged will be maintained at a voltage.
As a result, it is able to reduce the influence of the parasitic
capacitor between the gate electrode and the drain electrode on the
voltage across the pixel electrode, thereby to improve a display
effect.
[0042] In specific embodiments, the switch circuit may be
implemented in various modes, and some of them will be described
hereinafter.
[0043] <Implementation Mode 1 for Switch Circuit>
[0044] In this mode, the switch circuit may be implemented by
merely one switch unit. As shown in FIG. 2, the switch circuit
includes a first switch unit 201 arranged at at least one display
sub-region. Both ends of the first switch unit 201 are connected to
two ends of the parasitic capacitor C.sub.gd formed on the TFT at
the corresponding display sub-region, respectively, and an ON state
and an OFF state of the first switch unit 201 are controlled by
means of an external controller (not shown).
[0045] The parasitic capacitor C.sub.gd and the first switch unit
201 form a parallel circuit 200, one end of which is electrically
connected to a drain electrode 1032 of a TFT 103, and another end
of which is electrically connected to a gate electrode 1031 of the
TFT 103.
[0046] When the gate driving signal of the TFT at the corresponding
display sub-region is changed from a high level to a low level,
i.e., within a time period in which the gate driving signal is
changed from a high level to a low level until it is stabilized at
the low level, the external controller is used to control the first
switch unit 201 to be in the ON state; and within a time period
other than the above-mentioned time period, the external controller
is used to control the first switch unit 201 to be in the OFF
state.
[0047] In addition, one external controller may be provided with
respect to each row of gate lines, and a signal from the external
controller may be in synchronization with the gate driving signal
of the corresponding gate line.
[0048] As shown in FIG. 2, the first switch unit 201 may be a TFT
element, a gate electrode of which is connected to the external
controller, a source electrode of which is connected to the gate
electrode 1031 of the TFT 103, and a drain electrode of which is
connected to the drain electrode 1032 of the TFT 103, or any other
switch element.
[0049] In this mode, when the gate driving signal is changed from a
high level to a low level, the first switch unit will be in the ON
state. At this time, both ends of the parasitic capacitor C.sub.gd
will be electrically connected and at an identical potential, so
that the parasitic capacitor will be neither discharged nor
charged. Therefore, a change in the level of the gate driving
signal will not be transferred to the pixel electrode via the
parasitic capacitor C.sub.gd, thus the voltage across the pixel
electrode which has been charged will not be changed, and an
electric field between the pixel electrode and the common electrode
will remain unchanged. As a result, it is able to achieve accurate
grayscale display at the display sub-region, thereby to improve a
display effect.
[0050] <Implementation Mode 2 for Switch Circuit>
[0051] In the above mode 1, it is required to control the first
switch unit 201 to be in the ON state merely within the time period
when the gate driving signal is changed from a high level to a low
level until it is stabilized at the low level, and to control the
first switch unit 201 to be in the OFF state within a time period
other than the above-mentioned time period. Brief explanation will
be given as follows.
[0052] Taking the structure in FIG. 2 as an example, when the gate
driving signal is at a high level, it will be applied to the pixel
electrode if the first switch unit 201 is in the ON state, and the
pixel electrode will be thus charged wrongly. When the gate driving
signal is at a low level, it will be applied to the pixel electrode
if the first switch unit 201 is in the ON state, and the pixel
electrode will thus be discharged.
[0053] Hence, the first switch unit 201 can merely be in the ON
state within the time period in which the gate driving signal is
changed from a high level to a low level until it is stabilized at
the low level, but must be in the OFF state within the other time
period.
[0054] It can be found that, there is a high requirement on control
accuracy of the first switch unit in the mode 1, i.e., on control
accuracy of the external controller; otherwise, the voltage across
the pixel electrode may be changed inappropriately.
[0055] In order to reduce the control accuracy, in an embodiment as
shown in FIG. 3, the switch circuit in the mode 2 includes the
first switch unit 201 arranged at at least one display sub-region,
and a second switch unit 202 arranged in correspondence with the
first switch unit. Both ends of the first switch unit 201 are
connected to two ends of the parasitic capacitor C.sub.gd formed on
the TFT at the corresponding display sub-region, respectively. How
to control the ON and OFF states of the first switch unit 201 will
be described later.
[0056] The parasitic capacitor C.sub.gd and the first switch unit
201 form the parallel circuit 200, one end of which is electrically
connected to the drain electrode 1032 of the TFT 103, and another
end of which is electrically connected to the gate electrode 1031
of the TFT 103 via the second switch unit 202. In other words, one
end of the second switch unit 202 is electrically connected to one
end of the parallel circuit 200, and another end thereof is
electrically connected to the gate electrode 1031 of the TFT. How
to control ON and OFF states of the second switch unit 202 will be
described later. When the gate driving signal of the TFT at the
corresponding display sub-region is changed from a high level to a
low level, i.e., within the time period in which the gate driving
signal is changed from a high level to a low level until it is
stabilized at the low level, the first switch unit 201 will be in
the ON state and the second switch unit 202 will be in the OFF
state. When the gate driving signal of the TFT at the corresponding
display sub-region is at a high level, i.e., within a time period
in which the gate driving signal is at a high level, the second
switch unit 202 will be in the ON state, and the first switch unit
201 will be in the OFF state.
[0057] In the mode 2, when the gate driving signal is changed from
a high level to a low level, the first switch unit 201 will be in
the ON state, and the second switch unit 202 will be in the OFF
state. At this time, the gate driving signal will not be
transferred to the pixel electrode, and thus the pixel electrode
will not be adversely affected. In addition, when the first switch
unit 201 is in the ON state, both ends of the parasitic capacitor
C.sub.gd will be electrically connected and at an identical
potential, so the parasitic capacitor will be neither discharged
nor charged. A change in the level of the gate driving signal will
not be transferred to the pixel electrode via the parasitic
capacitor C.sub.gd, thus the voltage of the pixel electrode which
has been charged will not be changed, and an electric field between
the pixel electrode and the common electrode will remain unchanged.
As a result, it is able to achieve accurate grayscale display at
the display sub-region, thereby to improve the display effect.
[0058] When the gate driving signal of the TFT at the corresponding
display sub-region is at a high level, the second switch unit 202
is controlled to be in the ON state, and the first switch unit 201
is controlled to be in the OFF state. At this time, an actual
equivalent circuit is just that shown in FIG. 1, and the entire
array substrate will operate normally.
[0059] According to this mode, it is able to perform the control in
a simpler and more flexible manner as compared with the circuit as
shown in FIG. 2.
[0060] The switch circuit in FIG. 3 may be controlled in two modes.
In a first control mode, one external controller may be provided
with respect to each row of gate lines separately, and a signal
from the external controller may be in synchronization with the
gate driving signal of the corresponding gate line. As shown in
FIG. 3, the first switch unit is a first TFT which is in the OFF
state when the gate electrode is at a high level, the second switch
unit is a second TFT which is in the ON state when the gate
electrode is at the high level, the gate electrodes of the first
TFT and the second TFT are connected to the external controller,
and the signal from the external controller is in synchronization
with the gate driving signal.
[0061] In this mode, because a control signal is in synchronization
with, i.e., identical to, the gate driving signal, it will be at a
high level when the gate driving signal is at a high level. The
first TFT (i.e., the first switch unit 201) is in the OFF state,
and the second TFT (i.e., the second switch unit 202) is in the ON
state. At this time, the circuit structure as shown in FIG. 1 will
be obtained, and the array substrate will operate normally.
[0062] When the gate driving signal jumps from a high level, the
control signal will jump too. Hence, the first TFT (i.e., the first
switch unit 201) is in the ON state and the second TFT (i.e., the
second switch unit 202) is in the OFF state. At this time, both
ends of the parasitic capacitor are electrically connected, so as
to prevent the charges within the parasitic capacitor from moving,
thereby to maintain an electric field between the pixel electrode
and the common electrode to be unchanged.
[0063] When the gate driving signal is at a low level, the control
signal will be at a low level too. Hence, the first TFT (i.e., the
first switch unit 201) is in the ON state and the second TFT (i.e.,
the second switch unit 202) is in the OFF state. At this time, the
gate driving signal at the low level will not be outputted to the
pixel electrode via the second switch unit. At a maintenance stage,
the voltage of the pixel electrode will not be changed, and the
array substrate will operate normally.
[0064] In a second control mode, the switch circuit in FIG. 3 may
also be controlled directly by the gate driving signal, so this
mode will be simpler. In this mode, the first switch unit is a
first TFT which is in the OFF state when its gate electrode is at a
high level, the second switch is a second TFT which is in the ON
sate when its gate electrode is at a high level, and the gate
electrodes of the first TFT and the second TFT are electrically
connected to the gate line.
[0065] This control mode differs from the first control mode merely
in the control signal, and the operating modes are completely the
same, which will thus not be repeated herein.
[0066] The present disclosure further discloses in an embodiment a
display panel including the above-mentioned array substrate.
[0067] The present disclosure further discloses in an embodiment a
display device including the above-mentioned display panel. The
display panel may be any product or member having a display
function, e.g., a liquid crystal panel, an electronic paper, an
OLED panel, a mobile phone, a flat-panel PC, a TV, a display, a
laptop PC, a digital photo frame, and a navigator.
[0068] The above are merely the preferred embodiments of the
present disclosure. It should be appreciated that, a person skilled
in the art may make further improvements and modifications without
departing from the principle of the present disclosure, and these
improvements and modifications shall also fall within the scope of
the present disclosure.
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