U.S. patent application number 14/665429 was filed with the patent office on 2015-07-09 for capacitively coupled logic gate.
The applicant listed for this patent is David K.Y. Liu. Invention is credited to David K.Y. Liu.
Application Number | 20150194965 14/665429 |
Document ID | / |
Family ID | 45806069 |
Filed Date | 2015-07-09 |
United States Patent
Application |
20150194965 |
Kind Code |
A1 |
Liu; David K.Y. |
July 9, 2015 |
CAPACITIVELY COUPLED LOGIC GATE
Abstract
An electronic logic circuit uses areal capacitive coupling
devices coupled together to process a set of data inputs. Each
areal capacitive coupling device can be configured such that a
floating gate potential of such device can be altered to at least a
first state or a second state in response to receiving an input
signal from the set of data inputs, which is coupled electrically
to the floating gate. A majority function logic circuit (and other
similar circuits) can be interconnected this way using far fewer
gates than with a conventional CMOS implementation. Selective logic
gates can also be enabled or disabled by configuring them
effectively as memory devices.
Inventors: |
Liu; David K.Y.; (Fremont,
CA) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Liu; David K.Y. |
Fremont |
CA |
US |
|
|
Family ID: |
45806069 |
Appl. No.: |
14/665429 |
Filed: |
March 23, 2015 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
13233767 |
Sep 15, 2011 |
8988103 |
|
|
14665429 |
|
|
|
|
61383128 |
Sep 15, 2010 |
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Current U.S.
Class: |
326/35 ;
326/38 |
Current CPC
Class: |
H03K 19/23 20130101;
H01L 27/11803 20130101; H01L 27/11517 20130101; H03K 19/173
20130101 |
International
Class: |
H03K 19/23 20060101
H03K019/23; H03K 19/173 20060101 H03K019/173 |
Claims
1. An electronic logic circuit comprising: a plurality of two
terminal areal capacitive coupling gates coupled to process a set
of data inputs; each two terminal areal capacitive coupling gate
being a single gate configured such that a voltage potential of a
floating gate of such single gate can be altered in response to
receiving a single input signal from said set of data inputs, said
floating gate being configured to place said two terminal areal
capacitive coupling gate into a first state or a second state
through areal capacitive coupling to a potential associated with a
first active region of such gate receiving said single input
signal; each two terminal areal capacitive coupling gate further
being configured by a function select signal to be on or off so as
to enable the electronic logic circuit to process and implement a
majority function operation with a selected subset of two terminal
areal capacitive coupling gates for a selected subset of is said
set of data inputs; an output of each of said selected subset of
two terminal areal capacitive coupling gates being related to said
first state or said second state, such that a plurality of separate
selected outputs can be generated by said selected subset of two
terminal areal capacitive gates; and an output of each two terminal
areal capacitive coupling gate of said selected subset of two
terminal areal capacitive coupling gates being related to said
first state or said second state, and said selected subset of
interconnected two terminal areas capacitive gates being configured
to generate a plurality of separate outputs from a plurality of
separate ones of said set of data inputs; wherein said plurality of
separate outputs of said plurality of interconnected two terminal
areal capacitive coupling gates process separate single ones of
said set of data inputs and effectuate a collective output
corresponding to a logic function implemented for said selected
subset set of data inputs.
2. The logic circuit of claim 1, wherein said logic function is a
majority gate function implemented on a limited variable number of
a maximum number of inputs to said logic circuit.
3. The logic circuit of claim 1, wherein said two terminal areal
capacitive coupling gates operate using channel hot electron
injection.
4. The logic circuit of claim 1, wherein said function select
signal is hardwired by an electrical connection to an interconnect
mask.
5. A method of operating a logic circuit using a dual function
electronic logic gate which is a single gate that employs areal
capacitive coupling between a source/drain region and a floating
gate comprising: a. enabling the single gate to perform a first
circuit function within the is logic circuit when a first selection
voltage is applied to an input terminal of the device coupled to
said source/drain region; b. enabling the single gate to perform a
second circuit function within the logic circuit when a second
selection voltage is applied to said input terminal; wherein the
first circuit function is a memory function, and second circuit
function is a switching function; wherein the dual function
electronic logic gate only participates in a logic function
implemented by the logic circuit when configured to perform said
first circuit function; and further wherein the first input voltage
effectuating a memory function for the dual function electronic
logic gate is substantially higher than said second input voltage
effectuating said switching function.
6. The method of claim 5, wherein said steps are performed for
multiple dual function electronic logic gates in the logic
circuit.
7. The method of claim 6, wherein only a subset of available dual
function electronic logic gates are configured with said first
circuit function.
8. The method of claim 5, wherein said first selection voltage is
at least 2.times. said second selection voltage.
9. The method of claim 5, wherein said first selection voltage is
sufficiently high to cause hot electron injection onto the floating
gate of the dual function electronic logic gate.
10. The method of claim 5, wherein said input terminal is
electrically connected by an interconnect mask to only one of said
first selection voltage or second selection voltage.
Description
RELATED APPLICATIONS
[0001] The present application is a continuation of U.S. patent
application Ser. No. 13/233,767, filed Sep. 15, 2011, which claims
the benefit under 35 U.S.C. 119(e) of the priority date of
Provisional Application Ser. No. 61/383,128 filed Sep. 15, 2010.
Both of those applications are hereby incorporated by reference in
their entireties.
FIELD OF THE INVENTION
[0002] The present disclosure pertains to semiconductor logic
gates, particularly those which can be implemented using capacitive
coupling.
BACKGROUND
[0003] Reference is made to U.S. Pat. Nos. 7,782,668 and 7,787,295
and U.S. patent application Ser. Nos. 12/264,029, 12/264,060,
12/264,076, 12/271,647, 12,271,666 and 12/271,680 all of which are
hereby incorporated by reference.
[0004] The '668 patent discloses a new type of single-poly
non-volatile memory device structure that can be operated either as
an OTP (one time programmable) or as an MTP (multiple time
programmable) memory cell. The device is programmed using hot
electron injection. It also has a structure that is fully
compatible with advanced CMOS logic process, and would require, at
the worst case, very minimal additional steps to implement. Other
unique aspects of the device are described in the '668 patent as
well.
SUMMARY OF INVENTION
[0005] An object of the present invention is to extend the use of
capacitive coupling to specific types of logic devices and
circuits.
[0006] In accordance with this object a plurality of areal
capacitive coupling devices are coupled to process a set of data
inputs; each is preferably configured such that a floating gate
potential of such device can be altered in response to receiving an
input signal from the set of data inputs; the floating gate
potential can be adjusted to place the areal capacitive coupling
device into a first state or a second state through areal
capacitive coupling to a potential associated with a first active
region receiving the input signal; the areal capacitive coupling
devices as interconnected generate a first logic output which is a
first logical function associated with the set of data inputs.
[0007] Other objects of the invention include methods of operating
a dual function gate in which the device performs a different
circuit function depending on a level is of an input signal applied
to such logic gate;
[0008] Another object is to provide a logic gate with N inputs and
in which a selected set M of inputs (M<=N-2) can be considered
for purposes of determining a logical majority function.
[0009] A further object is to provide an electronic circuit in
which logic gates can also be imbued with a memory function to
allow for dual functionality.
DESCRIPTION OF THE DRAWINGS
[0010] FIG. 1 depicts a preferred embodiment of a circuit
implementing a 3-input majority function.
[0011] FIG. 2 depicts the Load Line characteristics of the 3-Input
Capacitive Coupling Device and Pull Down transistor shown in FIG.
1.
DETAILED DESCRIPTION
[0012] Applicant has discovered that the '668 gate/drain overlap
device using areal capacitive coupling (hereinafter referred to as
the "capacitive coupling device") can be used in non-memory
applications as well. As discussed herein, the device's unique
characteristics can be used to efficiently implement a number of
CMOS logic functions, including, preferably, one of the most device
consuming and yet useful--the Majority Function.
[0013] FIG. 1 below illustrates a preferred implementation of a
3-input majority function logic gate 100 implemented with three (3)
'668 capacitive coupling devices (shown at the top of the figure as
10A, 10B and 10C) along with standard CMOS transistors (including a
pair of inverters on the right --20A/20B, and a conventional N MOS
pulldown FET 30) at the bottom). It will be understood by those
skilled in the art that other combinations and connections of
devices could is be used to effectuate the same result of the
exemplary gate shown in FIG. 1, including of course for larger
numbers of inputs.
[0014] The output voltage characteristics, with the capacitive
coupling devices as load lines, of the above 3 input circuit is
illustrated in FIG. 2. As can be seen from the figure, if 2 or more
(a majority) of the inputs to devices 10A/10B/10C are conducting,
the intersecting point will yield an output voltage that is higher
than the VIH of the inverter circuit (20A/20B), and will allow the
output of the voltage after the two inverter stage to be high,
fulfilling a majority function.
[0015] Conversely, if only one or none of the inputs (not majority)
is conducting, the output voltage is below VIL, and will not be
able to trigger the inverter. This is how a 3-input majority
function is preferably implemented; namely with 3 capacitive
coupling devices, 1 pull-down transistor, and 2 pair of NMOS and
PMOS transistors for 2 inverter circuits. All of these devices are
conventional, and to ensure adequate margin of operation it is
preferable to perform simulations to select and match the size of
the various transistors. This can be accomplished using any number
of well-known design tools, and is commonly done in providing logic
cell libraries, so it is well within the skill of the ordinary
artisan without undue experimentation.
[0016] The transistor count saving, and the subsequent silicon area
saving, become geometrically larger when the number of inputs for
the majority function increases. For example, for a 5-input
majority function, only 5 capacitive coupling devices, 1 matched
pull-down transistor, and 2 pair of NMOS and PMOS transistors for
2-stage inverter circuit are required. In general, for any N input
majority function gate, the device count will be N capacitive
coupling devices and an additional set of 5 support
transistors.
[0017] One reason that using the capacitive coupling device
implementation of a logic gate is advantageous is that a
conventional N-channel floating gate device would not be able to
turn on if the drain coupling is not high enough to overcome the Vt
of the NMOS device. The present device has a high coupling ratio to
allow sufficient voltage coupled to the floating gate to turn on
the device in accordance with a target/nominal Vt implant process
used in the IC manufacturing flow.
[0018] Persons skilled in the art will appreciate from the present
teachings that the majority function can be implemented in an
alternative embodiment in which the invention is taken to an
extreme and 100% coupling is used, i.e., such as to effectuate a
form of NMOS gated diode (e.g., NMOS with gate connected to the
drain directly). The disadvantage of this approach is that it
removes one degree of process freedom, in that the only remaining
mechanism to control the switching/output of the device is through
adjusting the nominal Vt for the device, a tradeoff that may result
in compatability problems with the CMOS parameters of other devices
in the integrated circuit, as well as complicate the matching of
the logic circuit output to the pulldown FET characteristics.
[0019] A capacitive coupling device implementation with less than
100% coupling offers an advantage over a pure NMOS gated diode
implementation, since the output current of the capacitive coupling
device can be tailored specifically through the coupling
capacitance, without altering the baseline CMOS process parameters
(such as Vt) used by other logic circuits, and allowing the logic
function to be implemented optimally to other related circuit
elements, such as the pulldown FET. Thus the present invention
affords a more flexible technique to implement a logic function
since a nominal logic gate Vt and related process parameters can be
used as a driver to determine sizings of the gates/active regions,
and the extent of the coupling ratio (.A-inverted.) that should be
used for any particular circuit.
[0020] Other variants of the invention can include hardwired logic
(i.e., a PLD, programmable logic) and conventional CMOS logic
functions, albeit more efficient in device counts. By allowing
embedding of the device within a CMOS process, one can implement a
"hardwired" look-up table to implement some logic function, much
like an FPGA.
[0021] Another advantage of using the preferred embodiment of this
invention is that the situation where an input to the majority
function may no longer be valid can be addressed with the use of
capacitive coupled devices as described in '668. If an input is no
longer needed, the associated capacitive coupled device is can be
programmed to be off and be removed from being considered in the
output of the logic function. That is, any one or more of the logic
devices in the circuit can be configured effectively by a function
select signal. The function select signal can apply a potential to
the logic device so that it instead behaves as a quasi-memory
device. That is, the device behaves effectively like a memory gate,
not a logic gate, when the floating gate is raised to a
sufficiently high potential. This has the effect of turning the
device off (i.e., rendering it non-conductive) and thus selectively
enabling or disabling its participation in a circuit logic
function. In some embodiments the output or function can be
hardwired or burned in during manufacturing. This can be
accomplished by predetermined programming respective inputs to the
logic gates, to configure them into an erased or programmed state
as desired.
[0022] Other variations of circuits of the capacitive coupled dual
function devices can be employed of course, and the invention is
not limited in this respect. Many types of conventional circuits
are expected to benefit from devices which can adjust their
behavior dynamically in response to a function select signal.
[0023] Thus certain embodiments of the present invention can be
implemented so that a majority function circuit can be altered to
render a majority function for any subset of the inputs. For
example, even with maximum of 5 inputs, one can still program the
circuit to be a majority function of any of the 3 inputs. With a
set of 7 inputs one can consider the state of a selected subset of
5 inputs, and so on. Other variations will be apparent to those
skilled in the art.
[0024] This advantageous feature could potentially offer a
significant saving in the circuit design since costly revision of
the silicon design and its associated process cost can be
avoided.
[0025] While this preferred example illustrates a majority function
logic gate, those skilled in the art will appreciate from the
foregoing that this is just an example and that other complex CMOS
logic gates can be implemented using the capacitive coupling
devices as well. It is expected that the novel capacitive coupling
device can be utilized in a number of applications in a non-memory
is capacity as a substitute for a conventional FET.
* * * * *