U.S. patent application number 14/643224 was filed with the patent office on 2015-07-02 for stacked carbon-based fets.
The applicant listed for this patent is INTERNATIONAL BUSINESS MACHINES CORPORATION. Invention is credited to DECHAO GUO, Shu-Jen Han, Yu Lu, Keith Kwong Hon Wong.
Application Number | 20150187764 14/643224 |
Document ID | / |
Family ID | 51864187 |
Filed Date | 2015-07-02 |
United States Patent
Application |
20150187764 |
Kind Code |
A1 |
GUO; DECHAO ; et
al. |
July 2, 2015 |
STACKED CARBON-BASED FETS
Abstract
A stacked transistor device includes a lower transistor that has
a lower channel layer formed on a substrate and lower source and
drain regions formed directly over the lower channel layer. The
lower source and drain regions are in electrical contact with
respective conductive source and drain extensions formed in the
substrate. An upper transistor has upper source and drain regions
vertically aligned with the respective lower source and drain
regions. The upper source and drain regions are separated from the
respective lower source and drain regions by an insulator. The
upper transistor further includes an upper channel layer formed
over the upper source and drain regions.
Inventors: |
GUO; DECHAO; (Fishkill,
NY) ; Han; Shu-Jen; (Cortlandt Manor, NY) ;
Lu; Yu; (Hopewell Junction, NY) ; Wong; Keith Kwong
Hon; (New York, NY) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
Armonk |
NY |
US |
|
|
Family ID: |
51864187 |
Appl. No.: |
14/643224 |
Filed: |
March 10, 2015 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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|
13968101 |
Aug 15, 2013 |
8994080 |
|
|
14643224 |
|
|
|
|
13890849 |
May 9, 2013 |
8952431 |
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|
13968101 |
|
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Current U.S.
Class: |
257/401 |
Current CPC
Class: |
H01L 29/0847 20130101;
H01L 27/088 20130101; H01L 29/1054 20130101; H01L 29/7781 20130101;
H01L 29/1606 20130101; H01L 29/6656 20130101; H01L 29/78 20130101;
H01L 21/823412 20130101; H01L 27/092 20130101; H01L 21/8258
20130101; H01L 29/78645 20130101; H01L 29/66045 20130101; H01L
29/41725 20130101; H01L 29/78642 20130101; H01L 21/8256
20130101 |
International
Class: |
H01L 27/088 20060101
H01L027/088 |
Claims
1. A stacked transistor device, comprising: a lower transistor,
comprising a lower channel layer formed on a substrate and lower
source and drain regions formed directly over the lower channel
layer and in electrical contact with respective conductive source
and drain extensions formed in the substrate; and an upper
transistor, comprising upper source and drain regions vertically
aligned with the respective lower source and drain regions and
separated from said respective lower source and drain regions by an
insulator and further comprising an upper channel layer formed over
the upper source and drain regions.
2. The stacked transistor device of claim 1, wherein the upper and
lower channel layers are carbon-based.
3. The stacked transistor device of claim 1, wherein the upper
channel layer is carbon-based and the lower channel layer is
silicon based.
4. The stacked transistor device of claim 1, wherein the lower
transistor comprises a lower gate region and wherein the upper
transistor comprises an upper gate region
5. The stacked transistor device of claim 1, further comprising: a
lower gate dielectric layer formed on the lower channel layer; and
an upper gate dielectric layer formed over the upper source and
drain regions.
6. The stacked transistor device of claim 1, further comprising at
least one conductive metal contact that extends from above the
upper channel layer and contacts a source or drain extension.
7. The stacked transistor device of claim 6, wherein the at least
one conductive metal contact passes through an opening in the lower
channel layer.
8. The stacked transistor device of claim 6, wherein a conductive
metal surface contact is in contact with both source regions or
both drain regions to form a dual-transistor device.
9. The stacked transistor device of claim 8, wherein the conductive
metal surface contact connects to both drain regions to form an
inverter.
10. The stacked transistor device of claim 1, wherein at least one
conductive metal contact that passes through an opening in the
upper channel layer.
11. The stacked transistor device of claim 1, wherein at least one
conductive metal contact is formed contiguously and from a same
material as an upper source or drain region and passes through an
opening in a respective insulator to contact a respective lower
source or drain region.
12. The stacked transistor device of claim 1, wherein an upper
source region and an upper drain region are each formed entirely
from metal.
13. The stacked transistor device of claim 1, wherein an upper gate
region material has a different work function from a lower gate
region material, such that the gate regions will not interfere with
one another in operation.
Description
RELATED APPLICATION INFORMATION
[0001] This application is a Continuation application of co-pending
U.S. patent application Ser. No. 13/968,101, filed on Aug. 15,
2013, which in turn is a Continuation of co-pending application
Ser. No. 13/890,849 filed on May 9, 2013, both of which are
incorporated herein by reference in their entirety.
BACKGROUND
[0002] 1. Technical Field
[0003] The present invention relates to transistors and, more
particularly, to stacked carbon-based field effect transistors.
[0004] 2. Description of the Related Art
[0005] Carbon-based metal oxide semiconductor field effect
transistors (MOSFETs) do not need single-crystal substrates that
are common in conventional metal oxide semiconductor technologies.
This opens up the possibility of stacking multiple layers of such
devices, thereby increasing circuit density. However, simply
repeating layers of carbon transistor devices at advanced
technology nodes calls for very stringent overlay and device
matching. Interconnects between layers add significant delay and
greatly increase layout complexity.
SUMMARY
[0006] A stacked transistor device includes a lower transistor that
has a lower channel layer formed on a substrate and lower source
and drain regions formed directly over the lower channel layer. The
lower source and drain regions are in electrical contact with
respective conductive source and drain extensions formed in the
substrate. An upper transistor has upper source and drain regions
vertically aligned with the respective lower source and drain
regions. The upper source and drain regions are separated from the
respective lower source and drain regions by an insulator. The
upper transistor further includes an upper channel layer formed
over the upper source and drain regions.
[0007] These and other features and advantages will become apparent
from the following detailed description of illustrative embodiments
thereof, which is to be read in connection with the accompanying
drawings.
BRIEF DESCRIPTION OF DRAWINGS
[0008] The disclosure will provide details in the following
description of preferred embodiments with reference to the
following figures wherein:
[0009] FIG. 1 is a cross-sectional view of a step in the formation
of a stacked gate transistor in accordance with the present
principles;
[0010] FIG. 2 is a cross-sectional view of a step in the formation
of a stacked gate transistor in accordance with the present
principles;
[0011] FIG. 3 is a cross-sectional view of a step in the formation
of a stacked gate transistor in accordance with the present
principles;
[0012] FIG. 4 is a cross-sectional view of a step in the formation
of a stacked gate transistor in accordance with the present
principles;
[0013] FIG. 5 is a cross-sectional view of a step in the formation
of a stacked gate transistor in accordance with the present
principles;
[0014] FIG. 6 is a cross-sectional view of a step in the formation
of a stacked gate transistor in accordance with the present
principles;
[0015] FIG. 7 is a cross-sectional view of a step in the formation
of a stacked gate transistor in accordance with the present
principles;
[0016] FIG. 8 is a cross-sectional view of a step in the formation
of a stacked gate transistor in accordance with the present
principles;
[0017] FIG. 9 is a cross-sectional view of a step in the formation
of a stacked gate transistor in accordance with the present
principles;
[0018] FIG. 10 is a cross-sectional view of a step in the formation
of a stacked gate transistor in accordance with the present
principles;
[0019] FIG. 11 is a cross-sectional view of a step in the formation
of a stacked gate transistor in accordance with the present
principles;
[0020] FIG. 12 is a cross-sectional view of a step in the formation
of a stacked gate transistor in accordance with the present
principles;
[0021] FIG. 13 is a cross-sectional view of a step in the formation
of a stacked gate transistor in accordance with the present
principles;
[0022] FIG. 14 is a cross-sectional view of a step in the formation
of a stacked gate transistor in accordance with the present
principles;
[0023] FIG. 15 is a cross-sectional view of a step in the formation
of a stacked gate transistor in accordance with the present
principles; and
[0024] FIG. 16 is a block/flow diagram of a method for forming a
stacked gate transistor in accordance with the present
principles.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
[0025] The present principles provide self-aligned, stacked
carbon-based metal oxide semiconductor field effect transistors
(MOSFETs). According to the present principles, a carbon-based
MOSFET can be stacked on another carbon-based FET or a conventional
FET and may have opposite polarity. So, for example, a p-type FET
may be stacked on an n-type FET and the reverse is also true. This
structure lends itself well to several circuit elements, such as
inverters, NAND gates, XOR gates, multiplexers, memory cells,
etc.
[0026] It is to be understood that the present invention will be
described in terms of a given illustrative architecture having a
wafer; however, other architectures, structures, substrate
materials and process features and steps may be varied within the
scope of the present invention.
[0027] It will also be understood that when an element such as a
layer, region or substrate is referred to as being "on" or "over"
another element, it can be directly on the other element or
intervening elements may also be present. In contrast, when an
element is referred to as being "directly on" or "directly over"
another element, there are no intervening elements present. It will
also be understood that when an element is referred to as being
"connected" or "coupled" to another element, it can be directly
connected or coupled to the other element or intervening elements
may be present. In contrast, when an element is referred to as
being "directly connected" or "directly coupled" to another
element, there are no intervening elements present.
[0028] A design for an integrated circuit chip may be created in a
graphical computer programming language, and stored in a computer
storage medium (such as a disk, tape, physical hard drive, or
virtual hard drive such as in a storage access network). If the
designer does not fabricate chips or the photolithographic masks
used to fabricate chips, the designer may transmit the resulting
design by physical means (e.g., by providing a copy of the storage
medium storing the design) or electronically (e.g., through the
Internet) to such entities, directly or indirectly. The stored
design is then converted into the appropriate format (e.g., GDSII)
for the fabrication of photolithographic masks, which typically
include multiple copies of the chip design in question that are to
be formed on a wafer. The photolithographic masks are utilized to
define areas of the wafer (and/or the layers thereon) to be etched
or otherwise processed.
[0029] Methods as described herein may be used in the fabrication
of integrated circuit chips. The resulting integrated circuit chips
can be distributed by the fabricator in raw wafer form (that is, as
a single wafer that has multiple unpackaged chips), as a bare die,
or in a packaged form. In the latter case the chip is mounted in a
single chip package (such as a plastic carrier, with leads that are
affixed to a motherboard or other higher level carrier) or in a
multichip package (such as a ceramic carrier that has either or
both surface interconnections or buried interconnections). In any
case the chip is then integrated with other chips, discrete circuit
elements, and/or other signal processing devices as part of either
(a) an intermediate product, such as a motherboard, or (b) an end
product. The end product can be any product that includes
integrated circuit chips, ranging from toys and other low-end
applications to advanced computer products having a display, a
keyboard or other input device, and a central processor.
[0030] Reference in the specification to "one embodiment" or "an
embodiment" of the present principles, as well as other variations
thereof, means that a particular feature, structure,
characteristic, and so forth described in connection with the
embodiment is included in at least one embodiment of the present
principles. Thus, the appearances of the phrase "in one embodiment"
or "in an embodiment", as well any other variations, appearing in
various places throughout the specification are not necessarily all
referring to the same embodiment.
[0031] It is to be appreciated that the use of any of the following
"/", "and/or", and "at least one of", for example, in the cases of
"A/B", "A and/or B" and "at least one of A and B", is intended to
encompass the selection of the first listed option (A) only, or the
selection of the second listed option (B) only, or the selection of
both options (A and B). As a further example, in the cases of "A,
B, and/or C" and "at least one of A, B, and C", such phrasing is
intended to encompass the selection of the first listed option (A)
only, or the selection of the second listed option (B) only, or the
selection of the third listed option (C) only, or the selection of
the first and the second listed options (A and B) only, or the
selection of the first and third listed options (A and C) only, or
the selection of the second and third listed options (B and C)
only, or the selection of all three options (A and B and C). This
may be extended, as readily apparent by one of ordinary skill in
this and related arts, for as many items listed.
[0032] Referring now to the drawings in which like numerals
represent the same or similar elements and initially to FIG. 1, a
step in forming stacked carbon-based FETs is shown. A substrate 102
is formed from any appropriate material. For example, the substrate
102 may be formed from a dielectric such as silicon dioxide.
Source/drain extensions 104 are formed in the substrate 102. The
source/drain extensions 104 do not represent the functional
source/drain regions themselves, but are instead conductive
elements that will provide electrical communication with the
source/drain regions. As such, the source/drain regions may be
formed from any suitable material including, e.g., a conductor
metal such as tungsten or a conductive composite. A carbon-based
channel layer 106 is formed over the surface of substrate 102, with
a gate dielectric layer 108 above the carbon layer 106. The carbon
layer 106 may be formed from any suitable carbon-based channel
material including, e.g., carbon nanotubes and graphene. The gate
dielectric layer 108 may be formed from any appropriate dielectric
material including, e.g., a high-k dielectric such as hafnium
silicate, hafnium dioxide, zirconium silicate, and zirconium
dioxide.
[0033] A layer of gate material 110 is formed on the dielectric
layer 108. The gate material 110 may be, for example, a metal, such
as tantalum, tantalum nitride, or niobium, or may be a non-metallic
gate material such as polysilicon. A capping dielectric layer 112
is formed on the gate material layer 110. The capping dielectric
layer 112 may be formed from any appropriate dielectric including,
e.g., silicon dioxide. A top layer 114 is formed over the capping
dielectric layer 112 and may be formed from, e.g., amorphous
silicon.
[0034] Referring now to FIG. 2, a step in forming stacked
carbon-based FETs is shown. An anisotropic etch is performed on the
gate material layer 110, the capping dielectric layer 112, and the
top layer 114 to form a gate stack made up of a gate 202, a
dielectric cap 204, and a top 206 of, e.g., amorphous silicon. It
is contemplated that those having ordinary skill in the art will be
able to select an appropriate etch that stops on the gate
dielectric layer 108. In one embodiment, a reverse ion etch (RIE)
process is used to form the gate stack.
[0035] Referring now to FIG. 3, a step in forming stacked
carbon-based FETs is shown. A hardmask layer 302 is deposited
around the gate stack. The hardmask layer 302 may be any
appropriate hardmask material including, e.g., silicon nitride, and
may be deposited by any appropriate process including, e.g.,
chemical vapor deposition (CVD), atomic layer deposition (ALD),
physical vapor deposition (PVD), etc. After deposition, the nitride
layer is planarized to the level of the top layer 206 using, e.g.,
chemical mechanical planarization (CMP). It should be understood
that those having ordinary skill in the art will be able to select
a planarizing slurry appropriate to the materials being used.
[0036] Referring now to FIG. 4, a step in forming stacked
carbon-based FETs is shown. The hardmask layer 302 is patterned and
etched using, e.g., an anisotropic etch such as RIE to expose
source and drain regions 404 on either side of the gate stack,
leaving a remaining portion of hardmask 402.
[0037] Referring now to FIG. 5, a step in forming stacked
carbon-based FETs is shown. A sidewall spacer 502 is formed along
the gate stack and the remaining hardmask 402. The gate dielectric
layer 108 is etched in the source and drain regions 404, leaving a
gate dielectric 504 as part of the gate stack.
[0038] Referring now to FIG. 6, a step in forming stacked
carbon-based FETs is shown. Source and drain material 602 is
deposited in source and drain regions 404 and may include, e.g., an
appropriate metal or conductive composite such as palladium. The
source and drain regions may be deposited using, e.g., a PVD
process followed by a wet etch to clean the sidewalls 502. An
insulator 604 is then formed over the source/drain material 602 by
any appropriate process. An exemplary material for insulator 604
is, e.g., silicon dioxide. The insulator 604 is then planarized
using, e.g., a CMP that stops on the remaining hardmask 402.
[0039] Referring now to FIG. 7, a step in forming stacked
carbon-based FETs is shown. The insulator 604 is recessed above
source/drain regions 602 using any appropriate etching process such
as, e.g., a wet etch. The recesses are filled in with the same
material as the top layer 206, forming top layer 702, and may
include, e.g., amorphous silicon. The top layer 702 may be formed
by CVD, ALD, PVD, or any other appropriate form of deposition and
may then be planarized to the level of the original top layer 206
using, e.g., a CMP, that stops on the remaining hardmask 402.
[0040] Referring now to FIG. 8, a step in forming stacked
carbon-based FETs is shown. The top layers 206 and 702 are etched
using, e.g., a timed RIE process. The etch is timed such that the
top layer 206 over the gate stack is removed entirely, leaving a
remaining top layer 802 over source and drain regions 602. The etch
of top layer 206 exposes capping dielectric layer 204.
[0041] Referring now to FIG. 9, a step in forming stacked
carbon-based FETs is shown. The capping dielectric layer 204 is
removed using, e.g., a wet etch such as by diluted hydrofluoric
acid. The removal of the dielectric cap 204 exposes the gate metal
202. The gate metal 202 will be referred to henceforth as lower
gate 202 to distinguish it from the top gate to be formed.
[0042] Referring now to FIG. 10, a step in forming stacked
carbon-based FETs is shown. A top gate metal 1002 is formed by
depositing a gate material using any appropriate deposition process
including, e.g., CVD, ALD, and PVD. The surface is machined down to
at least the level of the remaining top layer 802 using, e.g., CMP.
It is worth noting that no barrier is needed between the top gate
metal 1002 and the lower gate metal 202. The materials of the two
gates may be fabricated such that they have different work
functions and will not interfere with one another in operation.
[0043] Referring now to FIG. 11, a step in forming stacked
carbon-based FETs is shown. The remaining top layer 802 is etched
further to produce recessed top layer 1104. The recessed top layer
1104 may be etched using, e.g., an appropriate wet etch. A top gate
dielectric 1102 is deposited using, e.g., CVD, ALD, or PVD. The top
gate dielectric 1102 may be formed from, e.g., a high-k dielectric
such as hafnium silicate, hafnium dioxide, zirconium silicate, or
zirconium dioxide.
[0044] Referring now to FIG. 12, a step in forming stacked
carbon-based FETs is shown. The top gate dielectric 1102 is
lithographically trimmed using, e.g., a resist 1204. The resist
1204 is patterned on top of the dielectric material 1102, and the
dielectric material 1102 not covered by the resist 1204 is removed.
Access to the top and bottom drain regions 1204 is provided by
etching through the resist 1204, the top gate dielectric 1102, the
remaining top layer 802, and the insulator 604.
[0045] Referring now to FIG. 13, a step in forming stacked
carbon-based FETs is shown. The resist 1204 is stripped and a top
carbon layer 1302 is placed on the top gate dielectric 1102. The
top carbon layer 1302 may be formed from any suitable carbon-based
channel material including, e.g., carbon nanotubes and graphene,
and is patterned to fit an active area. A hardmask layer 1304 is
formed over the top carbon layer 1302 by any appropriate deposition
process including, e.g., CVD, ALD, or PVD. The hardmask layer 1304
may be formed from, e.g., an oxide such as silicon dioxide.
[0046] Referring now to FIG. 14, a step in forming stacked
carbon-based FETs is shown. Bottom source and drain access holes
1402 are lithographically formed to provide access to source and
drain extensions 104. A top source access hole 1404 is
lithographically formed to provide access to the as yet unformed
top source region and a top drain access hole is lithographically
formed to provide access to the as yet unformed top drain region.
In this particular embodiment, a drain access hole 1406 contacts
both the upper and lower drain regions 604 and 602, essentially
joining the two. As will be discussed below, this structure forms
an inverter--different applications may connect different
terminals.
[0047] Referring now to FIG. 15, a step in forming stacked
carbon-based FETs is shown. The remaining top layer 802 of, e.g.,
amorphous silicon is removed using an appropriate wet etch such as
ammonium hydroxide. The access holes 1402, 1404, and 1406 are
filled with an appropriate contact metal such as, e.g., palladium.
The contact metal is deposited using any appropriate deposition
process such as, e.g., CVD or ALD and patterned to form bottom
source contact 1502, top source contact 1504, top drain contact
1506, and bottom drain contact 1508. Electrical access to the gates
202/1002 is provided, but not shown in these figures as it is out
of the plane of the drawing in this embodiment.
[0048] Embodiments of the present principles may be used to form a
variety of different devices. For example, if the drains are
shorted together as shown above, the lower source contact 1502 is
connected to ground, and the upper source contact 1504 is connected
to a supply voltage, an inverter is formed with the gates 202/1002
as input and the contact 1506 as output. Further electronic
components may be formed, including for example a two-input NAND
gate, a 2-1 multiplexer, and a 2-1 XOR gate, by connecting multiple
such devices.
[0049] Referring now to FIG. 16, a process for forming stacked
carbon-based FETs is shown. Block 1602 forms lower channel material
106 and source/drain extensions 104 on a substrate 102. As noted
above, the lower channel material 106 is a carbon-based channel
material that may include, for example, carbon nanotubes or
graphene. The use of carbon-based channel material allows the
creation of FET devices that are not formed from a single,
monolithic crystal, such that devices may be stacked. The
source/drain extensions 104 may be formed from any suitable
material including, e.g., a conductor metal such as tungsten or a
conductive composite.
[0050] Block 1604 forms the lower gate dielectric 504 and the lower
gate 202. Source/drain regions 404 are etched out and lower
source/drain material 602 is deposited in block 1606. Block 1607
forms an insulating barrier 604 above the source/drain material
602. This insulator 604 forms a barrier between the bottom of the
source/drain region 404 and the top of the source/drain region 404,
allowing for separate devices to be formed.
[0051] Block 1608 forms upper gate metal 1002 and upper gate
dielectric 1102. Block 1610 forms an upper channel material 1302
over the upper gate dielectric 1102. As noted above, the upper
channel material may be a carbon-based channel material such as
carbon nanotubes or graphene. Block 1612 forms electrical access
1502/1508 to the source/drain extensions 104. Block 1614,
meanwhile, forms the upper source and drain regions and provides
electrical access 1504 and 1506 to them.
[0052] It should be recognized that the present principles may be
adapted to an alternative embodiment that forms a carbon-based FET
on top of a conventional, semiconductor channel MOSFET. Such
structures may be used to form additional circuits such as NAND and
XOR gates, static random access memory (SRAM) cells, and
multiplexers. In such an embodiment, the bottom channel layer 106
may be formed from a semiconductor instead of a carbon material.
The source/drain extensions 104 may then be formed from a heavily
doped region of semiconductor.
[0053] Having described preferred embodiments of stacked
carbon-based FETs and methods for making the same (which are
intended to be illustrative and not limiting), it is noted that
modifications and variations can be made by persons skilled in the
art in light of the above teachings. It is therefore to be
understood that changes may be made in the particular embodiments
disclosed which are within the scope of the invention as outlined
by the appended claims. Having thus described aspects of the
invention, with the details and particularity required by the
patent laws, what is claimed and desired protected by Letters
Patent is set forth in the appended claims.
* * * * *