U.S. patent application number 14/658783 was filed with the patent office on 2015-07-02 for ballast resistor for super-high-voltage devices.
The applicant listed for this patent is Marvell World Trade LTD.. Invention is credited to Siew Yong Chui, Ravishanker Krishnamoorthy, Sehat Sutardja.
Application Number | 20150187754 14/658783 |
Document ID | / |
Family ID | 47361049 |
Filed Date | 2015-07-02 |
United States Patent
Application |
20150187754 |
Kind Code |
A1 |
Sutardja; Sehat ; et
al. |
July 2, 2015 |
BALLAST RESISTOR FOR SUPER-HIGH-VOLTAGE DEVICES
Abstract
An integrated circuit including a well region, a plurality of
semiconductor regions implanted in the well region, and a plurality
of polysilicon regions arranged on each of the plurality of
semiconductor regions. The well region has a first doping level.
Each of the plurality of semiconductor regions has a second doping
level. The second doping level is greater than the first doping
level. The polysilicon regions are respectively connected directly
to the plurality of semiconductor regions.
Inventors: |
Sutardja; Sehat; (Los Altos
Hills, CA) ; Krishnamoorthy; Ravishanker; (Singapore,
SG) ; Chui; Siew Yong; (Singapore, SG) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Marvell World Trade LTD. |
St. Michael |
|
BB |
|
|
Family ID: |
47361049 |
Appl. No.: |
14/658783 |
Filed: |
March 16, 2015 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
13467666 |
May 9, 2012 |
8981484 |
|
|
14658783 |
|
|
|
|
61501507 |
Jun 27, 2011 |
|
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Current U.S.
Class: |
257/360 |
Current CPC
Class: |
H01L 2924/0002 20130101;
H01L 29/0847 20130101; H01L 29/7835 20130101; H01L 2924/0002
20130101; H01L 27/0266 20130101; H01L 27/0288 20130101; H01L
29/0878 20130101; H01L 29/66659 20130101; H01L 29/66681 20130101;
H01L 29/7817 20130101; H01L 2924/00 20130101 |
International
Class: |
H01L 27/02 20060101
H01L027/02 |
Claims
1. An integrated circuit, comprising: a well region having a first
doping level; a plurality of semiconductor regions implanted in the
well region, wherein each of the plurality of semiconductor regions
has a second doping level, and wherein the second doping level is
greater than the first doping level; and a plurality of polysilicon
regions arranged on each of the plurality of semiconductor regions,
wherein the polysilicon regions are respectively connected directly
to the plurality of semiconductor regions.
2. The integrated circuit of claim 1, wherein the plurality of
semiconductor regions forms a drain of a metal-oxide semiconductor
field-effect transistor (MOSFET).
3. The integrated circuit of claim 2, wherein the MOSFET has a
higher voltage rating and size than a signal MOSFET.
4. The integrated circuit of claim 1, wherein the plurality of
polysilicon regions have a resistance of at least one Ohm.
5. The integrated circuit of claim 1, wherein arranging the
plurality of polysilicon regions on each of the plurality of
semiconductor regions degenerates conductivity and increases
resistivity of the plurality of semiconductor regions.
6. The integrated circuit of claim 1, wherein: the well region and
the plurality of semiconductor regions have a first type of doping,
the well region is arranged on a substrate having a second type of
doping, and the second type of doping is opposite to the first type
of doping.
7. The integrated circuit of claim 1, wherein: the plurality of
semiconductor regions is arranged along an axis, each of the
plurality of polysilicon regions has a length and a width, the
length is greater than the width, and the length extends along the
axis.
8. The integrated circuit of claim 1, wherein: the plurality of
semiconductor regions is arranged along an axis, each of the
plurality of polysilicon regions has a length and a width, the
width is greater than the length, and the width is perpendicular to
the axis.
9. An integrated circuit, comprising: a well region having a first
type of doping and a first doping level, wherein the well region is
arranged on a substrate having a second type of doping, and wherein
the second type of doping is opposite to the first type of doping;
a plurality of semiconductor regions implanted in the well region,
wherein each of the plurality of semiconductor regions has the
first type of doping and a second doping level, and wherein the
second doping level is greater than the first doping level; and a
plurality of polysilicon regions arranged on each of the plurality
of semiconductor regions, wherein the polysilicon regions are
respectively connected directly to the plurality of semiconductor
regions.
10. The integrated circuit of claim 9, wherein: the plurality of
semiconductor regions forms a drain of a metal-oxide semiconductor
field-effect transistor (MOSFET), and the MOSFET has a higher
voltage rating and size than a signal MOSFET.
11. The integrated circuit of claim 9, wherein the plurality of
polysilicon regions have a resistance of at least one Ohm.
12. The integrated circuit of claim 9, wherein arranging the
plurality of polysilicon regions on each of the plurality of
semiconductor regions degenerates conductivity and increases
resistivity of the plurality of semiconductor regions.
13. The integrated circuit of claim 9, wherein: the plurality of
semiconductor regions is arranged along an axis, each of the
plurality of polysilicon regions has a length and a width, the
length is greater than the width, and the length extends along the
axis.
14. The integrated circuit of claim 9, wherein: the plurality of
semiconductor regions is arranged along an axis, each of the
plurality of polysilicon regions has a length and a width, the
width is greater than the length, and the width is perpendicular to
the axis.
15. A metal-oxide semiconductor field-effect transistor integrated
circuit comprising: a plurality of drain regions, wherein the
plurality of drain regions includes a plurality of semiconductor
regions having a first doping level, wherein the plurality of
semiconductor regions is implanted in a well region having a second
doping level, and wherein the first doping level is greater than
the second doping level; and a plurality of resistors respectively
connected to the plurality of drain regions, wherein the plurality
of resistors includes a plurality of polysilicon regions
respectively arranged on each of the plurality of semiconductor
regions, wherein the plurality of polysilicon regions are
respectively connected directly to the plurality of semiconductor
regions.
16. The metal-oxide semiconductor field-effect transistor
integrated circuit of claim 15, further comprising: the well
region, wherein the plurality of semiconductor regions and the well
region have a first type of doping, wherein the well region is
arranged on a substrate having a second type of doping, and wherein
the second type of doping is opposite to the first type of
doping.
17. The metal-oxide semiconductor field-effect transistor
integrated circuit of claim 15, wherein: the plurality of
semiconductor regions is arranged along an axis, each of the
plurality of polysilicon regions has a length and a width, the
length is greater than the width, and the length extends along the
axis.
18. The metal-oxide semiconductor field-effect transistor
integrated circuit of claim 15, wherein: the plurality of
semiconductor regions is arranged along an axis, each of the
plurality of polysilicon regions has a length and a width, the
width is greater than the length, and the width is perpendicular to
the axis.
19. The integrated circuit of claim 15, wherein the plurality of
polysilicon regions have a resistance of at least one Ohm.
20. The integrated circuit of claim 15, wherein arranging the
plurality of polysilicon regions on each of the plurality of
semiconductor regions degenerates conductivity and increases
resistivity of the plurality of semiconductor regions.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is a continuation of U.S. patent
application Ser. No. 13/467,666 (now U.S. Pat. No. 8,981,484),
filed May 9, 2012, which claims the benefit of U.S. Provisional
Application No. 61/501,507, filed on Jun. 27, 2011. The entire
disclosures of the applications referenced above are incorporated
herein by reference.
FIELD
[0002] The present disclosure relates generally to integrated
circuits and more particularly to a method for realizing a resistor
at a drain of a super-high-voltage (SHV) metal-oxide semiconductor
field-effect transistors (MOSFETs) to protect from electrostatic
discharge (ESD).
BACKGROUND
[0003] The background description provided herein is for the
purpose of generally presenting the context of the disclosure. Work
of the presently named inventors, to the extent the work is
described in this background section, as well as aspects of the
description that may not otherwise qualify as prior art at the time
of filing, are neither expressly nor impliedly admitted as prior
art against the present disclosure.
[0004] Devices such as metal-oxide semiconductor field-effect
transistors (MOSFETs) can be damaged due to electrostatic discharge
(ESD). To protect MOSFETs in an integrated circuit (IC) from ESD,
additional circuitry may be used externally or internally to the
IC.
[0005] A super-high-voltage (SHV) MOSFET occupies a much larger die
area in an IC than low-power MOSFETs. Accordingly, adding circuitry
in the IC to protect the SHV MOSFET from ESD consumes additional
die area in the IC, which is undesirable. The SHV MOSFETs therefore
need to be self-protecting. That is, the SHV MOSFET in the IC needs
to protect itself from ESD without the additional ESD protecting
circuitry in the IC.
SUMMARY
[0006] An integrated circuit (IC) including a well region of the IC
having a first doping level and a plurality of semiconductor
regions implanted in the well region. Each of the plurality of
semiconductor regions has a second doping level. The second doping
level is greater than the first doping level. A plurality of
polysilicon regions are arranged on the plurality of semiconductor
regions. The polysilicon regions are respectively connected to the
semiconductor regions. The plurality of semiconductor regions is a
drain of a metal-oxide semiconductor field-effect transistor
(MOSFET).
[0007] In other features, the well region and the plurality of
semiconductor regions have a first type of doping, where the well
region is arranged on a substrate having a second type of doping,
and where the second type of doping is opposite to the first type
of doping.
[0008] In other features, the plurality of semiconductor regions is
arranged along an axis, each of the plurality of polysilicon
regions has a length and a width, the length is greater than the
width, and the length extends along the axis.
[0009] In other features, the plurality of semiconductor regions is
arranged along an axis, each of the plurality of polysilicon
regions has a length and a width, the width is greater than the
length, and the width is perpendicular to the axis.
[0010] In other features, the plurality of polysilicon regions have
a resistance of at least one Ohm.
[0011] In other features, the plurality of polysilicon regions
protect the MOSFET from electrostatic discharge.
[0012] In still other features, an integrated circuit (IC) includes
a well region of the IC having a first type of doping and a first
doping level, where the well region is arranged on a substrate
having a second type of doping, and where the second type of doping
is opposite to the first type of doping. A plurality of
semiconductor regions is implanted in the well region, where each
of the plurality of semiconductor regions has the first type of
doping and a second doping level, and where the second doping level
is greater than the first doping level. A plurality of polysilicon
regions is respectively connected to the plurality of semiconductor
regions. The plurality of semiconductor regions is a drain of a
metal-oxide semiconductor field-effect transistor (MOSFET).
[0013] In other features, the plurality of semiconductor regions is
arranged along an axis, each of the plurality of polysilicon
regions has a length and a width, the length is greater than the
width, and the length extends along the axis.
[0014] In other features, the plurality of semiconductor regions is
arranged along an axis, each of the plurality of polysilicon
regions has a length and a width, the width is greater than the
length, and the width is perpendicular to the axis.
[0015] In other features, the plurality of polysilicon regions have
a resistance of at least one Ohm.
[0016] In other features, the plurality of polysilicon regions
protect the MOSFET from electrostatic discharge.
[0017] In still other features, a metal-oxide semiconductor
field-effect transistor (MOSFET) integrated circuit (IC) includes a
plurality of drain regions of the MOSFET IC, where the plurality of
drain regions includes a plurality of semiconductor regions having
a first doping level, where the plurality of semiconductor regions
is implanted in a well region having a second doping level, and
where the first doping level is greater than the second doping
level. A plurality of resistors is respectively connected to the
plurality of drain regions, where the plurality of resistors
includes a plurality of polysilicon regions respectively arranged
on the plurality of semiconductor regions in the MOSFET IC.
[0018] In other features, the MOSFET IC further includes the well
region, where the plurality of semiconductor regions and the well
region have a first type of doping, where the well region is
arranged on a substrate having a second type of doping, and where
the second type of doping is opposite to the first type of
doping.
[0019] In other features, the plurality of semiconductor regions is
arranged along an axis, each of the plurality of polysilicon
regions has a length and a width, the length is greater than the
width, and the length extends along the axis.
[0020] In other features, the plurality of semiconductor regions is
arranged along an axis, each of the plurality of polysilicon
regions has a length and a width, the width is greater than the
length, and the width is perpendicular to the axis.
[0021] In other features, the plurality of resistors have a
resistance of at least one Ohm.
[0022] In other features, the plurality of resistors protect the
MOSFET IC from electrostatic discharge.
[0023] In still other features, a method includes implanting a
plurality of semiconductor regions having a first doping level in a
well region of an integrated circuit, where the well regions has a
second doping level, and where the first doping level is greater
than the second doping level. The method further includes arranging
a plurality of polysilicon regions on the plurality of
semiconductor regions in the integrated circuit and connecting the
plurality of polysilicon regions respectively to the plurality of
semiconductor regions.
[0024] In other features, each of the plurality of polysilicon
regions has a length and a width, and where the length is greater
than the width. The method further includes arranging the plurality
of semiconductor regions along an axis and arranging lengths of the
plurality of polysilicon regions parallel to the axis.
[0025] In other features, each of the plurality of polysilicon
regions has a length and a width, and where the width is greater
than the length. The method further includes arranging the
plurality of semiconductor regions along an axis and arranging
widths of the plurality of polysilicon regions perpendicular to the
axis.
[0026] Further areas of applicability of the present disclosure
will become apparent from the detailed description, the claims and
the drawings. The detailed description and specific examples are
intended for purposes of illustration only and are not intended to
limit the scope of the disclosure.
BRIEF DESCRIPTION OF DRAWINGS
[0027] The present disclosure will become more fully understood
from the detailed description and the accompanying drawings,
wherein:
[0028] FIG. 1 is a schematic of super-high-voltage (SHV)
metal-oxide semiconductor field-effect transistors (MOSFETs) with
ballast resistors;
[0029] FIG. 2 is a cross-section of layout of a drain region of a
SHV MOSFET without ballast resistors;
[0030] FIG. 3A is a cross-section of a layout of a drain region of
a SHV MOSFET with polysilicon arranged in the drain region
according to a first arrangement to provide ballast resistors;
[0031] FIG. 3B depicts details of a plurality of polysilicon
regions arranged in the drain region according to the first
arrangement;
[0032] FIG. 3C is a cross-section of a layout of a drain region of
a SHV MOSFET with polysilicon arranged in the drain region
according to a second arrangement to provide ballast resistors;
and
[0033] FIG. 3D depicts details of a plurality of polysilicon
regions arranged in the drain region according to the second
arrangement.
DESCRIPTION
[0034] Self-protection of super-high-voltage (SHV) metal-oxide
semiconductor field-effect transistors (MOSFETs) from electrostatic
discharge (ESD) can be problematic. For example, since the size of
a SHV MOSFET is large relative to a low-power MOSFET, the structure
of the SHV MOSFET may not be uniform due to process variations.
Consequently, different portions of the SHV MOSFET may breakdown at
different ESD voltages. A portion having the lowest breakdown
voltage turns on as soon as the ESD voltage reaches the lowest
breakdown voltage, carries all the current, and burns, which
renders the SHV MOSFET useless. The variation or spread in the
breakdown voltages among different portions of the SHV MOSFET can
be proportional to the size of the SHV MOSFET.
[0035] Referring now to FIG. 1, a SHV MOSFET 100 includes a
plurality of constituent MOSFETs M1, M2, . . . , and Mn connected
in parallel, where n is an integer greater than 1. To account for
the spread in the breakdown voltages and evenly distribute energy
from ESD across the SHV MOSFET 100, a plurality of ballast
resistors (R.sub.ballast) is added to the SHV MOSFET 100 as shown.
Specifically, a ballast resistor R.sub.ballast is added between a
drain pin (or a drain terminal) of the SHV MOSFET 100 and a drain
of each of the constituent MOSFETs M1, M2, . . . , and Mn.
[0036] The ballast resistors prevent the MOSFET with the lowest
breakdown voltage from turning on as follows. Suppose, for example
only, that the average breakdown voltage of the SHV MOSFET 100 is
600V. A 1% variation can result in a difference of up to 6V from
600V. Accordingly, the MOSFET M1 may breakdown at 602V; the MOSFET
M2 may break down at 600V, . . . , and the MOSFET Mn may breakdown
at 606V. When an ESD event occurs, the ESD voltage at the drain pin
of the SHV MOSFET 100 increases from OV.
[0037] As the ESD voltage at the drain pin of the SHV MOSFET 100
approaches 600V, at 599V for example, none of the MOSFETs M1, M2, .
. . , and Mn turns on. However, leakage currents are flowing
through the MOSFETs M1, M2, . . . , and Mn. These leakage currents
generate voltage drops across the ballast resistors connected to
the drains of the MOSFETs M1, M2, . . . , and Mn. A leakage current
through a MOSFET, and consequently a voltage drop across the
ballast resistor connected to the drain of the MOSFET, increases as
the voltage at the drain pin of the SHV MOSFET 100 approaches the
breakdown voltage of the MOSFET.
[0038] For example, when the voltage at the drain pin of the SHV
MOSFET 100 approaches 599V, which is close to the breakdown voltage
of the MOSFET M2 (600V), a higher leakage current flowing through
the MOSFET M2 generates a voltage drop across the ballast resistor
connected to the drain of the MOSFET M2. The voltage drop may
increase the voltage at the drain pin of the SHV MOSFET 100 to
602V.
[0039] When the voltage at the drain pin of the SHV MOSFET 100
nears 602V, which is close to the breakdown voltage of the MOSFET
M1 (602V), a higher leakage current flows through the MOSFET M1.
Since the MOSFET M1 begins conducting a higher leakage current, the
MOSFET M1 provides an additional path for the current to flow
should the MOSFET M2 turn on. In other words, the MOSFET M1 diverts
(i.e., provides a path for) some of the current flowing through the
MOSFET M2 as the MOSFET M2 nears turn-on due to the increased
voltage at the drain pin of the SHV MOSFET 100. Effectively, this
prevents (or delays) the MOSFET M2 from turning on although the
voltage at the drain pin of the SHV MOSFET 100 exceeds the
breakdown voltage of the MOSFET M2 (600V).
[0040] The leakage current flowing through the ballast resistor
connected to the drain of the MOSFET M1 generates a voltage drop
across the ballast resistor connected to the drain of the MOSFET
M1. The voltage drop may increase the voltage at the drain pin of
the SHV MOSFET 100 to more than 602V, which causes a higher leakage
current to flow through another one of the MOSFETs, and which
diverts some of the current from flowing through the MOSFETs M1 and
M2. This prevents (or delays) the MOSFET M1 from turning on
although the voltage at the drain pin of the SHV MOSFET 100 exceeds
the breakdown voltage of the MOSFET M1 (602V). At this point, the
MOSFET M2 may be close to being turned on.
[0041] This process continues until the voltage at the drain pin of
the SHV MOSFET 100 increases to nearly 606V, and a higher leakage
current flows through the MOSFET Mn, which diverts some of the
current from flowing through the MOSFETs M1, M2, etc. At this
point, the MOSFET M2 may be very close to being turned on, the
MOSFET M1 may be close to being turned on, and so on.
[0042] Effectively, the turn-on times of the MOSFETs M1, M2, . . .
, and Mn are synchronized due to the voltage drops across the
ballast resistors connected to the drains of the MOSFETs M1, M2, .
. . , and Mn. Accordingly, when the voltage at the drain pin of the
SHV MOSFET 100 exceeds 606V, the MOSFETs M1, M2, . . . , and Mn
turn on in quick succession, which may be considered nearly
concurrent, and the current flowing through the drain of the SHV
MOSFET 100 is distributed through all of the MOSFETs M1, M2, . . .
, and Mn. This prevents only one of the MOSFETs M1, M2, . . . , and
Mn having the lowest breakdown voltage (e.g., MOSFET M2) from
turning on, carrying all the current, and malfunctioning.
[0043] Referring now to FIG. 2, a cross-section of a layout of a
drain region of a SHV MOSFET 150 without a ballast resistor is
shown. In the drain region of the SHV MOSFET 150, an oxide layer is
split into two portions 152-1 and 152-2 (collectively oxide layer
152), and an N+drain region 154 is implanted in a high-voltage N
well 156. The doping level of the N+drain region 154 is greater
than the doping level of the high-voltage N well 156. A buried N
well 158 is optionally arranged between the high-voltage N well 156
and a P substrate 160. The high-voltage N well 156 and/or the
buried N well 158 is arranged on the P substrate 160. Note that the
polarities of doping materials may be reversed (i.e., N to P, P to
N, N+ to P+, and so on).
[0044] A metal layer 162 is arranged above the N+ drain region 154.
The high-voltage N well 156 can withstand a voltage greater than a
breakdown voltage of the oxide layer 152. Therefore, the metal
layer 162 and the drain of the SHV MOSFET 150 can withstand a
voltage greater than the breakdown voltage of the oxide layer
152.
[0045] It is well known to add a ballast resistor to the drain of
the MOSFET to distribute the current. However, in a typical SHV
process, only metal connections are allowed in the drain region,
for example between 152-1 and 152-2 in FIG. 3A. This limitation is
due to the high voltage present at the drain of the MOSFET 154.
Typical metal resistors are in milli-Ohm range, and it is not
practical to realize a metal resistor with larger resistance and
high current capability. For effective ballast protection, the
resistors need to be in the range of few Ohms.
[0046] The present disclosure describes a method to realize a
resistor in the region of few Ohms using polysilicon, which can
provide adequate protection.
[0047] One way to arrange a ballast resistor connected to the drain
of the SHV MOSFET 150 is to extend the metal layer 162 over the
oxide layer 152. For example, the metal layer 162 can be extended
to the right of the portion 152-2 of the oxide layer 152 or to the
left of the portion 152-1 of the oxide layer 152. In addition, only
the respective portion of the oxide layer 152 is extended along the
metal layer 162. The high-voltage N well 156 is not extended below
the respective portion of the oxide layer 152. Accordingly, there
is no high-voltage N well 156 below the extended portion 152-1 or
152-2 of the oxide layer 152. Consequently, the resistor formed by
the extended metal layer 162, and the portion of the oxide layer
152 extended below the resistor will both break down at the
breakdown voltage of the oxide layer 152.
[0048] Therefore, the resistor needs to be arranged above the N+
drain region 154 so that the high-voltage N well 156 is present
below the resistor to prevent the resistor from breaking down at
the breakdown voltage of the oxide layer 152. The present
disclosure proposes different arrangements of a plurality of
polysilicon regions above the N+ drain region 154. In these
arrangements, the plurality of polysilicon regions is arranged
directly on top of a plurality of portions of the N+ drain region
154 to form a plurality of ballast resistors. Specifically, the
plurality of polysilicon regions is arranged over the N+ drain
region 154 of the MOSFET 150 and between the two oxide layer
portions 152-1 and 152-2 of the MOSFET 150 as explained below.
[0049] Arranging polysilicon regions above the N+ drain region 154,
however, degenerates the conductivity of the N+ drain region 154,
which increases the resistance of the N+ drain region 154. This
phenomenon normally makes arranging polysilicon regions above the
N+ drain region 154 undesirable. In the present application,
however, this phenomenon is desirable because the additional
resistivity of a degenerated N+ drain region 154 increases the
total resistance offered by the polysilicon regions and the
degenerated N+ drain region 154. The values of the combined
resistances offered by the polysilicon regions and the degenerated
N+ drain region 154 can be estimated by estimating the degeneration
of the N+ drain region 154 due to the polysilicon regions.
[0050] Referring now to FIGS. 3A-3D, a plurality of ballast
resistors can be realized by arranging polysilicon over the drain
region in different ways. Specifically, a plurality of polysilicon
layers is arranged above a plurality of portions of the N+ drain
region 154, which is implanted in the high-voltage N well 156.
[0051] In FIGS. 3A and 3B, a cross-section of a layout of a drain
region of a SHV MOSFET 200 with a plurality of ballast resistors
according to a first arrangement is shown. Description of elements
that are similar to the elements shown in FIG. 2 is omitted. The P
substrate 160 is omitted for simplicity of illustration.
[0052] In FIG. 3A, reference numerals 252, 254, and 256
respectively denote Vial, Metal 1, and Contact shown in the
legend.
[0053] In FIG. 3C, reference numerals 162, 352, 354, and 356
respectively denote Metal 2, Vial, Metal 1, and Contact shown in
the legend.
[0054] In FIG. 3A, a plurality of polysilicon regions are arranged
above the N+ drain region 154, of which only a first polysilicon
region comprising elements 202-1 and 202-2 is visible in the
cross-sectional view. In FIG. 3B, a second polysilicon region
comprising elements 204-1 and 204-2 is shown. While only two
polysilicon regions are shown, additional polysilicon regions are
contemplated. Each polysilicon region is arranged above a
corresponding portion of the N+ drain region 154. The portions of
the N+ drain region 154 are arranged along an axis and extend along
(i.e., parallel to) the axis.
[0055] Each polysilicon region extends along (i.e., parallel to)
the axis. Specifically, each element of a polysilicon region is
elongated and extends lengthwise along the axis. More specifically,
a length L of an element of a polysilicon region (e.g., element
202-1) extends along the axis and is greater than a width W of the
element of the polysilicon region.
[0056] The high-voltage N well 156, the optional buried N well 158,
and the P substrate 160 are also arranged and extend along the axis
along which the portions of the N+ drain region 154 are arranged
and extend. The degeneration of the N+ drain region 154 due to
polysilicon extends along the axis as well.
[0057] The first polysilicon region provides a first ballast
resistor. The first ballast resistor is connected to a first
portion of the N+ drain region 154, which forms a first drain
region of a first MOSFET of the SHV MOSFET 200. The second
polysilicon region provides a second ballast resistor. The second
ballast resistor is connected to a second portion of the N+ drain
region 154, which forms a second drain region of a second MOSFET of
the SHV MOSFET 200, and so on.
[0058] In FIGS. 3C and 3D, a cross-section of a layout of a drain
region of a SHV MOSFET 300 with a plurality of ballast resistors
according to a second arrangement is shown. Description of elements
that are similar to the elements shown in FIG. 2 is omitted. The P
substrate 160 is omitted for simplicity of illustration.
[0059] In FIG. 3C, a plurality of polysilicon regions are arranged
above the N+ drain region 154, of which only a first polysilicon
region comprising elements 302-1 and 302-2 is visible in the
cross-sectional view. In FIG. 3D, a second polysilicon region
comprising elements 304-1 and 304-2 is shown. While only two
polysilicon regions are shown, additional polysilicon regions are
contemplated. Each polysilicon region is arranged above a
corresponding portion of the N+ drain region 154. The portions of
the N+ drain region 154 are arranged and extend along an axis.
[0060] Each polysilicon region extends perpendicularly to the axis.
Specifically, each polysilicon region is elongated perpendicular to
the axis. More specifically, a combined width 2W of a polysilicon
region (i.e., a sum of widths W of each of the two elements of a
polysilicon region) extends perpendicularly to the axis and is
greater than a length L of the polysilicon region.
[0061] The high-voltage N well 156, the optional buried N well 158,
and the P substrate 160 are arranged and extend along the axis
along which the portions of the N+ drain region 154 are arranged
and extend. The degeneration of the N+ drain region 154 due to
polysilicon extends along the axis as well.
[0062] The degeneration of the N+ drain region 154 when the
polysilicon is arranged according to the second arrangement is
greater than the degeneration of the N+ drain region 154 when the
polysilicon is arranged according to the first arrangement. Due to
greater degeneration, the N+ drain region 154 offers greater
resistance when the polysilicon is arranged according to the second
arrangement than when the polysilicon is arranged according to the
first arrangement.
[0063] The first polysilicon region provides a first ballast
resistor. The first ballast resistor is connected to a first
portion of the N+ drain region 154, which forms a first drain
region of a first MOSFET of the SHV MOSFET 300. The second
polysilicon region provides a second ballast resistor. The second
ballast resistor is connected to a second portion of the N+ drain
region 154, which forms a second drain region of a second MOSFET of
the SHV MOSFET 300, and so on.
[0064] The foregoing description is merely illustrative in nature
and is in no way intended to limit the disclosure, its application,
or uses. The broad teachings of the disclosure can be implemented
in a variety of forms. Therefore, while this disclosure includes
particular examples, the true scope of the disclosure should not be
so limited since other modifications will become apparent upon a
study of the drawings, the specification, and the following claims.
For purposes of clarity, the same reference numbers will be used in
the drawings to identify similar elements. As used herein, the
phrase at least one of A, B, and C should be construed to mean a
logical (A or B or C), using a non-exclusive logical OR. It should
be understood that one or more steps within a method may be
executed in different order (or concurrently) without altering the
principles of the present disclosure.
* * * * *