U.S. patent application number 14/659662 was filed with the patent office on 2015-07-02 for mixed size data processing operation.
The applicant listed for this patent is ARM Limited. Invention is credited to David James Seal, Nigel John Stephens.
Application Number | 20150186142 14/659662 |
Document ID | / |
Family ID | 43923357 |
Filed Date | 2015-07-02 |
United States Patent
Application |
20150186142 |
Kind Code |
A1 |
Stephens; Nigel John ; et
al. |
July 2, 2015 |
MIXED SIZE DATA PROCESSING OPERATION
Abstract
A data processing system includes a processor core and a memory.
The processor core includes processing circuitry controlled by
control signals generated by decoder circuitry which decodes
program instructions. The program instructions include mixed
operand size instructions (either load/store instructions or
arithmetic instructions) which have a first input operand of a
first operand size and a second input operand of a second input
operand size where the second operand size is smaller than the
first operand size. The processing performed first converts the
second operand so as to have the first operand size. The processing
then generates a third operand using as inputs the first operand of
the first operand size and the second operand now converted to have
the first operand size.
Inventors: |
Stephens; Nigel John;
(Cambridge, GB) ; Seal; David James; (Cambridge,
GB) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
ARM Limited |
Cambridge |
|
GB |
|
|
Family ID: |
43923357 |
Appl. No.: |
14/659662 |
Filed: |
March 17, 2015 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
13353805 |
Jan 19, 2012 |
9009450 |
|
|
14659662 |
|
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Current U.S.
Class: |
712/210 |
Current CPC
Class: |
G06F 9/355 20130101;
G06F 9/30149 20130101; G06F 9/30192 20130101; G06F 9/345 20130101;
G06F 9/30098 20130101; G06F 9/3016 20130101; G06F 9/30043
20130101 |
International
Class: |
G06F 9/30 20060101
G06F009/30 |
Foreign Application Data
Date |
Code |
Application Number |
Mar 8, 2011 |
GB |
1103891.6 |
Claims
1. Apparatus for processing data comprising: processing circuitry
configured to perform data processing operations specified by
program instructions; a plurality of registers, each of said
registers storing a scalar operand; and decoder circuitry coupled
to said processing circuitry and configured to decode said program
instructions to generate control signals for controlling said
processing circuitry to perform data processing operations
specified by said program instructions; wherein said decoder
circuitry is configured to decode a mixed operand size arithmetic
instruction to generate control signals to control said processing
circuitry to perform a mixed size data processing operation having:
(i) a first input operand of a first operand size stored within a
first register of said plurality of registers as specified by a
first register specifying field within said mixed operand size
arithmetic instruction; (ii) a second input operand of a second
operand size stored within a second register of said plurality of
registers as specified by a second register specifying field within
said mixed operand size arithmetic instruction, said second operand
size being less than said first operand size; and (iii) a third
operand of a third operand size, a parameter field within said
mixed operand size arithmetic instruction indicates an operand size
of the second input operand and whether the second input operand is
to be zero extended or sign extended; and said mixed size data
processing operation including processing with a same effect as:
(a) converting said second input operand from said second operand
size to said first operand size in dependence on said parameter
field; and (b) generating said third operand in dependence upon
said first input operand with said first operand size and said
second input operand with said first operand size.
2. Apparatus as claimed in claim 1, wherein said third operand has
said first operand size.
3. (canceled)
4. Apparatus as claimed in claim 1, wherein said generating said
third operand includes setting one of more result flags stored
within said apparatus.
5. Apparatus as claimed in claim 4, wherein said one or more result
flags indicate one of more of: said third operand is a zero; said
third operand is negative; generating said third operand included
generating an unsigned carry out bit of one from said third
operand; and generating said third operand included generating a
signed overflow from said third operand.
6. Apparatus as claimed in claim 1, wherein said parameter field
further indicates a shift amount of said second input operand in
said converting.
7. Apparatus as claimed in claim 6, wherein the parameter field
indicates a size of the second input operand and whether the second
input operand is to be zero extended or sign extended according to
whether a byte, halfword, or word is specified in combination with
said shift amount.
8. Apparatus as claimed in claim 6, wherein said generating has a
same effect as said shifting being performed after said second
input operand has been converted to said first operand size.
9. Apparatus as claimed in claim 1, wherein said third operand is
stored within a third register as specified by a third register
specifying field within said mixed operand size arithmetic
instruction.
10. (canceled)
11. Apparatus as claimed in claim 10, wherein said arithmetic data
operations include at least one of: adding said first input operand
with said first operand size and said second input operand with
said first input size to generate said third operand; and
subtracting said second input operand with said first operand size
from said first input operand with said first operand size to
generate said third operand.
12. Apparatus as claimed in claim 1, comprising a memory having a
memory address space and wherein said third operand is an address
value within said memory address space, said mixed operand size
arithmetic instruction performing one of a load operation and a
store operation between a third register specified by register
specifying field within said mixed operand size arithmetic
instruction and data value stored within said memory at said
address value.
13. Apparatus for processing data comprising: processing means for
performing data processing operations specified by program
instructions; a plurality of register means for storing data, each
of said register means storing a scalar operand; and decoder means
coupled to said processing means for decoding said program
instructions to generate control signals for controlling said
processing means to perform data processing operations specified by
said program instructions; wherein said decoder means is configured
to decode a mixed operand size arithmetic instruction to generate
control signals to control said processing circuitry to perform a
mixed size data processing operation having: (i) a first input
operand of a first operand size stored within a first register
means of said plurality of register means as specified by a first
register specifying field within said mixed operand arithmetic size
instruction; (ii) a second input operand of a second operand size
stored within a second register means of said plurality of register
means as specified by a second register specifying field within
said mixed operand size arithmetic instruction, said second operand
size being less than said first operand size; and (iii) a third
operand of a third operand size, a parameter field within said
mixed operand size arithmetic instruction indicates an operand size
of the second input operand and whether the second input operand is
to be zero extended or sign extended; and said mixed size data
processing operation including processing with a same effect as:
(a) converting said second input operand from said second operand
size to said first operand size in dependence on said parameter
field; and (b) generating said third operand in dependence upon
said first input operand with said first operand size and said
second input operand with said first operand size.
14. A method of processing data using processing circuitry
configured to perform data processing operations specified by
program instructions, a plurality of registers, each of said
registers storing a scalar operand and decoder circuitry coupled to
said processing circuitry and configured to decode said program
instructions to generate control signals for controlling said
processing circuitry to perform data processing operations
specified by said program instructions, said method comprising the
steps of: decoding a mixed operand size arithmetic instruction to
generate control signals to control said processing circuitry to
perform a mixed size data processing operation having: (i) a first
input operand of a first operand size stored within a first
register of said plurality of registers as specified by a first
register specifying field within said mixed operand size arithmetic
instruction; (ii) a second input operand of a second operand size
stored within a second register of said plurality of registers as
specified by a second register specifying field within said mixed
operand size arithmetic instruction, said second operand size being
less than said first operand size; and (iii) a third operand of a
third operand size, a parameter field within said mixed operand
size arithmetic instruction indicates an operand size of the second
input operand and whether the second input operand is to be zero
extended or sign extended; and said mixed size data processing
operation including processing with a same effect as: (a)
converting said second input operand from said second operand size
to said first operand size in dependence on said parameter field;
and (b) generating said third operand in dependence upon said first
input operand with said first operand size and said second input
operand with said first operand size.
15. A computer program product storing in non-transitory form a
computer program including at least one mixed operand size
arithmetic instruction for controlling a computer to perform a
method as claimed in claim 14.
16. A virtual machine comprising a computer controlled by a
computer program to provide an execution environment for executing
program instructions in accordance with a method as claimed in
claim 14.
17. Apparatus as claimed in claim 13, wherein said parameter field
further indicates a shift amount of said second input operand in
said converting.
18. Apparatus as claimed in claim 17, wherein the parameter field
indicates a size of the second input operand and whether the second
input operand is to be zero extended or sign extended according to
whether a byte, halfword, or word is specified in combination with
said shift amount.
19. A method of processing data as claimed in claim 14, wherein
said parameter field further indicates a shift amount of said
second input operand in said converting.
20. A method of processing data as claimed in claim 19, wherein the
parameter field indicates a size of the second input operand and
whether the second input operand is to be zero extended or sign
extended according to whether a byte, halfword, or word is
specified in combination with said shift amount.
Description
[0001] This application is a continuation of U.S. patent
application Ser. No. 13/353,805, filed Jan. 19, 2012, which claims
priority to GB Application No. 1103891.6, filed Mar. 8, 2011, the
entire contents of each of which are incorporated herein by
reference.
BACKGROUND
Technical Field
[0002] This invention relates to the field of data processing
systems. More particularly, this invention relates to the selection
of which data processing operations to support with program
instructions within a data processing system.
INTRODUCTION
[0003] It is known to provide data processing systems which operate
under the control of program instructions. The program instructions
are decoded by decoder circuitry to generate control signals. These
control signals control the processing circuitry to perform data
processing operations specified by those program instructions. An
important aspect of data processing system design is the selection
of which program instructions to support within a data processing
apparatus. This selection is particularly important in the field of
reduced instruction set computing (RISC) which is characterised by
the native support of relatively few program instructions, but with
each of these program instructions being able to execute rapidly
and efficiently.
[0004] It is known to manipulate operand values of different bit
sizes within a data processing system. For example, operands to be
manipulated may be of a word length (32-bits), a double word length
(64 bits), a half word length (16 bits) or a byte length (8 bits).
Other operand widths are also possible. It is generally more
efficient to use an operand size which is not too large for the
typical values of the operand to be stored. It is wasteful of
storage resources and energy to manipulate operands in, for
example, the form of double words when the operand values are such
that they can be fully represented as operands having a length of
one byte.
[0005] A problem arises when it is desired to perform a data
processing operation upon values which are stored within operands
of different operand sizes. One way of dealing with this is to
provide size conversion instructions which when executed change an
operand of a first operand size to an operand of a second operand
size, the second operand size being different to the first operand
size. Once the two values to be manipulated have been placed into
operands having the same operand size, then a data processing
instruction which uses those operands as inputs may then be
executed.
SUMMARY
[0006] Viewed from one aspect the present invention provides
apparatus for processing data comprising:
[0007] processing circuitry configured to perform data processing
operations specified by program instructions;
[0008] a plurality of registers, each of said registers storing a
scalar operand; and
[0009] decoder circuitry coupled to said processing circuitry and
configured to decode said program instructions to generate control
signals for controlling said processing circuitry to perform data
processing operations specified by said program instructions;
wherein
[0010] said decoder circuitry is configured to decode a mixed
operand size instruction to generate control signals to control
said processing circuitry to perform a mixed size data processing
operation having: [0011] (i) a first input operand of a first
operand size stored within a first register of said plurality of
registers as specified by a first register specifying field within
said mixed operand size instruction; [0012] (ii) a second input
operand of a second operand size stored within a second register of
said plurality of registers as specified by a second register
specifying field within said mixed operand size instruction, said
second operand size being less than said first operand size; and
[0013] (iii) a third operand of a third operand size; and
[0014] said mixed size data processing operation including
processing with a same effect as: [0015] (a) converting said second
input operand from said second operand size to said first operand
size; and [0016] (b) generating said third operand in dependence
upon said first input operand with said first operand size and said
second input operand with said first operand size.
[0017] The present techniques recognise that the need to insert
additional instructions merely for the purpose of changing the bit
size of operands before they are subsequently processed by a
following program instruction is wasteful in terms of processing
speed and energy consumption. The need to use these dedicated size
conversion instructions may negate the storage and efficiency
advantages achieved by storing operands with a smaller bit size.
The present techniques overcome this problem by providing one or
more mixed size data processing instructions that serve to both
convert the input operands to have the same bit size and then to
perform a data processing operation which generates a third operand
and is dependent upon the first operand and the second operand
which have previously been converted to have the same bit size.
[0018] It will be appreciated that the third operand which is
generated by the data processing operation may have the same or a
different size to the two input operands. For example, if the data
processing operation was a multiply, then it is possible that the
third operand may have twice the bit size. However, if the data
processing operation was, for example, an addition, a subtraction,
a logical operation or the like, then the third operand may
conveniently have the same size as the first operand size.
[0019] The conversion performed to change the operand size could be
undertaken in a variety of different ways. Two such ways which are
desirable to support with the mixed operand size instructions are
(i): the second input operand is sign extended from the second
operand size to the first operand size; and (ii) the second input
operand is zero extended from the second operand size to the first
operand size.
[0020] The mixed operand size instructions can be provided in a
variety of different forms useful in different circumstances. In
some forms, generating of the third operand may include setting of
one or more result flags within the apparatus. These result flags
may, for example, indicate one or more of (i) the third operand is
a zero; (ii) the third operand is negative; (iii) generating the
third operand included generating an unsigned carry out bit; and
(iv) generating the third operand included generating a signed
overflow.
[0021] A further variant which is sufficiently useful in real world
data processing tasks that it is worthwhile supporting within the
mixed operand size instructions is one in which the generating of
the third operand includes shifting the second input operand. These
variants are useful in dealing with, for example, variable stride
lengths when traversing a data structure. The shift amount that is
employed may be specified by a field within the mixed operand size
instruction, for example, as an immediate field or as an implied
parameter, based upon a characteristic such as the size of a data
value being subject to a load or store operation.
[0022] Within this context it is important that the manipulations
performed are undertaken in an appropriate order. Different results
may be generated if the manipulations are performed in different
orders. In accordance with this reason, the generation has a same
effect as if the shifting had been performed after the second input
operand is converted to the first operand size.
[0023] It will be understood that the actual processing performed
may not follow these steps, but what is significant is that the
result is the same as if these steps had been followed in this
order. The same is generally true of the above described
manipulations. It will be understood by those in this technical
field that many variations are possible of a given manipulation to
be performed that will ultimately generate the same result and the
present technique encompasses all of these variants.
[0024] The third operand when it is generated may be used in a
variety of different ways. In some embodiments the third operand
may be stored within a third register as specified by a third
register specifying field within the mixed operand size
instruction. The third operand thus directly forms the result of
the mixed operand size instruction.
[0025] In this context, the generation performed may be an
arithmetic operation performed upon the first input operand and the
second input operand when they have been converted to have the same
operand size.
[0026] The arithmetic operation could take a variety of forms.
Particularly useful forms are an addition and a subtraction.
[0027] Another general type of mixed operand size instruction is
one used within an apparatus including a memory where the third
operand is used as an address value for one of a load operation and
a store operation with that load operation or store operation being
between a third register specified by a register specifying field
within the mixed operand size instruction and the data value stored
within the memory at the address value specified by the third
operand. This type of instruction is particularly useful when
addressing data structures, such as arrays.
[0028] Viewed from another aspect the present invention provides
apparatus for processing data comprising:
[0029] processing means for performing data processing operations
specified by program instructions;
[0030] a plurality of register means for storing data, each of said
register means storing a scalar operand; and
[0031] decoder means coupled to said processing means for decoding
said program instructions to generate control signals for
controlling said processing means to perform data processing
operations specified by said program instructions; wherein
[0032] said decoder means is configured to decode a mixed operand
size instruction to generate control signals to control said
processing circuitry to perform a mixed size data processing
operation having: [0033] (i) a first input operand of a first
operand size stored within a first register means of said plurality
of register means as specified by a first register specifying field
within said mixed operand size instruction; [0034] (ii) a second
input operand of a second operand size stored within a second
register means of said plurality of register means as specified by
a second register specifying field within said mixed operand size
instruction, said second operand size being less than said first
operand size; and [0035] (iii) a third operand of a third operand
size; and
[0036] said mixed size data processing operation including
processing with a same effect as: [0037] (a) converting said second
input operand from said second operand size to said first operand
size; and [0038] (b) generating said third operand in dependence
upon said first input operand with said first operand size and said
second input operand with said first operand size.
[0039] Viewed from a further aspect the present invention provides
a method of processing data using processing circuitry configured
to perform data processing operations specified by program
instructions, a plurality of registers, each of said registers
storing a scalar operand and decoder circuitry coupled to said
processing circuitry and configured to decode said program
instructions to generate control signals for controlling said
processing circuitry to perform data processing operations
specified by said program instructions, said method comprising the
steps of:
[0040] decoding a mixed operand size instruction to generate
control signals to control said processing circuitry to perform a
mixed size data processing operation having: [0041] (i) a first
input operand of a first operand size stored within a first
register of said plurality of registers as specified by a first
register specifying field within said mixed operand size
instruction; [0042] (ii) a second input operand of a second operand
size stored within a second register of said plurality of registers
as specified by a second register specifying field within said
mixed operand size instruction, said second operand size being less
than said first operand size; and [0043] (iii) a third operand of a
third operand size; and
[0044] said mixed size data processing operation including
processing with a same effect as: [0045] (a) converting said second
input operand from said second operand size to said first operand
size; and [0046] (b) generating said third operand in dependence
upon said first input operand with said first operand size and said
second input operand with said first operand size.
[0047] Further complementary aspects of the invention include a
computer program product storing in non-transitory form a computer
program including at least one mixed operand size instruction for
controlling a computer to perform the above described method as
well as a virtual machine comprising a computer controlled by a
computer program to provide an execution environment for executing
a program in accordance with the above described techniques.
[0048] The above, and other objects, features and advantages of
this invention will be apparent from the following detailed
description of illustrative embodiments which is to be read in
connection with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0049] FIG. 1 schematically illustrates a data processing system
for performing data processing operations under control of program
instructions including mixed operand size instructions;
[0050] FIG. 2 schematically illustrates a mixed operand size
instruction;
[0051] FIG. 3 schematically illustrates the conversion and
generating steps which may be undertaken in response to a mixed
operand size instruction;
[0052] FIG. 4 is a flow diagram schematically illustrating the
decoding and execution of a mixed operand size instruction;
[0053] FIGS. 5A and 5B shows details of the encoding and operation
of a plurality of variants of a mixed operand size instruction
being a load/store instruction; and
[0054] FIG. 6 shows details of the encoding and operation of a
plurality of variants of a mixed operand size instruction being an
add/subtract instruction.
DESCRIPTION OF EXAMPLE EMBODIMENTS
[0055] FIG. 1 schematically illustrates a data processing apparatus
2 having a processor core 4 and a memory 6. The memory 6 stores
operand data 8 to be manipulated and program instructions 10 for
controlling the processor core 4 to perform desired processing
operations. The processor core 4 includes processing circuitry
illustrated in this example in the form of a scalar register file
12, a multiplier 14, a shifter 16 and an adder 18 which together
forming a scalar integer data path. The scalar register file 12
may, for example, contain 31 registers with each of these registers
storing either a 64-bit value or a 32-bit value. This is one source
of the mixed operand sizes as previously discussed.
[0056] The processor core 4 also includes fetch circuitry 20 for
fetching program instructions 10 from the memory 6 and supplying
them to an instruction pipeline 22 where they are processed with a
view to performing the data processing manipulation specified by
those program instructions. Decoder circuitry 24 is responsive to
the program instructions progressing along the instruction pipeline
22 to generate control signals which are used to control the
processing circuitry 12, 14, 16, 18. The processing circuitry
further includes a load/store unit 26 as the processing operations
to be performed may include load operations and store operations. A
load operation copies a data value from the memory 6 into one of
the registers of the scalar register file 12. Conversely, a store
operation copies a data value from one of the registers of the
scalar register file 12 into the memory 6. The memory 6 is
addressed with an address value lying within the memory address
space of the memory 6. This address value may be formed using a
data manipulation involving operands of mixed sizes as will be
discussed further below.
[0057] Also illustrated in FIG. 1 are result flags 28. These result
flags are set when data processing operations are executed to
indicate differing characteristics of the results of those data
processing operations. For example, the result flags may indicate
one or more of: (i) the result operand is zero; (ii) the result
operand is negative; (iii) generating the result operand included
generating an unsigned carry out bit from the result operand; and
(iv) that generating the third operand included generating a signed
overflow from the signed operand. These result flags may also be
set by the mixed operand size instructions described further below.
It will be appreciated by those in this technical field that the
processor core 4 will typically include many further elements but
that these have been omitted from FIG. 1 for the sake of
clarity.
[0058] In operation, a mixed operand size instruction may be
fetched from the memory 6 by the fetch circuitry 20 and supplied to
the instruction pipeline 22. When this mixed operand size
instruction reaches the decode stage of the instruction pipeline,
the decoder circuitry 24 decodes the mixed operand size instruction
and generates control signals which control the processing
circuitry 12, 14, 16, 18, 26 to perform a specified processing
operation. This processing operation has a first input operand of a
first operand size stored within a first register of the scalar
register file 12 as specified by a first register specifying field
within the mixed operand size instruction. The mixed size data
processing operation further has a second input operand of a second
operand size stored within a second register of the scalar register
file 12 as specified by a second register specifying field within
the mixed operand size instruction. This second operand size is
less than the first operand size. For example, the second operand
size may be 32-bits and the first operand size may be 64-bits. It
is also possible that the second operand size could be 16-bits or
8-bits. Furthermore, it is also possible that the first operand
size may be different from 64-bits, such as 32-bits or 16-bits. The
operand sizes may also be larger, such as 128-bits.
[0059] The mixed size data processing instruction has a third
operand of a third operand size. This third operand may be a result
value itself which is stored into a third register of the scalar
register file 12 in the case of an arithmetic instruction, such as
an addition or subtraction. Alternatively, the third operand may be
used when the mixed operand size instruction is a load instruction
or a store instruction as the address value to be addressed within
the memory 6 for a load operation or a store operation taking place
between a third register of the scalar register file as specified
by a third register specifying field within the mixed operand size
instruction and a data value stored within the memory 6 at the
calculated address.
[0060] The processing operations performed by the processing
circuitry 12, 14, 16, 18, 26 in response to the control signals
generated by the decoder circuitry 24 include converting the second
input operand from the second operand size to the first operand
size. For example, the second input operand may be converted from a
32-bit operand to a 64-bit operand. When the second input operand
has been converted to the first operand size, then the third
operand may be generated in dependence on the first input operand
and the second input operand now sharing the first operand size. In
this way a size conversion is combined with a further manipulation,
such as an arithmetic operation or a load/store operation, within
the same instruction being a mixed operand size instruction. This
improves the efficiency of operation since a separate stand-alone
size conversion instruction/operation is not required. The third
operand may also share the first operand size.
[0061] The size conversion performed may sign extend the second
input operand from the second operand size to the first operand
size or alternatively may zero extend the second operand from the
second operand size to the first operand size. These alternatives
may be specified by option specifying bits within the mixed operand
size instruction as will be described further below. The generation
of the third operand can optionally include shifting of the second
input operand. The shift size may be specified by a field within
the mixed operand size instruction either explicitly or implicitly
as part of the opcode. The processing is performed in a manner such
that the result generated as the third operand is the same as when
that produced by first converting the second input operand to the
first operand size followed by the shift operation.
[0062] As previously mentioned, the third operand may be stored
within a third register as specified by a third register specifying
field within the mixed operand size instruction. This type of mixed
operand size instruction is well suited to supporting arithmetic
operations, such as addition and subtraction. Another possibility
is that the third operand serves as an address value for addressing
the memory 6 when the mixed operand size instruction is a load
instruction or a store instruction.
[0063] FIG. 2 schematically illustrates a mixed operand size
instruction. As will be seen, this mixed operand size instruction
includes an opcode 30 which specifies firstly that the instruction
is a mixed operand size instruction and further the particular type
of mixed operand size instruction, namely either a load/store
instruction or an arithmetic instruction having input operands of
different sizes. The mixed operand size instruction further
includes a first register field 32 specifying a register storing a
first input operand, a second register field 34 specifying a
register storing a second input operand and a third register field
36 specifying a register storing an output operand. The mixed
operand size instruction also includes option specifying bits 38
which can be used to specify different variants of the different
types of mixed operand size instructions. These variants include
ones which do or do not set the result flags, do or do not involve
a shift and the amount of that shift, whether the conversion
utilises sign extension or zero extension and the operand size of
the third operand. Further options may be specified for the mixed
operand size instruction.
[0064] FIG. 3 schematically illustrates the processing performed by
the processing circuitry 12, 14, 16, 18, 26 of the processor core 4
when executing a mixed operand instruction. A first operand is read
from a first register. The first operand has a first operand size,
such as for example, 64-bits. A second operation with a second
operand size, such as for example 32-bits, is read from a second
register as specified by a second register specifying field. The
second operand is then converted such that it has the same size as
the first operand. This conversion includes either sign extension
or zero extension into the most significant 32-bits in this
example. The second operand after this sign extension or zero
extension may then optionally be subject to a shift, such as a left
shift by a shift amount specified or implied within the mixed
operand size instruction. The result of the conversion is the first
operand has the first operand size and the second operand has the
first operand size.
[0065] The first operand and the converted second operand are then
used to generate a third operand having a third operand size, which
may for example be the same as the first operand size. This
generation step may optionally set the result flags 28 as
previously described. The generation may be an arithmetic operation
performed with the first operand and the second operand providing
two input operands. The arithmetic operation may, for example, be
an addition or a subtraction.
[0066] At this point the illustration in FIG. 3 shows two
alternative forms of the mixed operation size instruction. In the
first form the mixed operand size instruction is a load instruction
or a store instruction. In this case the third operand serves as
the address value for the load operation or the store operation.
The destination/target register for that load operation or store
operation is specified within a third register specifying field 36
of the mix operand size instruction.
[0067] Another variant of the mixed operand size instruction is an
arithmetic instruction, such as an addition or subtraction when the
original first input operand and second input operand had different
operand sizes. With these variants the third operand forms the
result operand which is stored into a third register as specified
by the third register specifying field 36.
[0068] FIG. 4 is a flow diagram schematically illustrating the
processing performed by the processing circuitry 12, 14, 16, 18, 26
in response to the decoding of a mixed operand size instruction. It
will be appreciated that the flow diagram of FIG. 4 shows this
processing as being performed in a sequential manner. Those
familiar with this technical field will realise that in practice
the ordering of the operations may be varied and some of the
operations may be performed in parallel. The present techniques
encompass these alternatives.
[0069] At step 40 processing waits until a mixed operand size
instruction is received. At step 42 a first operand is read from a
first register and a second operand is read from a second
register.
[0070] At step 46 a determination is made as to whether or not the
mixed operand size instruction decoded at step 40 specified that
signed extension should be used. If signed extension is to be used,
then this is performed at step 48, which also converts the second
operand to the first operand size. If signed extension is not to be
performed, then zero extension is performed at step 50, which also
converts the second operand to the first operand size. After both
steps 48 and 50, processing proceeds to step 52 where a
determination is made as to whether or not the mixed operand size
instruction decoded at step 40 specified any shift was to be
performed on the second operand after it had been converted to have
the first operand size.
[0071] If a shift is to be performed, the step 54 shifts the second
operand by the specified amount. The amount may be explicitly
specified by an immediate field within the mixed operand size
instruction or may be implied by the opcode or in some other
way.
[0072] Step 56 determines if the operation to be performed upon the
first operand and the second operation is an addition. If the
operation to be performed is an addition, then this is undertaken
at step 58 so as to generate the third operand. If the operation to
be performed is not an addition, then step 60 performs a
subtraction of the second operand from the first operand to
generate the third operand. In the present examples, either an
addition or subtraction is performed both when the mixed operand
size instruction is an arithmetic instruction and when the mixed
operand size instruction is a load instruction or a store
instruction. The address calculation associated with the load
instruction or the store instruction includes within it
manipulations which may be either an addition or a subtraction of
the first operand and the second operand.
[0073] Subsequent to either the addition at step 58 or the
subtraction at step 60, a determination is made at step 62 as to
whether or not the mixed operand size instruction decoded at step
48 is a load instruction or a store instruction. If the instruction
is not a load instruction or a store instruction, then step 64
stores the third operand into a third register as specified by the
third register specifying field 36. If the instruction is a load
instruction or a store instruction, then step 66 performs the
specified load or store between the address location within the
memory 6 specified by the third operand and a third register
serving as either the destination for the load or the source for a
store.
[0074] FIGS. 5A and 5B illustrates the syntax and various options
associated with a mixed operand size instruction being either a
load instruction or a store instruction. Considering the mnemonic
column 68 this specifies stores as "STR" and loads "LDR". Whether
the store is of a byte, a halfword, a word or a doubleword is
indicated by the mnemonic including either "B" or "H" or the name
of the register to be transferred which forms part of the opcode.
Whether or not a particular load instruction sign extends or zero
extends the data in memory to generate the third operand is
indicated by the letter "S" which precedes the operand size
letter.
[0075] The mixed operand size instructions are 32-bit instructions.
The bit encoding of these instructions in the case of the load
instruction and the store instruction is shown at 70. The third
register specifying field is a target register R.sub.t. The
description column in FIG. 5 gives a brief description of the
operation performed by each of the variants.
[0076] FIG. 6 is similar to FIG. 5 except that in this case the
mixed operand size instructions are arithmetic instructions
generating an output operand which is the result of the arithmetic
operation performed. The arithmetic operation may be either an
addition or a subtraction. The addition or subtraction may or may
not set the result flags 28 as indicated by the "S" at the end of
the mnemonic. The operand size of the first operand is specified by
the name used to represent the R.sub.n register field, "Wn"
indicates a 32-bit operand and "Xn" indicates a 64-bit operand
where "n" is a register number between 0 and 30. The operand size
of the second operand and whether it should by zero extended or
sign extended is specified by the <extend> parameter which
may be followed by an optional shift amount between 1 and 3. The
bit encoding of the mixed operand size instructions being addition
or subtractions is shown at 72. A brief description of each of the
instructions is given in the description column.
[0077] Although illustrative embodiments of the invention have been
described in detail herein with reference to the accompanying
drawings, it is to be understood that the invention is not limited
to those precise embodiments, and that various changes and
modifications can be effected therein by one skilled in the art
without departing from the scope and spirit of the invention as
defined by the appended claims.
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