U.S. patent application number 14/628825 was filed with the patent office on 2015-06-18 for bonded strained semiconductor with a desired surface orientation and conductance direction.
The applicant listed for this patent is MICRON TECHNOLOGY, INC.. Invention is credited to Leonard Forbes.
Application Number | 20150171165 14/628825 |
Document ID | / |
Family ID | 39028319 |
Filed Date | 2015-06-18 |
United States Patent
Application |
20150171165 |
Kind Code |
A1 |
Forbes; Leonard |
June 18, 2015 |
BONDED STRAINED SEMICONDUCTOR WITH A DESIRED SURFACE ORIENTATION
AND CONDUCTANCE DIRECTION
Abstract
According to various method embodiments, a semiconductor layer
is oriented to a substrate. The semiconductor layer has a surface
orientation and is oriented to the substrate to provide a desired
direction of conductance for the surface orientation. The oriented
semiconductor layer is bonded to the substrate to strain the
semiconductor layer. Various embodiments provide a tensile strain,
and various embodiments provide a compressive strain. Other aspects
and embodiments are provided herein.
Inventors: |
Forbes; Leonard; (Corvallis,
OR) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
MICRON TECHNOLOGY, INC. |
Boise |
ID |
US |
|
|
Family ID: |
39028319 |
Appl. No.: |
14/628825 |
Filed: |
February 23, 2015 |
Related U.S. Patent Documents
|
|
|
|
|
|
Application
Number |
Filing Date |
Patent Number |
|
|
11498586 |
Aug 3, 2006 |
8962447 |
|
|
14628825 |
|
|
|
|
Current U.S.
Class: |
257/288 |
Current CPC
Class: |
H01L 29/7849 20130101;
H01L 29/7843 20130101; H01L 29/66651 20130101; H01L 29/1037
20130101; H01L 29/045 20130101; H01L 21/823807 20130101; H01L
29/1054 20130101 |
International
Class: |
H01L 29/10 20060101
H01L029/10; H01L 29/04 20060101 H01L029/04; H01L 29/78 20060101
H01L029/78 |
Claims
1. A structure, comprising: a substrate; a crystalline
semiconductor layer bonded to the substrate, the semiconductor
layer having a surface orientation and a desired channel
conductance direction for the surface orientation, the crystalline
semiconductor layer having a local strained region; and a gate
oxide over the local strained region, a gate over the gate oxide,
and first and second source/drain regions to provide a channel
region with the desired channel conductance direction within in the
local strained region.
2. The structure of claim 1, wherein the local strained region
includes a uniaxial tensile strain.
3. The structure of claim 1, wherein the local strained region
includes a uniaxial compressive strain.
4. The structure of claim 1, wherein the crystalline semiconductor
layer includes a silicon layer with a (100) crystalline orientation
and the desired channel conductance direction is a <110>
direction with respect to the crystalline orientation.
5. The structure of claim 1, wherein the crystalline semiconductor
layer includes a silicon layer with a (110) crystalline orientation
and the desired channel conductance direction is a <100>
direction with respect to the crystalline orientation.
6. The structure of claim 1, wherein the crystalline semiconductor
layer includes a silicon layer with a (111) crystalline orientation
and the desired channel conductance direction is a <110>
direction with respect to the crystalline orientation.
7. The structure of claim 1, wherein the crystalline semiconductor
layer includes a silicon layer with a (100) crystalline orientation
and the desired channel conductance direction is a <100>
direction with respect to the crystalline orientation.
8. The structure of claim 1, wherein the local strained region has
a strain greater than 0.75%.
9. The structure of claim 1, wherein the local strained region has
a strain within a range between approximately 0.75% and
approximately 1.5%.
10. The structure of claim 1, wherein the local strained region has
a strain within a range between approximately 1.0% and
approximately 1.2%.
11. The structure of claim 1, wherein the crystalline semiconductor
layer has a thickness of approximately 1000 .ANG. or less.
12. The structure of claim 1, wherein the crystalline semiconductor
layer has a thickness of approximately 300 .ANG. to 1000 .ANG..
13. A structure, comprising: a substrate; a crystalline silicon
layer bonded to the substrate, the semiconductor layer having a
thickness of approximately 1000 .ANG. or less and having a surface
orientation and a desired channel conductance direction for the
surface orientation, the crystalline semiconductor layer having a
local strained region that includes a uniaxial strain; and a gate
oxide over the local strained region, a gate over the gate oxide,
and first and second source/drain regions to provide a channel
region with the desired channel conductance direction within in the
local strained region.
14. The structure of claim 13, wherein the uniaxial strain is
compressive.
15. The structure of claim 13, wherein the uniaxial strain is
tensile.
16. The structure of claim 13, wherein the local strained region
has a strain within a range between approximately 0.75% and
approximately 1.5%.
17. The structure of claim 13, wherein the local strain region
includes a first local strain region that includes a tensile
strain, the structure further including a second local strain
region that includes a compressive strain.
18. A structure, comprising: a substrate; a first crystalline
silicon layer bonded to the substrate, the first layer having a
first surface orientation and a first desired channel conductance
direction for the first surface orientation, the first layer having
a first local strained region; a first device formed using the
first layer, including a first gate oxide over the first local
strained region, a first gate over the first gate oxide, and first
and second source/drain regions to provide a first channel region
with the first desired channel conductance direction within in the
first local strained region; a second crystalline silicon layer
bonded to the substrate, the second layer having a second surface
orientation and a second desired channel conductance direction for
the second surface orientation, the second layer having a second
local strained region; and a second device formed using the second
layer, including a second gate oxide over the second local strained
region, a second gate over the second gate oxide, and third and
fourth source/drain regions to provide a second channel region with
the second desired channel conductance direction within in the
second local strained region.
19. The structure of claim 18, wherein the first layer is a (100)
silicon layer, the first desired channel conductance is in the
<110> direction with respect to the (100) silicon layer, the
second layer is (110) silicon layer, and the second desired channel
conductance is in the <100> direction with respect to the
(110) silicon layer.
20. The structure of claim 18, wherein the first local strained
region includes a tensile strain and the second local strained
region includes a compressive strain.
Description
PRIORITY APPLICATION
[0001] This application is a continuation of U.S. application Ser.
No. 11/498,586, filed Aug. 3, 2006, which is incorporated herein by
reference in its entirety.
TECHNICAL FIELD
[0002] This disclosure relates generally to semiconductor
structures, and more particularly, to strained semiconductor,
devices and systems, and methods of forming the strained
semiconductor, devices and systems.
BACKGROUND
[0003] The semiconductor industry continues to strive for
improvements in the speed and performance of semiconductor devices.
Strained silicon technology has been shown to enhance carrier
mobility in both n-channel and p-channel devices, and thus has been
of interest to the semiconductor industry as a means to improve
device speed and performance. Currently, strained silicon layers
are used to increase electron mobility in n-channel CMOS
transistors. There has been research and development activity to
increase the hole mobility of p-channel CMOS transistors using
strained silicon germanium layers on silicon.
[0004] FIG. 1A illustrates a known device for improved hole
mobility with an n-type silicon substrate 101, a silicon germanium
layer 102, a silicon capping layer 103, a gate oxide 104, a gate
105, and N+ source/drain regions 106 and 107. FIG. 1B illustrates a
band structure for the device of FIG. 1A, and indicates that some
carriers or holes are at the silicon-oxide interface and some are
confined in the silicon germanium layer. Both the silicon germanium
and the silicon capping layers will be strained if they are thin.
Alternatively, the silicon germanium layer may be graded to a
relaxed or unstrained layer resulting in more stress in the silicon
cap layer. The crystalline silicon layer is strained by a lattice
mismatch between the silicon germanium layer and the crystalline
silicon layer.
[0005] More recently, strained silicon layers have been fabricated
on thicker relaxed silicon germanium layers to improve the mobility
of electrons in NMOS transistors. Structures with strained silicon
on silicon germanium on insulators have been described as well as
structures with strained silicon over a localized oxide insulator
region. These structures yield high mobility and high performance
transistors on a low capacitance insulating substrate.
[0006] Wafer bending has been used to investigate the effect of
strain on mobility and distinguish between the effects of biaxial
stress and uniaxial stress. Bonding a semiconductor onto bowed or
bent substrates has been disclosed to introduce strain in the
semiconductor. Stress can also be introduced by wafer bonding.
Packaging can introduce mechanical stress by bending.
Compressively-strained semiconductor layers have been bonded to a
substrate.
[0007] FIGS. 2-4 illustrate some known techniques to strain
channels and improve carrier mobilities in CMOS devices. FIG. 2
illustrates a known device design to improve electron mobility in
NMOS transistors using a tensile strained silicon layer on silicon
germanium. As illustrated, a graded silicon germanium layer 208 is
formed on a p-type silicon substrate 209 to provide a relaxed
silicon germanium region 210, upon which a strained silicon layer
211 is grown. The transistor channel is formed in the strained
silicon layer 211. There is a large mismatch in the cell structure
between the silicon and silicon germanium layers, which biaxially
strains the silicon layer. As illustrated in FIG. 3, uniaxial
compressive stress can be introduced in a channel 312 of a PMOS
transistor to improve hole mobility using silicon germanium
source/drain regions 313 in trenches adjacent to the PMOS
transistor. Large improvements in hole mobility, up to 50%, have
been made in PMOS devices in silicon technology using strained
silicon germanium source/drain regions to compressively strain the
transistor channel. Silicon-carbide source/drain regions in
trenches adjacent to an NMOS transistor can introduce tensile
stress and improve electron mobility. FIG. 4 illustrates a known
device design to improve mobility for both NMOS and PMOS
transistors using silicon nitride capping layers 414. These silicon
nitride capping layers can be formed to introduce tensile stress
for NMOS transistors and can be formed to introduce compressive
stress for PMOS transistors.
[0008] Another proposal to improve device speed and performance
involves higher mobility surfaces. For example, it has been
proposed to bond unstrained (110) layers of silicon onto (100)
surface substrates to improve hole mobility in unstrained channel
regions of p-channel MOSFETs, and to amorphize the regions in which
to fabricate n-channel transistors and recrystallize the (100)
silicon seeded by the underlying (100) substrate to provide the
unstrained channel region of n-channel MOSFETs with the high
channel mobility characteristic of the (100) surface.
BRIEF DESCRIPTION OF THE DRAWINGS
[0009] FIG. 1A illustrates a known device for improved hole
mobility, and FIG. 1B illustrates a band structure for the device
of FIG. 1A.
[0010] FIG. 2 illustrates a known device design to improve electron
mobility in NMOS transistors using a tensile strained silicon layer
on silicon germanium.
[0011] FIG. 3 illustrates a known device design to provide uniaxial
compressive stress in a channel of a PMOS transistor using silicon
germanium source/drain regions in trenches adjacent to the PMOS
transistor.
[0012] FIG. 4 illustrates a known device design to improve mobility
for both NMOS and PMOS transistors using silicon nitride capping
layers.
[0013] FIGS. 5A-5I illustrate an embodiment where a semiconductor
layer is bonded to tensile strain the semiconductor layer.
[0014] FIGS. 6A-6K illustrate an embodiment where a semiconductor
layer is bonded to compressive strain the semiconductor layer.
[0015] FIG. 7 illustrates a top view of a structure in which a
plurality of transistors are being formed, according to various
embodiments.
[0016] FIGS. 8-14 illustrate various methods for straining
semiconductor layers.
[0017] FIG. 15 is a simplified block diagram of a high-level
organization of a memory device according to various
embodiments.
[0018] FIG. 16 illustrates a diagram for an electronic system
having one or more transistors with strained channels for improved
mobility, according to various embodiments.
[0019] FIG. 17 illustrates an embodiment of a system having a
controller and a memory, according to various embodiments.
DETAILED DESCRIPTION
[0020] The following detailed description refers to the
accompanying drawings which show, by way of illustration, specific
aspects and embodiments in which the present subject matter may be
practiced. These embodiments are described in sufficient detail to
enable those skilled in the art to practice the present subject
matter. The various embodiments of the present subject matter are
not necessarily mutually exclusive as aspects of one embodiment can
be combined with aspects of another embodiment. Other embodiments
may be utilized and structural, logical, and electrical changes may
be made without departing from the scope of the present subject
matter. In the following description, the terms "wafer" and
"substrate" are interchangeably used to refer generally to any
structure on which integrated circuits are formed, and also to such
structures during various stages of integrated circuit fabrication.
Both terms include doped and undoped semiconductors, epitaxial
layers of a semiconductor on a supporting semiconductor or
insulating material, combinations of such layers, as well as other
such structures that are known in the art. The term "horizontal" as
used in this application is defined as a plane parallel to the
conventional plane or surface of a wafer or substrate, regardless
of the orientation of the wafer or substrate. The term "vertical"
refers to a direction perpendicular to the horizontal as defined
above. Prepositions, such as "on", "side", "higher", "lower",
"over" and "under" are defined with respect to the conventional
plane or surface being on the top surface of the wafer or
substrate, regardless of the orientation of the wafer or substrate.
The following detailed description is, therefore, not to be taken
in a limiting sense, and the scope of the present invention is
defined only by the appended claims, along with the full scope of
equivalents to which such claims are entitled.
[0021] According to various method embodiments, a semiconductor
layer is oriented to a substrate. The semiconductor layer has a
surface orientation and is oriented to the substrate to provide a
desired direction of conductance for the surface orientation. The
oriented semiconductor layer is bonded to the substrate to strain
the semiconductor layer.
[0022] According to various embodiments for forming a transistor, a
strained semiconductor layer is formed on a substrate, which
includes orienting a semiconductor layer to a substrate and bonding
the oriented semiconductor layer to the substrate to strain the
semiconductor layer. The semiconductor layer has a surface
orientation and is oriented to provide a desired direction of
conductance for the surface orientation. A gate insulator is formed
on the strained semiconductor layer, a gate is formed on the gate
insulator, and first and second diffusion regions define a channel
beneath the gate insulator between the first and second diffusion
regions.
[0023] According to various embodiments for forming a CMOS device,
a strained semiconductor layer is formed on a substrate. A first
semiconductor layer and a second semiconductor layer are oriented
to a substrate. The first semiconductor layer has a first surface
orientation and is oriented to provide a first desired direction of
conductance for the first surface orientation to promote electron
mobility. The second semiconductor layer has a second surface
orientation and is oriented to provide a second desired direction
of conductance for the second surface orientation to promote hole
mobility. The first and second oriented semiconductor layers are
bonded to the substrate to strain the semiconductor layer. An
n-channel transistor is formed using the first semiconductor layer
and a p-channel transistor is formed using the second semiconductor
layer.
[0024] Various structure embodiments include a substrate and a
crystalline semiconductor layer bonded to the substrate. The
semiconductor layer has a surface orientation and a desired channel
conductance direction for the surface orientation. The crystalline
semiconductor layer has a local strained region. The structure
further includes a gate oxide over the local strained region, a
gate over the gate oxide, and first and second source/drain regions
to provide a channel region with the desired channel conductance
direction within in the local strained region.
[0025] For example, strips of silicon of different surface
orientations and strip directions can be bonded onto silicon
substrates of various surface orientations. The strip direction
corresponds to a desired direction of conduction. In transistor
embodiments, the desired direction of conduction for the strained
silicon is the channel direction. The strips of silicon can be
locally strained, and can either be tensile strained during the
bonding process to improve the electron mobility and/or can be
compressive strained during the bonding process to improve the hole
mobility. The improved carrier mobility improves CMOS transistor
performance. The carrier wafer or substrate can be a silicon wafer
of any surface orientation, such as the common (100), (110) or
(111) silicon substrates.
[0026] Tensile Strain Embodiments
[0027] FIGS. 5A-5I illustrate an embodiment where a semiconductor
layer is bonded to tensile strain the semiconductor layer, such as
is provided in U.S. Published Patent Application 20040224480, filed
May 7, 2003 and entitled "Micromechanical Strained Semiconductor By
Wafer Bonding." U.S. 20040224480 is incorporated by reference
herein in its entirety.
[0028] FIGS. 5A-5C illustrate a process for forming recesses in a
substrate using a LOCal Oxidation of Silicon (LOCOS) process
according to various embodiments. The LOCOS process is useful to
form recesses in silicon substrates, and one of ordinary skill in
the art will understand, upon reading and comprehending this
disclosure, that other methods to form recesses in substrates can
be used for silicon and other substrates.
[0029] FIG. 5A illustrates a semiconductor structure 515 toward the
beginning of a LOCOS process. The semiconductor structure 515
includes a silicon substrate 516. A layer of silicon nitride 517 is
deposited, such as by Chemical Vapor Deposition (CVD) and the like,
on the silicon substrate and is etched to expose portions of the
silicon substrate for subsequent selective oxidation. One of
ordinary skill in the art will understand, upon reading and
comprehending this disclosure, that the pattern of the silicon
nitride affects the pattern and characteristics of the recesses and
thus of the strained semiconductor film.
[0030] FIG. 5B illustrates the semiconductor structure 515 after
the silicon substrate 516 has been oxidized. In various
embodiments, the oxide 518 is thermally grown by means of wet
oxidation. The oxide grows where there is no masking nitride. At
the edges of the nitride, some oxidant diffuses laterally to grow
under the nitride edges. This lateral growth has the shape of a
slowly tapering oxide wedge and is commonly referred to as a
"bird's beak."
[0031] FIG. 5C illustrates the semiconductor structure 516 after
the oxide has been removed. Recesses 519 remain where the oxidation
occurred. Because of the formation of the recesses 519, the
substrate 516, also referred to as a first wafer, can be referred
to as a dimpled substrate as, in various embodiments, the substrate
has a dimpled appearance. As provided below, a second wafer, or
membrane, is bonded to the substrate such that portions of the
second wafer are strained in the recesses of the substrate.
[0032] One benefit of the LOCOS process is that it is a common
economical semiconductor fabrication process. Another benefit of
the LOCOS process is the tapered bird's beak, which allows for
controlled strain in the film. One of ordinary skill in the art
will understand, upon reading and comprehending this disclosure,
that the slowly tapering shape of the bird's beak is useful to
controllably induce strain in ultra-thin semiconductor films.
However, the tapered bird's beak shape is not required to practice
the present subject matter. One of ordinary skill in the art will
understand, upon reading and comprehending this disclosure, that
other means for creating a recess or void in the substrate can be
used. For example, a grinding process can be used to create a
recess or a trench can be otherwise formed in the substrate.
[0033] FIGS. 5D-5H illustrate a method to form a strained
semiconductor membrane using a bond cut process to bond a membrane
to a substrate with recesses, according to various embodiments. The
bond cut process involves bonding together two substrates, or
wafers, and breaking off a section of at least one of the two
substrate after the substrates have been bonded together. The
substrate is also referred to herein in various embodiments as a
first wafer or dimpled substrate, and the membrane is also referred
to herein in various embodiments as a second wafer.
[0034] FIG. 5D illustrates a sacrificial semiconductor wafer 520,
and FIG. 5E illustrates a semiconductor substrate 516. The
substrate 516 includes a semiconductor material, and includes a
number of recesses 519, such as illustrated in FIG. 5C. In various
embodiments, the semiconductor material includes one of the
following materials: silicon; germanium; silicon-germanium; gallium
arsenide; indium phosphide; and other semiconductor materials. This
list of potential semiconductor materials is not intended to be an
all-inclusive list. The substrate is cut into wafer size patterns,
and integrated circuits are formed thereon. In various embodiments,
the sacrificial wafer includes various semiconductor material
including but not limited to silicon, germanium, silicon-germanium,
gallium arsenide, indium phosphide, and other semiconductor
materials.
[0035] The sacrificial wafer 520 is a single crystal wafer, and is
conditioned by implanting ions 521 into a surface. The ions are
implanted along a plane, represented in FIG. 5D as a line 522, to
define a surface layer 523 with a predetermined thickness. The
plane is approximately parallel to the surface in which the ions
are implanted. In various embodiments, hydrogen ions are used as
implantation ions. The hydrogen ions can include H.sup.+,
H.sub.2.sup.+, D.sup.+, and/or D.sub.2.sup.+ ions. The implanted
ions act to form cavities along the plane 522. The cavities are
joined through thermal processing, allowing the surface layer 523
to be removed from the remaining portion of the sacrificial wafer
524 at the cleavage plane 522. In various embodiments, this thermal
processing occurs while the surface layer 523 is being bonded to
the substrate 516, as shown in FIG. 5F. Once these cavities join
and the surface layer is bonded to the substrate, the surface layer
breaks off of the sacrificial wafer at the cleavage plane and
remains bonded to the substrate. The remaining portion of the
sacrificial wafer 524 can be used to form membranes for other
substrates, thus reducing the overall cost for the manufacturing
process of a wide variety of electronic devices.
[0036] FIG. 5F illustrates the surface layer 523 of the sacrificial
wafer 520 bonded to the substrate 516. Before the surface layer is
bonded to the substrate, the sacrificial wafer and the substrate
can be cleaned using conventional cleaning procedures. In various
embodiments, the bonding force includes the strong Van der Waal's
force that naturally bonds surfaces together as the bonding force.
In various embodiments, the Van der Waal's force provides an
initial bonding force that is strengthened during subsequent
thermal processing. As illustrated in FIG. 5F, the surface layer
523 of the sacrificial wafer 520 is bonded to the substrate 516 in
an environment 525A at a first pressure. In various embodiments,
the first pressure is a vacuum or a low pressure near a vacuum.
[0037] In various embodiments, the bonded wafers are heated to
further bond the surface layer to the substrate and to cut the
surface layer 523 from the sacrificial wafer. In various
embodiments, the environment 525A has a bonding temperature within
a range of approximately 300.degree. C. to 400.degree. C. Heating
the sacrificial wafer joins the cavities in the cleavage plane 522,
allowing the remaining portion 524 of the sacrificial wafer to be
removed from the surface layer, which remains bonded to the
substrate. The remaining portion 524 of the sacrificial wafer can
be prepared and conditioned for another bond cut process.
[0038] The thickness of the surface layer 523 bonded to the
substrate 516 is defined by the depth of ion implantation 521
during the bond cut process. In various embodiments, the thickness
of the surface layer 523 is such that it does not yield or
otherwise plastically deform under the desired mechanical strain
induced by the bond. In various embodiments, the thickness of the
surface layer 523 is less than 200 nm, such that it can be termed
an ultra thin wafer. In various embodiments, the silicon layer has
a thickness of about 0.1 microns (100 nm or 1000 .ANG.). In various
embodiments, the silicon layer has a thickness less than 0.1
microns. In various embodiments, the silicon layer has a thickness
in a range of approximately 300 .ANG. to 1000 .ANG..
[0039] In various embodiments, the silicon film is prepared for
transistor fabrication. In various embodiments, the preparation of
the film includes grinding, polishing, chemical etch, chemical etch
with etch stops, and/or plasma assisted chemical etch, and the
like, which can be used to further thin the film. Thus, the
membrane bonded to the substrate illustrated in FIG. 5G can be
thinner than the surface layer defined in the sacrificial layer in
FIG. 5D. Device processing can be accomplished using conventional
processes and procedures.
[0040] FIG. 5H illustrates the membrane 523 further bonded to the
substrate 516 in the recesses 519 formed therein. The process is
performed in an environment 525B having a second temperature. The
second pressure is greater than the first pressure to force the
membrane into the recesses. The volume between the membrane and the
recessed substrate is a sealed volume, such that the pressure
inside these volumes is approximately the first pressure. In
various embodiments, the second pressure is atmospheric pressure.
In various embodiments, the environment 525B has a bonding
temperature within a range of approximately 800.degree. C. to
1000.degree. C. The portion of the membrane bonded to the substrate
in the recesses is strained. One of ordinary skill in the art will
understand, upon reading and comprehending this disclosure, that
the recesses can be made with appropriate dimension to provide a
desired tensile strain.
[0041] FIG. 5I illustrates a transistor fabricated with a strained
semiconductor membrane, according to various embodiments. The
illustrated transistor 530 includes a crystalline semiconductor
substrate 516 with a recess 519, and a crystalline semiconductor
membrane 523 bonded to the substrate 516 to provide the membrane
523 with a desired tensile strain in the recesses. A gate
dielectric 531 is formed on the strained membrane, and a gate 532
is formed on the gate dielectric 531. First and second diffusion
regions 533 and 534 are formed in the structure 530. The tensile
strained semiconductor membrane 523 between the first and second
diffusion regions 533 and 534 forms a tensile strained channel
region 535.
[0042] Various embodiments tensile strain a thin semiconductor
layer, such as a silicon layer, with a strain greater than 0.5% to
achieve significant mobility enhancement. For further mobility
enhancement, various embodiments tensile strain a thin
semiconductor wafer, such as an ultra-thin silicon wafer with a
thickness within a range of approximately 300 .ANG. to 1000 .ANG.,
with a strain within a range of approximately 0.75% to
approximately 1.5%. Various embodiments tensile strain a thin
semiconductor layer, such as a thin silicon layer, with a strain in
the range of approximately 1% to approximately 1.2% to reduce
unnecessary strain and provide a margin of error without unduly
affecting mobility enhancement. In various embodiments, the film is
approximately 1000 .DELTA. or less. In various embodiments, the
channel length of the transistor is less than or equal to about
1000 .DELTA., and the thickness of the film is less than or equal
to about 300 .DELTA.. The strain enhances mobility in the channel,
thus overcoming problems associated with heavy channel doping.
[0043] Compressive Strain Embodiment
[0044] FIGS. 6A-6K illustrate an embodiment where a semiconductor
layer is bonded to compressive strain the semiconductor layer, such
as is provided in U.S. patent application Ser. No. 11/356,335,
filed Feb. 16, 2006 and entitled "Localized Compressive Strained
Semiconductor." U.S. patent application Ser. No. 11/356,335 is
incorporated by reference herein in its entirety. The description
that follows refers to embodiments with silicon and silicon dioxide
or oxide. However, those of ordinary skill in the art will
understand how to implement the teachings herein with other
semiconductors and insulators.
[0045] FIG. 6A illustrates a crystalline silicon substrate 636 with
a mask layer 637. The mask layer is patterned to define the areas
where there will be localized compressive strain. Thus, the defined
areas are used to provide a channel with compressive strain to
improve hole mobility for p-channel transistors. In various
embodiments, the mask is a silicon nitride. A thin native oxide is
between the silicon nitride and the crystalline silicon
substrate.
[0046] As illustrated in FIG. 6B, the exposed crystalline silicon
636 is etched at 638 to a desired depth on each side of the mask
637. A thick oxide layer 639 is deposited. The resulting structure
is planarized, such as may be performed by a chemical mechanical
planarization (CMP) process. The planarizing process stops on the
raised silicon areas 640 to leave islands or strips of silicon 640
embedded in an oxide 639, such as is illustrated in the side view
of FIG. 6C and the top view of FIG. 6D.
[0047] FIG. 6E illustrates the structure after an oxidation
process. The dotted line 641 corresponds to the top surface 641 of
the structure illustrated in FIG. 6C, and the dotted lines 642
correspond to the edges 642 of the oxide islands in FIG. 6C. The
exposed silicon island 640 oxides rapidly, while the regions
covered by the deposited oxide 639 oxidize much more slowly. The
thickness of the deposited oxide and the subsequent oxidation is
timed to leave the resulting silicon surface planar under the
oxides of different thickness, and to provide the desired strain,
as will be evident upon reading and comprehending this
specification.
[0048] FIG. 6F illustrates the structure after the oxide is etched
back to expose the crystalline substrate 643 and reduce the oxide
in the island portion 640 of the oxide. A "bird's beak" is left at
the edges of the oxide islands. The bird's beak has a similar shape
to that formed by a LOCal Oxidation of Silicon (LOCOS) process. A
native oxide 644 forms on the exposed silicon areas by exposure to
air, water or peroxide.
[0049] FIGS. 6G-6H illustrate methods for providing an amorphous
silicon layer in contact with the crystalline silicon on one side
of the oxide island, according to various embodiments. As
illustrated in FIG. 6G, an amorphous silicon layer 645 is
deposited, and a silicon implant 646 breaks up the oxide such that
the crystalline silicon substrate at 647 is able to seed the
crystalline growth of the amorphous silicon layer. As illustrated
in FIG. 6H, the native oxide is removed at 647 from one side of the
oxide island and amorphous silicon 645 is deposited and patterned
over the oxide islands. According to various embodiments, the
thickness of the silicon film is within a range from approximately
100 nm to approximately 200 nm. Such thicknesses are capable of
being mechanically compressed without affecting yield.
[0050] FIG. 6I illustrates a recrystallization process for the
amorphous silicon layer, and further illustrates the bonding of the
crystallized layer after the oxide island is removed. The
recrystallization process is also referred to as a solid phase
epitaxial (SPE) process, which includes depositing a thin amorphous
silicon layer and annealing the structure to recrystallize the
amorphous silicon, where one end of the amorphous layer is seeded
to promote a desired crystalline growth. The recrystallization, as
illustrated by the arrows 648, is seeded at 647 where the silicon
layer 645 is in direct contact with the crystalline silicon
substrate 636, and thus only grows from one side since the other
side still has the unperturbed native oxide 643. According to
various embodiments, the silicon film is recrystallized at
temperatures from approximately 550.degree. C. to approximately
700.degree. C. The transistor channel is formed in this
recrystallized silicon strip. The oxide island is etched from
underneath the silicon strip to leave an empty space beneath the
silicon strip. As illustrated by the arrow 649, a silicon strip or
silicon bridge layer is influenced toward and bonded to the surface
beneath the silicon layer. In various embodiments, the naturally
occurring Van der Waal's force is sufficient to influence the
bridge layer or film 645 into contact with the surface 650 beneath
the silicon layer. In various embodiments, a nano-imprint mask is
used to assist with influencing the film into contact with the
surface beneath the silicon layer.
[0051] FIG. 6J illustrates the silicon layer bonded to the surface
beneath the silicon layer. Since the length of the bowed silicon
film strip is longer than the planar surface region of the silicon
substrate, the film 645, now in crystalline form, will be under
compressive stress, as illustrated by the arrows 651, after bonding
to the substrate surface.
[0052] FIG. 6K illustrates a PMOS transistor 652 fabricated in the
structure formed with crystalline silicon under compression. The
remaining steps in the PMOS transistor fabrication can be achieved
by conventional techniques, in which the compressively-strained
ultra-thin silicon strip 645 forms the transistor channel region.
For example, a gate insulator 653, such as silicon oxide or other
gate insulator, is formed on the structure, a gate 654 is formed on
the gate insulator, and source/drain regions 655 are formed to
define a channel 645 beneath the gate and between the source/drain
regions. The source/drain regions can be formed by an ion
implantation process.
[0053] Locally Strained Semiconductor Embodiment
[0054] FIG. 7 illustrates a top view of a structure in which a
plurality of transistors are being formed, according to various
embodiments. The oxide 756 is illustrated by the dotted line and
the pattern of silicon strips 757 is also illustrated. In another
embodiment, a number of oxide regions are combined in the column
direction to form one oxide area. For example, the column of oxide
regions 756A-756E can be formed as one oxide area. As discussed
above, these oxide areas can be used to provide a local tensile
strain to the silicon strips or a local compressive strain to the
silicon strips. According to various embodiments, the same
substrate includes silicon strips with both locally tensile
strained regions to promote electron mobility and locally
compressive strained regions to promote hole mobility.
[0055] Surface Orientation/Conductance Direction
[0056] FIGS. 8-13 illustrate various methods for straining
semiconductor layers. With reference to the embodiment illustrated
in FIG. 8, as illustrated at 858 a semiconductor layer is oriented
to a substrate to provide a desired direction of conductance of a
surface orientation of the semiconductor layer. In embodiments in
which strips of semiconductor are bonded to the substrate, the
strips are formed in the direction of conductance. Other
embodiments use larger membranes or films. The surface crystal
orientation is conventionally provided using Miller indices in
parentheses. The direction of conduction is provided using X Y Z
coordinates in angle brackets, and is based on the same coordinate
system used to identify the surface orientation of the
semiconductor layer. For a given surface crystal orientation, some
directions are more conductive than others. At 859, the oriented
semiconductor layer is bonded to the substrate to strain the
semiconductor layer. Various embodiments induce a compressive
strain and various embodiments induce a tensile strain when the
layer is bonded to the substrate. The thickness of the layer is
sufficiently thin to permit the strain without yield. Various
embodiments create the layer using a bond cut process, such as
illustrated in FIGS. 5D-5G. Various embodiments remove the back of
a sacrificial wafer, which has been bonded to the substrate, by a
mechanical and chemical etch procedure. Various embodiments create
the layer by depositing an amorphous layer and recrystallizing the
layer using a solid phase epitaxial process, such as illustrated in
FIGS. 6G-I.
[0057] FIG. 9 illustrates an embodiment of a method of bonding a
(100) silicon layer to provide desired conductance in the
<110> direction. In embodiments in which strips of silicon
are bonded to the substrate, the strips are formed in the
<110> direction. At 958, a (100) silicon layer is oriented to
a substrate to provide a <110> direction of conductance for
the (100) silicon layer. At 959, the oriented (100) silicon layer
is bonded to the substrate to strain the silicon layer. Various
embodiments bond the layer onto raised oxide areas on any carrier
wafer to improve hole mobility by removing the oxide from under the
strips and completing the bonding to leave the strip in compressive
stress. Various embodiments bond the silicon layer over recessed
oxide areas on any carrier wafer to improve electron mobility by
removing the oxide from under the strips and completing the bonding
to leave the strip in tensile stress.
[0058] FIG. 10 illustrates an embodiment of a method of bonding a
(110) silicon layer to provide desired conductance in the
<100> direction. Other directions of conductance can be used
with respect to the (110) silicon layer. In embodiments in which
strips of silicon are bonded to the substrate, the strips are
formed in the <100> direction. At 1058, a (110) silicon layer
is oriented to a substrate to provide a <100> direction of
conductance for the (110) silicon layer. At 1059, the oriented
(110) silicon layer is bonded to the substrate to strain the
silicon layer. Various embodiments bond the layer onto raised oxide
areas on any carrier wafer to improve hole mobility by removing the
oxide from under the strips and completing the bonding to leave the
strip in compressive stress. Various embodiments bond the silicon
layer over recessed oxide areas on any carrier wafer to improve
electron mobility by removing the oxide from under the strips and
completing the bonding to leave the strip in tensile stress.
[0059] FIG. 11 illustrates an embodiment of a method of bonding a
(111) silicon layer to provide desired conductance in the
<110> direction. In embodiments in which strips of silicon
are bonded to the substrate, the strips are formed in the
<110> direction. At 1158, a (111) silicon layer is oriented
to a substrate to provide a <110> direction of conductance
for the (111) silicon layer. At 1159, the oriented (111) silicon
layer is bonded to the substrate to strain the silicon layer.
Various embodiments bond the layer onto raised oxide areas on any
carrier wafer to improve hole mobility by removing the oxide from
under the strips and completing the bonding to leave the strip in
compressive stress. Various embodiments bond the silicon layer over
recessed oxide areas on any carrier wafer to improve electron
mobility by removing the oxide from under the strips and completing
the bonding to leave the strip in tensile stress.
[0060] FIG. 12 illustrates an embodiment of a method of bonding
(100) silicon layers to provide desired conductance in the
<110> direction. As illustrated at 1258A and 1259A, a first
(100) silicon layer is oriented to a substrate to provide a
<110> direction of conductance of the first (100) silicon
layer, and the first (100) silicon layer is bonded to the substrate
to tensile strain the first silicon layer. As illustrated in 1258B
and 1259B, a second (100) silicon layer is oriented to a substrate
to provide a <110> direction of conductance of the first
(100) silicon layer, and the second (100) silicon layer is bonded
to the substrate to compressive strain the second silicon layer.
Thus, on a same substrate, the strips with local tensile stress
improve the mobility of n-channel MOSFETs and the strips with local
compressive stress improve hole mobility of p-channel MOSFETs.
Thus, the present subject matter can be implemented in CMOS
design.
[0061] FIG. 13 illustrates an embodiment of a method of bonding a
(100) silicon layer to provide a desired conductance in the
<110> direction and bonding a (110) silicon layer to provide
a desired conductance in the <100> direction. At 1358, a
(100) silicon layer is oriented to a substrate to provide a
<110> direction of conductance and a (110) silicon layer is
oriented to the substrate to provide a <100> direction of
conductance. At 1359, the oriented (100) silicon layer and the
oriented (110) silicon layer are bonded to the substrate to strain
the semiconductor layers. Local strain for either the (100) layer
or the (110) layer can be either tensile strain or compressive
strain. Since in this case the strips will all have the same height
above the smooth surface of the carrier wafer the backs of the
strips can also be mechanically polished as well as chemically
polished. Removing the oxide from under the strips and completing
the bonding will leave the strips in tensile stress improving the
mobility of both electrons and holes in MOSFETs. The MOSFETs can be
fabricated using conventional techniques.
[0062] The direction of a uniaxial strain can affect the carrier
mobility. For example, as reported by Irie et al., "In-Plane
Mobility Anisotropy and Universality Under Uni-Axial Strains In N-
and P-MOS Inversion Layers On (100), (110), and (111) Si," IEDM
Technical Digest, 13-15 Dec. 2004, pp. 224-228, a <110>
channel direction and a tensile strain direction in the <110>
direction is desirable for improved electron mobility in a (100)
silicon layer and a <100> channel direction and a tensile
strain in the <100> direction is desirable for improved hole
mobility in a (110) silicon layer. Thus, various embodiments
uniaxially strain the semiconductor layer in a desired direction
with respect to the desired direction for conduction to improve
carrier mobility. With reference to FIG. 14, at 1458 a
semiconductor layer is oriented to a substrate to provide a desired
direction of conductance for a surface orientation of the
semiconductor layer. At 1459 the oriented semiconductor layer is
bonded to the substrate to strain the semiconductor layer. As
illustrated by 1460, the bonding process includes uniaxially
straining the semiconductor layer in a desired direction with
respect to the desired direction of conduction to improve
conductance.
[0063] Device/System Embodiments
[0064] FIG. 15 is a simplified block diagram of a high-level
organization of various embodiments of a memory device according to
various embodiments of the present subject matter. The illustrated
memory device 1561 includes a memory array 1562 and read/write
control circuitry 1563 to perform operations on the memory array
via communication line(s) or channel(s) 1564. The illustrated
memory device 1561 may be a memory card or a memory module such as
a single inline memory module (SIMM) and dual inline memory module
(DIMM). One of ordinary skill in the art will understand, upon
reading and comprehending this disclosure, that semiconductor
components in the memory array and/or the control circuitry are
able to be fabricated using the strained semiconductor, as
described above. For example, in various embodiments, the memory
array and/or the control circuitry include p-channel transistors
with improved hole mobility and/or n-channel transistors with
improved electron mobility, as disclosed herein. The structure and
fabrication methods for these devices have been described
above.
[0065] The illustrated memory array 1562 includes a number of
memory cells 1565 arranged in rows and columns, where word lines
1566 connect the memory cells in the rows and bit lines 1567
connect the memory cells in the columns. The read/write control
circuitry 1563 includes word line select circuitry 1568, which
functions to select a desired row. The read/write control circuitry
1563 further includes bit line select circuitry 1569, which
functions to select a desired column. The read/write control
circuitry 1563 further includes read circuitry 1570, which
functions to detect a memory state for a selected memory cell in
the memory array 1562.
[0066] FIG. 16 illustrates a diagram for an electronic system
having one or more transistors with strained channels for improved
mobility, according to various embodiments of the present subject
matter. Electronic system 1671 includes a controller 1672, a bus
1673, and an electronic device 1674, where the bus 1673 provides
communication channels between the controller 1672 and the
electronic device 1674. In various embodiments, the controller
and/or electronic device include p-channel transistors with
improved hole mobility and/or n-channel transistors with improved
electron mobility, as disclosed herein. The illustrated electronic
system 1671 may include, but is not limited to, information
handling devices, wireless systems, telecommunication systems,
fiber optic systems, electro-optic systems, and computers.
[0067] FIG. 17 illustrates an embodiment of a system 1775 having a
controller 1776 and a memory 1777, according to various embodiments
of the present subject matter. The controller 1776 and/or memory
1777 may include p-channel transistors with improved hole mobility
and/or n-channel transistors with improved electron mobility, as
disclosed herein. The illustrated system 1775 also includes an
electronic apparatus 1778 and a bus 1779 to provide communication
channel(s) between the controller and the electronic apparatus, and
between the controller and the memory. The bus may include an
address, a data bus, and a control bus, each independently
configured; or may use common communication channels to provide
address, data, and/or control, the use of which is regulated by the
controller. In an embodiment, the electronic apparatus 1778 may be
additional memory configured similar to memory 1777. An embodiment
may include a peripheral device or devices 1780 coupled to the bus
1779. Peripheral devices may include displays, additional storage
memory, or other control devices that may operate in conjunction
with the controller and/or the memory. In an embodiment, the
controller is a processor. Any of the controller 1776, the memory
1777, the electronic apparatus 1778, and the peripheral devices
1780 may include p-channel transistors with improved hole mobility
and/or n-channel transistors with improved electron mobility, as
disclosed herein. The system 1775 may include, but is not limited
to, information handling devices, telecommunication systems, and
computers. Applications containing strained semiconductor films as
described in this disclosure include electronic systems for use in
memory modules, device drivers, power modules, communication
modems, processor modules, and application-specific modules, and
may include multilayer, multichip modules. Such circuitry can
further be a subcomponent of a variety of electronic systems, such
as cameras, video recorders and players, televisions, displays,
games, phones, clocks, personal computers, wireless devices,
automobiles, aircrafts, industrial control systems, and others.
[0068] The memory may be realized as a memory device containing
p-channel transistors with improved hole mobility and/or n-channel
transistors with improved electron mobility, as disclosed herein.
It will be understood that embodiments are equally applicable to
any size and type of memory circuit and are not intended to be
limited to a particular type of memory device. Memory types include
a DRAM, SRAM (Static Random Access Memory) or Flash memories.
[0069] Additionally, the DRAM could be a synchronous DRAM commonly
referred to as SGRAM (Synchronous Graphics Random Access Memory),
SDRAM (Synchronous Dynamic Random Access Memory), SDRAM II, and DDR
SDRAM (Double Data Rate SDRAM).
[0070] This disclosure includes several processes, circuit
diagrams, and semiconductor structures. The present subject matter
is not limited to a particular process order or logical
arrangement. Although specific embodiments have been illustrated
and described herein, it will be appreciated by those of ordinary
skill in the art that any arrangement which is calculated to
achieve the same purpose may be substituted for the specific
embodiments shown. This application is intended to cover
adaptations or variations of the present subject matter. It is to
be understood that the above description is intended to be
illustrative, and not restrictive. Combinations of the above
embodiments, and other embodiments, will be apparent to those of
skill in the art upon reviewing the above description. The scope of
the present subject matter should be determined with reference to
the appended claims, along with the full scope of equivalents to
which such claims are entitled.
* * * * *