U.S. patent application number 14/104514 was filed with the patent office on 2015-05-28 for packaging substrate and fabrication method thereof.
This patent application is currently assigned to Siliconware Precision Industries Co., Ltd. The applicant listed for this patent is Siliconware Precision Industries Co., Ltd. Invention is credited to Chi-Ching Ho, Sheng-Che Huang, Ying Chou Tsai.
Application Number | 20150144384 14/104514 |
Document ID | / |
Family ID | 53181673 |
Filed Date | 2015-05-28 |
United States Patent
Application |
20150144384 |
Kind Code |
A1 |
Ho; Chi-Ching ; et
al. |
May 28, 2015 |
PACKAGING SUBSTRATE AND FABRICATION METHOD THEREOF
Abstract
A packaging substrate is disclosed, which includes: a dielectric
layer; a circuit layer embedded in and exposed from a surface of
the dielectric layer, wherein the circuit layer has a plurality of
conductive pads; and a plurality of conductive bumps formed on the
conductive pads and protruding above the surface of the dielectric
layer. As such, when an electronic element is disposed on the
conductive pads through a plurality of conductive elements, the
conductive elements can come into contact with both top and side
surfaces of the conductive bumps so as to increase the contact area
between the conductive elements and the conductive pads, thereby
strengthening the bonding between the conductive elements and the
conductive pads and preventing delamination of the conductive
elements from the conductive pads.
Inventors: |
Ho; Chi-Ching; (Taichung,
TW) ; Tsai; Ying Chou; (Taichung, TW) ; Huang;
Sheng-Che; (Taichung, TW) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Siliconware Precision Industries Co., Ltd |
Taichung |
|
TW |
|
|
Assignee: |
Siliconware Precision Industries
Co., Ltd
Taichung
TW
|
Family ID: |
53181673 |
Appl. No.: |
14/104514 |
Filed: |
December 12, 2013 |
Current U.S.
Class: |
174/257 ;
174/261; 174/264; 29/848 |
Current CPC
Class: |
H01L 21/4853 20130101;
H01L 23/49838 20130101; H01L 2224/81193 20130101; H05K 3/064
20130101; H05K 3/205 20130101; H01L 21/4857 20130101; H01L
2221/68345 20130101; H05K 3/4038 20130101; H05K 3/4007 20130101;
H01L 23/49866 20130101; H01L 2224/16225 20130101; H01L 24/16
20130101; H01L 21/486 20130101; Y02P 70/50 20151101; H01L 23/49827
20130101; Y10T 29/49158 20150115; H01L 23/49811 20130101; H01L
21/6835 20130101; H01L 2224/16238 20130101; H01L 23/49822 20130101;
H05K 2201/0376 20130101; H05K 3/3436 20130101; H01L 24/81 20130101;
H05K 3/4682 20130101; Y02P 70/613 20151101 |
Class at
Publication: |
174/257 ;
174/261; 174/264; 29/848 |
International
Class: |
H05K 1/11 20060101
H05K001/11; H05K 3/10 20060101 H05K003/10; H05K 1/09 20060101
H05K001/09 |
Foreign Application Data
Date |
Code |
Application Number |
Nov 27, 2013 |
TW |
102143206 |
Claims
1. A packaging substrate, comprising: a dielectric layer having
opposite first and second surfaces; a first circuit layer embedded
in the first surface of the dielectric layer and having a surface
exposed from the first surface of the dielectric layer, wherein the
first circuit layer has a plurality of first conductive pads; and a
plurality of conductive bumps formed on the first conductive pads
and protruding above the first surface of the dielectric layer.
2. The substrate of claim 1, wherein the surface of the first
circuit layer is flush with or lower than the first surface of the
dielectric layer.
3. The substrate of claim 1, further comprising an insulating layer
formed on the first surface of the dielectric layer and the surface
of the first circuit layer and having a plurality of openings for
exposing the conductive bumps.
4. The substrate of claim 1, further comprising a second circuit
layer formed on the second surface of the dielectric layer.
5. The substrate of claim 4, further comprising a plurality of
conductive vias formed in the dielectric layer for electrically
connecting the first circuit layer and the second circuit
layer.
6. The substrate of claim 4, further comprising an insulating layer
formed on the second surface of the dielectric layer and the second
circuit layer and having a plurality of openings for exposing
portions of the second circuit layer.
7. The substrate of claim 1, wherein the conductive bumps are less,
equal to or greater in width than the first conductive pads.
8. The substrate of claim 1, wherein the conductive bumps are made
of copper.
9. A method for fabricating a packaging substrate, comprising the
steps of: providing a carrier having a first circuit layer formed
thereon, wherein the first circuit layer has a plurality of first
conductive pads; forming a dielectric layer on the carrier and the
first circuit layer, wherein the dielectric layer has a first
surface in contact with and attached to the carrier and a second
surface opposite to the first surface; removing the carrier so as
to expose a surface of the first circuit layer from the first
surface of the dielectric layer; and forming on the first
conductive pads a plurality of conductive bumps protruding above
the first surface of the dielectric layer.
10. The method of claim 9, wherein the surface of the first circuit
layer is flush with or lower than the first surface of the
dielectric layer.
11. The method of claim 9, wherein the carrier has a conductive
layer that allows the first circuit layer to be formed thereon, and
the conductive layer is exposed after removing the carrier such
that the step of forming the conductive bumps further comprises:
forming a metal layer on the conductive layer; and removing
portions of the metal layer and the conductive layer under the
metal layer so as for the remaining portions of the metal layer and
the conductive layer to form the conductive bumps.
12. The method of claim 9, wherein the carrier has a conductive
layer that allows the first circuit layer to be formed thereon, and
the conductive layer is exposed after removing the carrier such
that the step of forming the conductive bumps further comprises:
forming a resist layer on the conductive layer and forming a
plurality of openings in the resist layer corresponding in position
to the first conductive pads; forming a metal layer in the openings
of the resist layer; and removing the resist layer so as for the
metal layer to form the conductive bumps.
13. The method of claim 9, wherein the step of forming the
conductive bumps further comprises: forming a metal layer on the
first surface of the dielectric layer and the surface of the first
circuit layer; and removing portions of the metal layer so as for
the remaining portions of the metal layer to form the conductive
bumps.
14. The method of claim 9, wherein the carrier has a metal layer,
and after the carrier is removed, portions of the metal layer are
removed so as for the remaining portions of the metal layer to form
the conductive bumps.
15. The method of claim 9, further comprising forming an insulating
layer on the first surface of the dielectric layer and the surface
of the first circuit layer and forming a plurality of openings in
the insulating layer for exposing the conductive bumps.
16. The method of claim 9, further comprising forming a second
circuit layer on the second surface of the dielectric layer.
17. The method of claim 16, further comprising forming a plurality
of conductive vias in the dielectric layer for electrically
connecting the first circuit layer and the second circuit
layer.
18. The method of claim 16, further comprising forming an
insulating layer on the second surface of the dielectric layer and
the second circuit layer and forming a plurality of openings in the
insulating layer for exposing portions of the second circuit
layer.
19. The method of claim 9, wherein the conductive bumps are less,
equal to or greater in width than the first conductive pads.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to packaging substrates, and
more particularly, to a packaging substrate and a fabrication
method thereof for improving the product reliability.
[0003] 2. Description of Related Art
[0004] Along with the rapid development of electronic industries,
electronic products are developed toward the trend of
multi-function and high performance. To improve the wiring
precision of multi-layer circuit boards, redistribution layer (RDL)
technologies have been developed to alternately stack a plurality
of dielectric layers and circuit layers on one another and form a
plurality of conductive vias in the dielectric layers to
electrically connect upper and lower circuit layers. Further,
coreless packaging technologies have been developed to meet the
miniaturization requirement.
[0005] FIGS. 1A to 1F are schematic cross-sectional views showing a
method for fabricating a packaging substrate 1 according to the
prior art.
[0006] Referring to FIG. 1A, a carrier 10 is provided and a
conductive layer 100 is formed on upper and lower sides of the
carrier 10.
[0007] Referring to FIG. 1B, a first circuit layer 11 is formed on
the conductive layer 100 by electroplating. The first circuit layer
11 has a plurality of first conductive pads 110.
[0008] Referring to FIG. 1C, a dielectric layer 12 is formed on the
carrier 10 and the first circuit layer 11.
[0009] Referring to FIG. 1D, a second circuit layer 13 is formed on
the dielectric layer 12. The second circuit layer 13 has a
plurality of second conductive pads 130. Further, a plurality of
conductive vias 14 are formed in the dielectric layer 12 for
electrically connecting the first circuit layer 11 and the second
circuit layer 13.
[0010] Referring to FIG. 1E, the carrier 10 is removed to expose
the conductive layer 100.
[0011] Referring to FIG. 1F, the conductive layer 100 is removed to
expose the first circuit layer 11. Then, a first solder mask layer
15 is formed on an upper side of the dielectric layer 12 and the
first circuit layer 11 and a plurality of first openings 150 are
formed in the first solder mask layer 15 so as to expose the first
conductive pads 110 and portions of the dielectric layer 12 around
peripheries of the first conductive pads 110, and a second solder
mask layer 16 is formed on a lower side of the dielectric layer 12
and the second circuit layer 13 and a plurality of second openings
160 are formed in the second solder mask layer 16 to expose the
second conductive pads 130.
[0012] Subsequently, referring to FIG. 1G an electronic element 9
is disposed on the first conductive pads 110 through a plurality of
conductive elements 18 made of such as a solder material. That is,
the conductive elements 18 come into contact with surfaces 110a of
the first conductive pads 110. However, such planar contact
surfaces lead to small contact area between the conductive elements
18 and the first conductive pads 110, thus adversely affecting the
bonding strength between the conductive elements 18 and the first
conductive pads 110 and easily causing delamination of the
conductive elements 18 from the first conductive pads 110.
Therefore, the product reliability is reduced.
[0013] In an embodiment, after the carrier 10 is removed, the first
circuit layer 11 is etched to have a surface lower than that of the
dielectric layer 12. That is, the first circuit layer 11 is
recessed into the dielectric layer 12 about 5 um, which however
easily causes non-wetting of the conductive elements 18 and
consequently causes the conductive elements 18 to be stuck on the
surface of the dielectric layer 12 without electrically connecting
to the first conductive pads 110.
[0014] Therefore, there is a need to provide a packaging substrate
and a fabrication method thereof so as to overcome the
above-described drawbacks.
SUMMARY OF THE INVENTION
[0015] In view of the above-described drawbacks, the present
invention provides a packaging substrate, which comprises: a
dielectric layer having opposite first and second surfaces; a first
circuit layer embedded in the first surface of the dielectric layer
and having a surface exposed from the first surface of the
dielectric layer, wherein the first circuit layer has a plurality
of first conductive pads; and a plurality of conductive bumps
formed on the first conductive pads and protruding above the first
surface of the dielectric layer.
[0016] In the above-described substrate, the conductive bumps can
be made of copper.
[0017] The present invention further provides a method for
fabricating a packaging substrate, which comprises the steps of:
providing a carrier having a first circuit layer formed thereon,
wherein the first circuit layer has a plurality of first conductive
pads; forming a dielectric layer on the carrier and the first
circuit layer, wherein the dielectric layer has a first surface in
contact with and attached to the carrier and a second surface
opposite to the first surface; removing the carrier so as to expose
a surface of the first circuit layer from the first surface of the
dielectric layer; and forming on the first conductive pads a
plurality of conductive bumps protruding above the first surface of
the dielectric layer.
[0018] In an embodiment, the carrier has a conductive layer that
allows the first circuit layer to be formed thereon, and the
conductive layer is exposed after removing the carrier such that
the step of forming the conductive bumps further comprises: forming
a metal layer on the conductive layer; and removing portions of the
metal layer and the conductive layer under the metal layer so as
for the remaining portions of the metal layer and the conductive
layer to form the conductive bumps.
[0019] In another embodiment, the carrier has a conductive layer
that allows the first circuit layer to be formed thereon, and the
conductive layer is exposed after removing the carrier such that
the step of forming the conductive bumps further comprises: forming
a resist layer on the conductive layer and forming a plurality of
openings in the resist layer corresponding in position to the first
conductive pads; forming a metal layer in the openings of the
resist layer; and removing the resist layer so as for the metal
layer to form the conductive bumps.
[0020] In a further embodiment, the step of forming the conductive
bumps further comprises: forming a metal layer on the first surface
of the dielectric layer and the surface of the first circuit layer;
and removing portions of the metal layer so as for the remaining
portions of the metal layer to form the conductive bumps.
[0021] In still another embodiment, the surface of the carrier has
a metal layer, and after the carrier is removed, portions of the
metal layer are removed so as for the remaining portions of the
metal layer to form the conductive bumps.
[0022] In the above-described substrate and method, the conductive
bumps can be less, equal to or greater in width than the first
conductive pads.
[0023] In the above-described substrate and method, the surface of
the first circuit layer can be flush with or lower than the first
surface of the dielectric layer.
[0024] In the above-described substrate and method, an insulating
layer can be formed on the first surface of the dielectric layer
and the surface of the first circuit layer and have a plurality of
openings for exposing the conductive bumps.
[0025] In the above-described substrate and method, a second
circuit layer can be formed on the second surface of the dielectric
layer. Further, a plurality of conductive vias can be formed in the
dielectric layer for electrically connecting the first circuit
layer and the second circuit layer. Furthermore, an insulating
layer can be formed on the second surface of the dielectric layer
and the second circuit layer and have a plurality of openings for
exposing portions of the second circuit layer.
[0026] According to the present invention, when an electronic
element is disposed on the first conductive pads through a
plurality of conductive elements, the conductive elements can come
into contact with both top and side surfaces of the conductive
bumps so as to increase the contact area between the conductive
elements and the first conductive pads, thereby strengthening the
bonding between the conductive elements and the first conductive
pads and preventing delamination of the conductive elements from
the first conductive pads.
[0027] Further, even if the surface of the first circuit layer is
lower than the first surface of the dielectric layer, the
conductive bumps protruding above the first surface of the
dielectric layer ensure sufficient wetting of the conductive
elements so as to prevent the conductive elements from being stuck
on the first surface of the dielectric layer as in the prior art.
Therefore, the conductive elements can be in effective contact with
the conductive bumps so as to be electrically connected to the
first conductive pads.
BRIEF DESCRIPTION OF DRAWINGS
[0028] FIGS. 1A to 1F are schematic cross-sectional views showing a
method for fabricating a packaging substrate according to the prior
art;
[0029] FIG. 1G is a schematic cross-sectional view showing a
subsequent process of the conventional packaging substrate;
[0030] FIGS. 2A to 2G' are schematic cross-sectional views showing
a method for fabricating a packaging substrate according to the
present invention, wherein FIGS. 2F' and 2F'' show other
embodiments of the FIG. 2F, and FIG. 2G' shows another embodiment
of FIG. 2G;
[0031] FIG. 2H is a schematic cross-sectional view showing a
subsequent process of the packaging substrate of the present
invention;
[0032] FIGS. 3A and 3B are schematic cross-sectional views showing
a method for forming the conductive bumps of FIG. 2F;
[0033] FIGS. 4A to 4C are schematic cross-sectional views showing
another method for forming the conductive bumps of FIG. 2F; and
[0034] FIGS. 5A and 5B are schematic cross-sectional views showing
a further method for forming the conductive bumps of FIG. 2E
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
[0035] The following illustrative embodiments are provided to
illustrate the disclosure of the present invention, these and other
advantages and effects can be apparent to those in the art after
reading this specification.
[0036] It should be noted that all the drawings are not intended to
limit the present invention. Various modifications and variations
can be made without departing from the spirit of the present
invention. Further, terms such as "upper", "lower", "first",
"second", "a" etc. are merely for illustrative purposes and should
not be construed to limit the scope of the present invention.
[0037] FIGS. 2A to 2G are schematic cross-sectional views showing a
method for fabricating a packaging substrate 2 according to the
present invention.
[0038] Referring to FIGS. 2A and 2B, a carrier 20 is provided and a
first circuit layer 21 is formed on upper and lower surfaces of the
carrier 20.
[0039] The carrier 20 can be an insulating plate, a ceramic plate,
a copper clad laminate or a glass plate. In the present embodiment,
a metal layer 200 is formed on the upper and lower surfaces of the
carrier 20 to serve as a conductive layer, i.e., a seed layer. If
the carrier 20 is a copper clad laminate, the copper foil of the
copper clad laminate can serve as the conductive layer.
[0040] Referring to FIG. 2B, a first circuit layer 21 is formed on
the conductive layer 200 by electroplating. The first circuit layer
21 has a plurality of first conductive pads 210.
[0041] Referring to FIG. 2C, a dielectric layer 22 is formed on the
carrier 20 and the first circuit layer 21. The dielectric layer 22
has a first surface 22a in contact with and attached to the carrier
20 and a second surface 22b opposite to the first surface 22a.
[0042] In the present embodiment, the dielectric layer 22 is made
of prepreg.
[0043] Referring to FIG. 2D, a second circuit layer 23 is formed on
the second surface 22b of the dielectric layer 22. The second
circuit layer 23 has a plurality of second conductive pads 230.
Further, a plurality of conductive vias 24 are formed in the
dielectric layer 22 for electrically connecting the first circuit
layer 21 and the second circuit layer 23.
[0044] Referring to FIG. 2E, the carrier 20 is removed to expose
the conductive layer 200.
[0045] Referring to FIG. 2F, a plurality of conductive bumps 27
made of such as copper are formed on the conductive layer 200
corresponding in position to the first conductive pads 210. The
conductive bumps 27 protrude to a height h of 5 um above the first
surface 22a of the dielectric layer 22. Then, portions of the
conductive layer 200 exposed from the conductive bumps 27 are
removed while maintaining portions 200' of the conductive layer 200
under the conductive bumps 27.
[0046] In the present embodiment, the width D of the conductive
bumps 27 is equal to the width R of the first conductive pads
210.
[0047] In another embodiment, referring to FIG. 2F', the width D'
of the conductive bumps 27' is greater than the width R of the
first conductive pads 210. In a further embodiment, referring to
FIG. 2F'', the width D'' of the conductive bumps 27' is less than
the width R of the first conductive pads 210.
[0048] Referring to FIG. 2G, a first insulating layer 25 is formed
on the first surface 22a of the dielectric layer 22 and the first
circuit layer 21 and a plurality of first openings 250 are formed
in the first insulating layer 25 so as to expose the conductive
bumps 27 and portions of the first surface 22a of the dielectric
layer 22 around peripheries of the conductive bumps 27. Further, a
second insulating layer 26 is formed on the second surface 22b of
the dielectric layer 22 and the second circuit layer 23 and a
plurality of second openings 260 are formed in the second
insulating layer 26 to expose the second conductive pads 230.
[0049] In another embodiment, referring to FIG. 2G', when the
conductive layer 200 is removed, the first conductive pads 210 are
also partially removed so as to be recessed into the first surface
22a of the dielectric layer 22.
[0050] Subsequently, referring to FIG. 2H, an electronic element 9
is disposed on the first conductive pads 210 through a plurality of
conductive elements 28 made of such as a solder material. Since the
conductive bumps 27 protrude above the first surface 22a of the
dielectric layer 22, the conductive elements 28 can come into
contact with both top surfaces 27a and side surfaces 27c of the
conductive bumps 27 so as to increase the contact area between the
conductive elements 28 and the first conductive pads 210, thereby
strengthening the bonding between the conductive elements 28 and
the first conductive pads 210 and preventing delamination of the
conductive elements 28 from the first conductive pads 210.
Therefore, the product reliability is improved.
[0051] Further, even if the surface of the first circuit layer 21
is lower than the first surface 22a of the dielectric layer 22, the
conductive bumps 27 protruding above the first surface 22a of the
dielectric layer 22 ensure sufficient wetting of the conductive
elements 28 so as to prevent the conductive elements 28 from being
stuck on the first surface 22a of the dielectric layer 22.
Therefore, the conductive elements 28 can be in effective contact
with the conductive bumps 27 so as to be electrically connected to
the first conductive pads 210.
[0052] The conductive bumps 27 can be formed through the following
methods.
[0053] FIGS. 3A and 3B are schematic cross-sectional views showing
a method for forming the conductive bumps 27 according to a first
embodiment.
[0054] Referring to FIG. 3A, a metal layer 40 is formed on the
conductive layer 200 by attaching or electroplating.
[0055] In the present embodiment, the conductive layer 200 is a
copper foil.
[0056] Referring to FIG. 3B, a patterning process is performed to
remove portions of the metal layer 40 and the conductive layer 200
under the metal layer 40. As such, the remaining portions 40' of
the metal layer 40 and the remaining portions 200' of the
conductive layer 200 form the conductive bumps 27.
[0057] FIGS. 4A to 4C are schematic cross-sectional views showing a
method for forming the conductive bumps 27 according to a second
embodiment.
[0058] Referring to FIG. 4A, a resist layer 52 is formed on the
conductive layer 200 and a plurality of third openings 520 are
formed in the resist layer 52 to expose portions of the conductive
layer 200 corresponding in position to the first conductive pads
210.
[0059] In the present embodiment, the conductive layer 200 is a
copper foil.
[0060] Referring to FIG. 4B, a metal layer 50 is formed on the
exposed portions of the conductive layer 200 in the third openings
520 of the resist layer 52 by electroplating.
[0061] Referring to FIG. 4C, the resist layer 52 and the portions
of the conductive layer 200 under the resist layer 52 are removed.
As such, the metal layer 50 and the portions 200' of the conductive
layer 200 under the metal layer 50 form the conductive bumps
27.
[0062] FIGS. 5A and 5B are schematic cross-sectional views showing
a method for forming the conductive bumps 27 according to a third
embodiment.
[0063] Referring to FIG. 5A, the conductive layer 200 is removed
and a metal layer 30 is formed on the first surface 22a of the
dielectric layer 22 and the first circuit layer 21.
[0064] In the present embodiment, a copper foil can be laminated on
the first surface 22a of the dielectric layer 22 and the first
circuit layer 21 to serve as the metal layer 30. Alternatively, the
metal layer 30 can be formed by electroplating.
[0065] In other embodiments, after the conductive layer 200 is
removed, the first circuit layer 21 has a surface slightly lower
than the first surface 22a of the dielectric layer 22 so as to be
recessed into the first surface 22a of the dielectric layer 22.
[0066] In another embodiment, no conductive layer 200 is formed on
the upper and lower surfaces of the carrier 20. Instead, referring
to FIG. 5A, the metal layer 30 is directly formed on the upper and
lower surfaces of the carrier 20. Therefore, after the carrier 20
is removed, the metal layer 30 is exposed.
[0067] Referring to FIG. 5B, a patterning process is performed to
remove portions of the metal layer 30. As such, the remaining
portions 30' of the metal layer 30 form the conductive bumps
27.
[0068] The present invention further provides a packaging substrate
2, which has: a dielectric layer 22 having opposite first and
second surfaces 22a, 22b; a first circuit layer 21 embedded in the
first surface 22a of the dielectric layer 22 and having a surface
exposed from the first surface 22a of the dielectric layer 22,
wherein the first circuit layer 21 has a plurality of first
conductive pads 210; and a plurality of conductive bumps 27, 27',
27'' formed on the first conductive pads 210 and protruding above
the first surface 22a of the dielectric layer 22.
[0069] The surface of the first circuit layer 21 can be flush with
the first surface 22a of the dielectric layer 22.
[0070] The conductive bumps 27, 27', 27'' can be less, equal to or
greater in width than the first conductive pads 210. The conductive
bumps 27, 27', 27'' can be made of copper.
[0071] The packaging substrate 2 can further have a first
insulating layer 25 formed on the first surface 22a of the
dielectric layer 22 and the surface of the first circuit layer 21
and having a plurality of openings 250 for exposing the conductive
bumps 27, 27', 27'' and portions of the first surface 22a around
peripheries of the conductive bumps 27, 27', 27''.
[0072] The packaging substrate 2 can further have a second circuit
layer 23 formed on the second surface 22b of the dielectric layer
22 and having a plurality of second conductive pads 230. Further, a
plurality of conductive vias 24 are formed in the dielectric layer
22 for electrically connecting the first circuit layer 21 and the
second circuit layer 23. Furthermore, the packaging substrate 2 can
have a second insulating layer 26 formed on the second surface 22b
of the dielectric layer 22 and the second circuit layer 23 and
having a plurality of second openings 260 for exposing the second
conductive pads 230.
[0073] According to the present invention, since the first
conductive pads have the conductive bumps formed thereon and
protruding above the first surface of the dielectric layer, when an
electronic element is disposed on the first conductive pads through
a plurality of conductive elements made of such as a solder
material, the conductive elements can come into contact with a
plurality of surfaces of the conductive bumps so as to increase the
contact area between the conductive elements and the first
conductive pads, thereby strengthening the bonding between the
conductive elements and the first conductive pads and preventing
delamination of the conductive elements from the first conductive
pads. Therefore, the product reliability is improved.
[0074] Further, even if the surface of the first circuit layer is
lower than the first surface of the dielectric layer, the
conductive bumps protruding above the first surface of the
dielectric layer ensure sufficient wetting of the conductive
elements so as to cause the conductive elements to be in effective
contact with the conductive bumps so as to be electrically
connected to the first conductive pads, thereby improving the
product reliability.
[0075] The above-described descriptions of the detailed embodiments
are only to illustrate the preferred implementation according to
the present invention, and it is not to limit the scope of the
present invention. Accordingly, all modifications and variations
completed by those with ordinary skill in the art should fall
within the scope of present invention defined by the appended
claims.
* * * * *