U.S. patent application number 14/604762 was filed with the patent office on 2015-05-21 for method of forming and structure of a non-volatile memory cell.
The applicant listed for this patent is eMemory Technology Inc.. Invention is credited to Cheng-Yen Shen, Wein-Town Sun.
Application Number | 20150140766 14/604762 |
Document ID | / |
Family ID | 51352452 |
Filed Date | 2015-05-21 |
United States Patent
Application |
20150140766 |
Kind Code |
A1 |
Sun; Wein-Town ; et
al. |
May 21, 2015 |
Method of forming and structure of a non-volatile memory cell
Abstract
A structure of a memory cell includes a substrate, a well, three
source/drain doped regions, two bottom dielectric layers, two
charge trapping layers, a blocking layer and two gates to form a
storage transistor and a select transistor of the memory cell. A
bottom dielectric layer and a charge trapping layer may be used to
provide the dielectric of the gate of the select transistor with
enough thickness but without any additional fabrication
process.
Inventors: |
Sun; Wein-Town; (Taoyuan
City, TW) ; Shen; Cheng-Yen; (Taoyuan City,
TW) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
eMemory Technology Inc. |
Hsin-Chu |
|
TW |
|
|
Family ID: |
51352452 |
Appl. No.: |
14/604762 |
Filed: |
January 26, 2015 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
14325383 |
Jul 8, 2014 |
|
|
|
14604762 |
|
|
|
|
61883205 |
Sep 27, 2013 |
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Current U.S.
Class: |
438/287 |
Current CPC
Class: |
G11C 16/24 20130101;
G11C 16/3418 20130101; H01L 29/512 20130101; G11C 16/0441 20130101;
H01L 29/66545 20130101; H01L 29/42328 20130101; H01L 27/11558
20130101; H01L 27/11524 20130101; H01L 29/45 20130101; H01L
29/66833 20130101; H01L 29/788 20130101; H01L 29/7881 20130101;
H01L 29/0649 20130101; H01L 29/792 20130101; G11C 2216/10 20130101;
G11C 16/10 20130101; G11C 16/0416 20130101; G11C 16/14 20130101;
G11C 16/26 20130101; H01L 29/7882 20130101; G11C 16/0433 20130101;
H01L 29/42344 20130101; H01L 27/1157 20130101 |
Class at
Publication: |
438/287 |
International
Class: |
H01L 29/66 20060101
H01L029/66; H01L 27/115 20060101 H01L027/115 |
Claims
1. A method of forming a non-volatile memory cell comprising:
defining an active region which comprises a select transistor
region and a storage transistor region; forming a well on a
substrate; forming a stacked layer comprising a bottom dielectric
layer, a charge trapping layer and a top dielectric layer; etching
the top dielectric layer in the select transistor region; forming a
select gate on the select transistor region and a memory gate on
the storage transistor region; and forming a plurality of
source/drain doped regions.
2. The method of claim 1, further comprising: forming a plurality
of lightly doped region regions.
3. The method of claim 1, wherein the step of defining the active
region comprises a step of forming isolations on the substrate.
4. The method of claim 1, wherein the step of forming the well
comprises a step of implanting impurities on the substrate.
5. The method of claim 1, wherein step of forming the plurality of
lightly doped region regions comprises a step of implanting ions on
the well to form four lightly doped regions on the well and each
formed between a corresponding bottom dielectric layer and a
corresponding source/drain doped region.
6. The method of claim 1, further comprising: implanting impurities
on the substrate to form a deep well between the substrate and the
well.
7. The method of claim 6, wherein the deep well is a deep
N-well.
8. The method of claim 1, further comprising: implanting impurities
on the substrate to form a barrier layer between the substrate and
the well.
9. The method of claim 8, wherein the barrier layer is an N-barrier
layer.
10. The method of claim 1, wherein a length of the select gate is
greater than or equal to a length of the memory gate.
11. The method of claim 1, wherein the first charge trapping layer
and the second charge trapping layer are composed of silicon
nitride.
12. The method of claim 1, wherein the first charge trapping layer
and the second charge trapping layer are composed of silicon
oxynitride.
13. The method of claim 1, wherein the substrate is a P-substrate,
the well is an N-well, and the source/drain doped regions are P+
doped regions.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This non-provisional application is a division of U.S.
patent application Ser. No. 14/325,383, filed Jul. 8, 2014, which
claims priority to US provisional application U.S. 61/883,205 filed
on Sep. 27, 2013, both of which are included herein by reference in
their entirety.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates to a non-volatile memory cell,
and more specifically, to a non-volatile memory cell having two
transistors and a method of fabricating the non-volatile memory
cell.
[0004] 2. Description of the Prior Art
[0005] Non-volatile memory can store data in the absence of a power
supply; therefore it is preferred to be used by various portable
electronic products such as personal digital assistants (PDAs),
mobile phones, and memory cards. In order to respond to the
requirements of the market, non-volatile memory technology must
have compatibility with CMOS processing, low power consumption,
high writing efficiency, low cost, and high density. However, as
non-volatile memory becomes smaller in size, the gate oxide layer
becomes accordingly thinner making stored data dissipate easily and
causes a problem in the data storing ability of non-volatile
memory.
[0006] FIG. 1 illustrates a conventional memory cell 10. The memory
cell 10 includes an N-channel metal oxide semiconductor (NMOS)
transistor 28 and a P-channel metal oxide semiconductor (PMOS)
transistor 30 separated by an insulating field oxide layer (FOX)
24. The NMOS transistor 28 is formed on a P-type substrate 12 and
includes a first floating gate 32, an N+ source doped region 14,
and an N+ drain doped region 16. The PMOS transistor 30 is formed
on an N-type substrate 18 and includes a second floating gate 34, a
P+ source doped region 20, and a P+ drain doped region 22. The PMOS
transistor 30 is implanted with a source/drain doped N-type channel
stop region 38 under the second floating gate 34, adjacent to the
P+ source doped region 20. The first floating gate 32 and the
second floating gate 34 are connected with a floating gate metal
line 36 so that both are kept at the same level. When writing data
into the memory cell 10, the first floating gate 32 generates a
corresponding level according to a control gate voltage. At this
time, the second floating gate 34 has the same level as the first
floating gate 32 because of the connection by the floating gate
metal line 36. Then, the electrons in a depletion region between
the P+ source doped region 20 and the N-type channel stop region 38
are accelerated and injected into the second floating gate 34.
[0007] However, the conventional memory cell 10 has disadvantages.
First, the conventional memory cell 10 comprises the PMOS
transistor 30 and the NMOS transistor 28 which occupy a large
amount of chip area since there is a minimum spacing rule between
different types of transistors set by the fabrication technology
used. Second, the conventional memory cell 10 requires the floating
gate metal line 36 for connecting the first floating gate 32 and
the second floating gate 34. Third, the field oxide layer 24 is
required to separate the PMOS transistor 30 from the NMOS
transistor 28. Therefore, the conventional memory cell 10 occupies
considerable chip area and is structurally complicated. All of
which increase the cost and difficulties in the manufacturing
process.
SUMMARY OF THE INVENTION
[0008] A non-volatile memory cell comprises a well formed on a
substrate, a plurality of source/drain doped regions formed on the
well, a first bottom dielectric layer formed between a first
source/drain doped region and a second source/drain doped region of
the plurality of source/drain doped regions on the well, a second
bottom dielectric layer formed between the second source/drain
doped region and a third source/drain doped region of the plurality
of source/drain doped regions on the well, a first charge trapping
layer formed on the first bottom dielectric layer, a second charge
trapping layer formed on the second bottom dielectric layer, a
blocking layer formed on the first charge trapping layer, a memory
gate formed on the blocking layer, and a select gate formed on the
second charge trapping layer.
[0009] A method of forming a non-volatile memory cell comprises
defining an active region which comprises a select transistor
region and a storage transistor region, forming a well on a
substrate, forming a stacked layer comprising a bottom dielectric
layer, a charge trapping layer and a top dielectric layer, etching
the top dielectric layer in the select transistor region, forming a
select gate on the select transistor region and a memory gate on
the storage transistor region, and forming a plurality of
source/drain doped regions.
[0010] These and other objectives of the present invention will no
doubt become obvious to those of ordinary skill in the art after
reading the following detailed description of the preferred
embodiment that is illustrated in the various figures and
drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0011] FIG. 1 illustrates a conventional memory cell.
[0012] FIG. 2 illustrates a non-volatile memory cell according to
an embodiment of the present invention.
[0013] FIG. 3 illustrates a non-volatile memory cell according to
another embodiment of the present invention.
[0014] FIG. 4 illustrates a flowchart of a method of fabrication of
the non-volatile memory cell in FIG. 2.
[0015] FIG. 5 illustrates a substrate after a well is formed
according to an embodiment of the present invention.
[0016] FIG. 6 illustrates a bottom dielectric layer, a charge
trapping layer and a top dielectric layer formed over the surface
of the substrate.
[0017] FIG. 7 illustrates the etching of the bottom dielectric
layer, the charge trapping layer and the top dielectric layer in
step 404 in FIG. 4.
[0018] FIG. 8 illustrates the top dielectric layer partially
etched.
[0019] FIG. 9 illustrates the layer of gate compound formed over
the surface of the substrate.
[0020] FIG. 10 illustrates the non-volatile memory cell after
layers of compounds on the substrate are etched.
[0021] FIG. 11 illustrates spacers and at least four lightly doped
regions formed on the substrate.
DETAILED DESCRIPTION
[0022] FIG. 2 illustrates a non-volatile memory cell 200 according
to an embodiment of the present invention. The non-volatile memory
cell 200 comprises a substrate 210, isolations STI, a well 220,
three source/drain doped regions 231, 232, and 233, two bottom
dielectric layers 251 and 252, two charge trapping layers 261 and
262, a blocking layer 271, a memory gate 281 and a select gate 282.
The substrate 210 may be a p-substrate. In another embodiment, the
substrate 210 may also be referred to a wafer. The isolations STI
may be used to define an active region on the substrate 210. The
well 220 may be an N-well and formed on the substrate 210 by
implanting impurities. Each of the three source/drain doped regions
231, 232, and 233 may be a P+ doped region and formed on the well
220. Each of the two bottom dielectric layers 251 and 252 may be
composed of silicon dioxide and formed on the well 220. The first
bottom dielectric layer 251 may be formed between a first
source/drain doped region 231 and a second source/drain doped
region 232. The second bottom dielectric layer 252 may be formed
between the second source/drain doped region 232 and a third
source/drain doped region 233. Each of the two charge trapping
layers 261 and 262 may be composed of silicon nitride or silicon
oxynitride . The first charge trapping layer 261 maybe formed on
the first bottom dielectric layer 251. The second charge trapping
layer 262 may be formed on the second bottom dielectric layer 252.
The blocking layer 271 may be composed of silicon dioxide and
formed on the first charge trapping layer 261. Each of the two
gates 281 and 282 maybe a poly silicon gate. The memory gate 281
may be formed on the blocking layer 271. The select gate 282 may be
formed on the second charge trapping layer 262.
[0023] In addition, the non-volatile memory cell 200 may further
comprise of at least four lightly doped regions 241, 242, 243, and
244. Each of the at least four lightly doped regions 241, 242, 243,
and 244 maybe a P-doped region and formed on the well 220. The
first lightly doped region 241 may be in contact with the first
source/drain doped region 231 and formed between the first
source/drain doped region 231 and the first bottom dielectric layer
251. The second lightly doped region 242 maybe in contact with the
second source/drain doped region 232 and formed between the second
source/drain doped region 232 and the first bottom dielectric layer
251. The third lightly doped region 243 maybe in contact with the
second source/drain doped region 232 and formed between the second
source/drain doped region 232 and the second bottom dielectric
layer 252. The fourth lightly doped region 244 may be in contact
with the third source/drain doped region 233 and formed between the
third source/drain doped region 233 and the second bottom
dielectric layer 252.
[0024] To protect the at least four lightly doped regions 241, 242,
243, and 244 from being overlapped by forming of three source/drain
doped regions 231, 232, and 233, at least four spacers 291, 292,
293, and 294 are formed. Each spacer shall be formed above a
lightly doped region.
[0025] The first source/drain doped region 231, the second
source/drain doped region 232, the first bottom dielectric layer
251, the first charge trapping layer 261, the blocking layer 271
and the memory gate 281 may form a storage transistor 201 of the
non-volatile memory cell 200. The second source/drain doped region
232, the third source/drain doped region 233, the second bottom
dielectric layer 252, the second charge trapping layer 262, and the
select gate 282 may form a select transistor 202 of the
non-volatile memory cell 200.
[0026] The storage transistor 201 may be formed in a storage
transistor region 101 of the substrate 210 and the select
transistor 202 may be formed in a select transistor region 102 of
the substrate 210. The channel length of the storage transistor 201
may be greater than or equal to the base length of the fabrication
technology. The channel length of the select transistor 202 may be
greater than or equal to the channel length of the storage
transistor 201. A select line and a bit line may be used to provide
voltages needed during operations of the non-volatile memory cell
200. The second source/drain doped region 232 is a floating region
and is used to electrically connect the storage transistor 201 and
the select transistor 202.
[0027] To perform write operation on the non-volatile memory cell
200, electrons are injected into the first charge trapping layer
261 through hot-electron injection mechanism induced by channel
-hot-hole . Before writing data onto the non-volatile memory cell
200, the select transistor 202 is turned on to have a conducting
channel between the third source/drain doped region 233 and the
second source/drain doped region 232. The conducting channel
between the third source/drain doped region 233 and the second
source/drain doped region 232 would allow the third source/drain
doped region 233 and the second source/drain doped region 232 to
have the same voltage level. Holes in the channel between the
second source/drain doped region 232 and the first source/drain
doped region 231 are accelerated to obtain high energy. As a result
of high energy impacting the well 220, electron hole pairs are
generated. The electrons generated are attracted by a voltage
applied to the memory gate 281 and the electrons are then injected
into the first charge trapping layer 261 of the storage transistor
201.
[0028] To perform an erase operation on the non-volatile memory
cell 200, electrons injected into the first charge trapping layer
261 may be ejected through Fowler Nordheim tunneling. Fowler
Nordheim tunneling may also be performed by the memory cell when
performing read operation. And controlling the voltage on the
select line and the bit line allows the program inhibit operation
to be performed.
[0029] In another embodiment of the present invention, a memory
cell may further comprise a deep well. FIG. 3 illustrates a
non-volatile memory cell 300 according to another embodiment of the
present invention. The non-volatile memory cell 300 comprises the
substrate 210, a deep well 310, the well 220, the three
source/drain doped regions 231, 232, and 233, the two bottom
dielectric layers 251 and 252, the two charge trapping layers 261
and 262, the blocking layer 271 and the memory gate 281 and the
select gate 282. The substrate 210 may be a P-substrate. In some
cases, the substrate 210 may also be referred to a wafer. The deep
well 310 may be a deep N-well or an N-type barrier layer. The well
220 may be an N-well and formed on the substrate 210 by implanting
impurities. Each of the three source/drain doped regions 231, 232,
and 233 maybe a P+ doped region and formed on the well 220. Each of
the two bottom dielectric layers 251 and 252 maybe composed of
silicon dioxide and formed on the well 220. The first bottom
dielectric layer 251 may be formed between the first source/drain
doped region 231 and the second source/drain doped region 232. The
second bottom dielectric layer 252 may be formed between the second
source/drain doped region 232 and the third source/drain doped
region 233. Each of the two charge trapping layers 261 and 262
maybe composed of silicon nitride or silicon oxynitride. The first
charge trapping layer 261 maybe formed on the first bottom
dielectric layer 251. The second charge trapping layer 262 may be
formed on the second bottom dielectric layer 252. The blocking
layer 271 may be composed of silicon dioxide and formed on the
first charge trapping layer 261. Each of the two gates 281 and 282
may be a poly silicon gate. The memory gate 281 may be formed on
the blocking layer 271. The select gate 282 may be formed on the
second charge trapping layer 262.
[0030] In addition, the non-volatile memory cell 300 may further
comprise of the at least four lightly doped regions 241, 242, 243,
and 244. Each of the at least four lightly doped regions 241, 242,
243, and 244 may be a P-doped region and formed on the well 220.
The first lightly doped region 241 may be in contact with the first
source/drain doped region 231 and formed between the first
source/drain doped region 231 and the first bottom dielectric layer
251. The second lightly doped region 242 may be in contact with the
second source/drain doped region 232 and formed between the second
source/drain doped region 232 and the first bottom dielectric layer
251. The third lightly doped region 243 may be in contact with the
second source/drain doped region 232 and formed between the second
source/drain doped region 232 and the second bottom dielectric
layer 252. The fourth lightly doped region 244 may be in contact
with the third source/drain doped region 233 and formed between the
third source/drain doped region 233 and the second bottom
dielectric layer 252.
[0031] The storage transistor 201 and the select transistor 202 of
the non-volatile memory cell 300 comprise of similar components as
that in the non-volatile memory cell 200. The difference of the
non-volatile memory cell 300 and the non-volatile memory cell 200
is that the non-volatile memory cell 300 has a deep well 310 formed
on the substrate 210 while the other does not. The function and
operation of the two non-volatile memory cells 200 and 300 are the
same. Therefore, the operation of the non-volatile memory cell 300
is not discussed further for brevity.
[0032] FIG. 4 illustrates a flowchart of a method of fabrication
the non-volatile memory cell 200 in FIG. 2. The method of
fabrication may include but is not limited to the following
steps:
[0033] Step 401: Form isolations STI on the substrate 210;
[0034] Step 402: Form the well 220 on the substrate 210;
[0035] Step 403: Grow/deposit a bottom dielectric layer 250, a
charge trapping layer 260, and a top dielectric layer 270 on the
substrate 210;
[0036] Step 404: Etch the bottom dielectric layer 250, the charge
trapping layer 260, and the top dielectric layer 270 from areas out
of the areas of the non-volatile memory cell 200;
[0037] Step 405: Etch the top dielectric layer 270 formed in the
select transistor region 102;
[0038] Step 406: Deposit a layer of gate compound 280 on the
substrate 210;
[0039] Step 407: Form the memory gate 281 and the select gate
282;
[0040] Step 408: Etch the bottom dielectric layer 250, the charge
trapping layer 260, and the top dielectric layer 270 from areas out
of the areas of the memory gate 281 and the select gate 282;
[0041] Step 409: Form the at least four lightly doped regions 241,
242, 243, and 244; and
[0042] Step 410: Form source/drain doped regions 231, 232, and 233
of the non-volatile memory cell 200.
[0043] In step 401, isolations STI are formed on the substrate 210
to define the active region where the non-volatile memory cell 200
is to be formed. FIG. 5 illustrates the substrate 210 after the
well 220 is formed according to an embodiment of the present
invention. In step 402, impurities are implanted onto the substrate
210 to form the well 220. To form an N-well, the impurities may be
N-type impurities.
[0044] FIG. 6 illustrates the bottom dielectric layer 250, the
charge trapping layer 260 and the top dielectric layer 270 formed
on the surface of the substrate 210. In step 403, the bottom
dielectric layer 250, the charge trapping layer 260 and the top
dielectric layer 270 may be grown/deposited on the entire surface
of the substrate 210. The bottom dielectric layer 250 and the top
dielectric layer 270 may be composed of silicon oxide. The charge
trapping layer 260 may be composed of silicon nitride or silicon
oxynitride.
[0045] FIG. 7 illustrates the etching of the bottom dielectric
layer 250, the charge trapping layer 260 and the top dielectric
layer 270 instep 404. Instep 404, the bottom dielectric layer 250,
the charge trapping layer 260 and the top dielectric layer 270 may
be etched from areas of the substrate 210 other than areas of the
substrate 210 where the non-volatile memory cells 200 are to be
formed. The areas of the substrate 210 other than areas of the
substrate 210 where the non-volatile memory cells 200 are to be
formed may include areas of the substrate 210 where input/output
(I/O) devices and logic devices are to be formed. After step 404, a
gate dielectric layer of input/output (I/O) devices may be formed
on the substrate 210 and etched from areas of the substrate 210
outside the input/output (I/O) device regions.
[0046] FIG. 8 illustrates the top dielectric layer 270 partially
etched. In step 405, selected areas of the top dielectric layer 270
formed in the select transistor region 102 are removed through
etching. That is to say, the storage transistor region 101 and the
select transistor region 102 are defined in this step. And after
step 405, the gate dielectric layer of logic devices may be formed
on the substrate 210.
[0047] Note that the etching of the gate dielectric layer of
input/output (I/O) devices maybe performed separately or at the
same time as the etching in step 405. The gate dielectric layer of
input/output (I/O) devices and the gate dielectric layer of logic
devices may be formed separately for reasons that the thickness of
the gate dielectric layer of input/output (I/O) devices may be
thicker than the gate dielectric layer of logic devices.
[0048] FIG. 9 illustrates the layer of gate compound 280 formed on
the surface of the substrate 210. In Step 406, the layer of gate
compound 280 is deposited on the substrate 210. The layer of gate
compound 280 may be a polysilicon layer.
[0049] FIG. 10 illustrates the non-volatile memory cell 200 after
layers of compounds on the substrate 210 are etched. In step 407,
the select gate 282 on the select transistor region 102 and the
memory gate 281 on the storage transistor region 101 are formed. In
other words, a mask which defines the positions of the select gate
282 and the memory gate 281 is adopted, then an etching process is
proceeded to etch the areas of the layer of gate compound 280
outside the area of the select gate 282 and the memory gate 281. In
this step, the areas on the substrate 210 where the gates of the
input/output (I/O) devices and the gates of logic devices are
formed may also be defined by the mask. And areas of the layer of
gate compound 280 where the gates of the input/output (I/O) devices
and the gates of logic devices are defined may also remain on the
substrate 210 after the etching process.
[0050] In step 408, the reverse Oxide-Nitride-Oxide (ONO) etching
process may be performed. After the etching process of the layer of
gate compound 280 is finished, a first stacked layer which
comprises the blocking layer 271 and the first charge trapping
layer 261 and the first bottom dielectric layer 251 is formed.
Moreover, a second stacked layer which comprises the second charge
trapping layer 262 and the second bottom dielectric layer 252 is
also formed. The first stacked layer and the second stacked layer
may be defined by etching areas of the bottom dielectric layer 250,
the charge trapping layer 260, and the top dielectric layer 270
outside the area of the select gate 282 and the area of the memory
gate 281.
[0051] Two masks maybe adopted for the gate compound etching
process and the reverse ONO etching process. Moreover, to perform
the etching process, a layer of photoresist may be deposited over
the entire surface of a top layer of layers of compounds to be
etched. For example, to form a poly silicon gate, a layer of oxide
and a layer of poly silicon compound are formed on the entire
surface of the substrate. The top layer for instance may be the
layer of poly silicon gate compound. The layer of photoresist is
formed above the layer of poly silicon gate compound to be etched.
The photoresist may be developed using a mask that specifies the
selected areas of the layer of poly silicon gate compound to be
etched. The photoresist is etched, removing photoresist above the
selected areas of the layer of poly silicon gate compound to be
etched. The process is then followed by the removal of parts of the
layer of oxide and the layer of poly silicon compound from the
selected areas, leaving remaining parts of the layer of oxide and
the layer of poly silicon compound protected by the remaining
photoresist to form the gate components of the non-volatile memory
cell 200 intact. The photoresist acts as a protection layer to the
layers of compounds that need not be etched during the etching
process. The remaining photoresist may be removed after an etching
process. The etching process maybe used for forming components that
are above the surface of the substrate 210.
[0052] The non-volatile memory cell 200 may further comprise of the
at least four lightly doped regions 241, 242, 243, and 244. In step
409, the at least four lightly doped regions 241, 242, 243, and 244
may be formed by implanting ions to the selected areas of the well
220. The at least four lightly doped regions 241, 242, 243, and 244
maybe formed before forming the source/drain doped regions 231,
232, and 233.
[0053] After step 409, the lightly doped regions of the
input/output (I/O) devices and the logic devices maybe formed by
implanting ions to the selected areas of the substrate 210. The
lightly doped regions of the input/output (I/O) devices and the
logic devices are formed separate from the lightly doped regions of
the non-volatile memory cells 200 since the lightly doped regions
of the input/output (I/O) devices and the logic devices and the
lightly doped regions of the non-volatile memory cells 200 may
require different concentrations of the implanted ions that are
defined according to the specific need of the devices.
[0054] A protection layer, such as the spacers 291, 292, 293, and
294, may be placed above the at least four lightly doped regions
241, 242, 243, and 244 to protect the at least four lightly doped
regions 241, 242, 243, and 244 from being overlapped by other
implanted components such as the three source/drain doped regions
231, 232, and 233. The present invention is not limited to the use
of protection layers to prevent lightly doped regions from being
overlapped by source/drain doped region.
[0055] FIG. 11 illustrates the spacers 291, 292, 293, and 294 and
the at least four lightly doped regions 241, 242, 243, and 244
formed on the substrate in FIG. 5. The surface area occupied by the
spacers 291, 292, 293, and 294 on the substrate 210 may be the same
as the surface area occupied by the at least four lightly doped
regions 241, 242, 243, and 244 on the substrate 210.
[0056] In step 410, selected areas of the well 220 are implanted
with ions to form the three source/drain doped regions 231, 232,
and 233. The structure of the non-volatile memory cell 200 is
illustrated in FIG. 2. The source/drain doped regions of the
input/output (I/O) devices and the logic devices on the substrate
210 may also be formed on this step.
[0057] Note that the non-volatile memory cell 300 in FIG. 3 may be
formed by implanting impurities into the substrate to form the deep
well 310. The deep well 310 may be formed before forming the well
220.
[0058] The present invention discloses a non-volatile memory cell
comprising of two transistors, a storage transistor and a select
transistor, coupled in series. The charge trapping layer of the
storage transistor may store electrons according to the data stored
on the non-volatile memory cell. The select transistor may be used
to select the non-volatile memory cell to be used during an
operation. The use of lightly doped regions reduces the short
channel effect on the non-volatile memory cell. A second charge
trapping layer and a second bottom dielectric layer may serve as a
dielectric of the gate of the select transistor. As compared to
prior art, the method of fabrication of the present invention is
more efficient since there is no need for additional etching step
to reduce the thickness of the dielectric, which is the same
dielectric as that of IO devices, of the gate of the select
transistor. The non-volatile memory cell of the present invention
may perform write operation, erase operation, read operation, and
program inhibit operation. In some embodiments of the present
invention, a deep well may be added to prevent damage to the
non-volatile memory cell when operating under high supply
voltage.
[0059] Those skilled in the art will readily observe that numerous
modifications and alterations of the device and method may be made
while retaining the teachings of the invention. Accordingly, the
above disclosure should be construed as limited only by the metes
and bounds of the appended claims.
* * * * *