U.S. patent application number 14/583813 was filed with the patent office on 2015-05-14 for method for forming a finfet structure.
The applicant listed for this patent is UNITED MICROELECTRONICS CORP.. Invention is credited to Jei-Ming Chen, Kuan-Hsien Li, Chin-Fu Lin, Chih-Chien Liu, Hung-Lin Shih.
Application Number | 20150132966 14/583813 |
Document ID | / |
Family ID | 52443587 |
Filed Date | 2015-05-14 |
United States Patent
Application |
20150132966 |
Kind Code |
A1 |
Shih; Hung-Lin ; et
al. |
May 14, 2015 |
METHOD FOR FORMING A FINFET STRUCTURE
Abstract
A method for forming a FinFET structure includes providing a
substrate, a first region and a second region being defined on the
substrate, a first fin structure and a second fin structure being
disposed on the substrate within the first region and the second
region respectively. A first oxide layer cover the first fin
structure and the second fin structure. Next a first protective
layer and a second protective layer are entirely formed on the
substrate and the first oxide layer in sequence, the second
protective layer within the first region is removed, and the first
protective layer within the first region is then removed.
Afterwards, the first oxide layer covering the first fin structure
and the second protective layer within the second region are
removed simultaneously, and a second oxide layer is formed to cover
the first fin structure.
Inventors: |
Shih; Hung-Lin; (Hsinchu
City, TW) ; Chen; Jei-Ming; (Tainan City, TW)
; Liu; Chih-Chien; (Taipei City, TW) ; Lin;
Chin-Fu; (Tainan City, TW) ; Li; Kuan-Hsien;
(Tainan City, TW) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
UNITED MICROELECTRONICS CORP. |
Hsin-Chu City |
|
TW |
|
|
Family ID: |
52443587 |
Appl. No.: |
14/583813 |
Filed: |
December 29, 2014 |
Related U.S. Patent Documents
|
|
|
|
|
|
Application
Number |
Filing Date |
Patent Number |
|
|
14079648 |
Nov 14, 2013 |
8951884 |
|
|
14583813 |
|
|
|
|
Current U.S.
Class: |
438/703 |
Current CPC
Class: |
H01L 21/823431 20130101;
H01L 21/823462 20130101; H01L 21/30604 20130101; H01L 29/401
20130101 |
Class at
Publication: |
438/703 |
International
Class: |
H01L 21/8234 20060101
H01L021/8234; H01L 29/40 20060101 H01L029/40 |
Claims
1. A method for forming a FinFET structure, at least comprising the
following steps: providing a substrate, a first region and a second
region being defined on the substrate, a first fin structure and a
second fin structure being disposed on the substrate within the
first region and the second region respectively, a first oxide
layer covering the first fin structure and the second fin
structure; forming a first protective layer and a second protective
layer entirely on the substrate and the first oxide layer in
sequence; removing the second protective layer within the first
region; removing the first protective layer within the first
region; removing the first oxide layer covering the first fin
structure and the second protective layer within the second region;
removing the first protective layer within the second region after
the second protective layer within the second region is removed;
and forming a second oxide layer covering the first fin structure,
wherein the second oxide layer is formed before the first
protective layer within the second region is removed.
2. The method of claim 1, wherein the first oxide layer is thicker
than the second oxide layer.
3. The method of claim 1, wherein the first oxide layer covering
the first fin structure and the second protective layer within the
second region are removed simultaneously.
4. The method of claim 1, wherein the first protective layer
comprises a silicon nitride layer.
5. The method of claim 1, wherein the second protective layer
comprises a silicon oxide layer.
6. The method of claim 1, further comprising forming an oxide
region disposed in the substrate, surrounding the first fin
structure and the second fin structure.
7. The method of claim 1, wherein the surface of the first fin
structure is exposed after the first oxide layer is removed from
the first fin structure.
8. The method of claim 1, wherein the method for removing the first
oxide layer covering the first fin structure and the second
protective layer within the second region comprises a dry-etching
process and a wet-etching process.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application is a divisional application of U.S. patent
application Ser. No. 14/079,648 filed Nov. 14, 2013, which is
herein incorporated by reference in its entirety.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates generally to fin-type field
effect transistors (FinFET) and more particularly to the method for
forming an improved FinFET structure that includes multiple gate
dielectric thicknesses.
[0004] 2. Description of the Prior Art
[0005] Semiconductor structure includes both passive semiconductor
devices such as resistors, as well as active devices such as
transistors and diodes. Field effect transistor devices are common
transistor devices within semiconductor structures.
[0006] Field effect transistor structure and device dimensions have
been scaled effectively to increasingly smaller dimensions over the
period of several decades. Various field effect transistor
structures having desirable properties are known in the
semiconductor fabrication art. One recent advance in transistor
technology is the introduction of fin type field effect transistors
that are known as FinFET.
[0007] In the conventional process, the method for forming
individual FinFETs on one substrate comprises: first, a substrate
having at least two fin structure is provided, and a first oxide
layer is then formed on these two fin structures, next, parts of
the first oxide layer, especially the portion that covers on one of
the fin structure is then removed, afterwards, a second oxide layer
is then formed on the exposed fin structure. However, since there
is no other layer that is formed during the process, the fin
structure or the isolating region surrounding each fin structure is
easily damaged by the etching processes, influencing the yield and
the performance of the FinFET.
SUMMARY OF THE INVENTION
[0008] The present invention provides a method for forming a FinFET
structure, at least comprising the following steps: first, a
substrate is provided, a first region and a second region are
defined on the substrate, a first fin structure and a second fin
structure are disposed on the substrate, within the first region
and the second region respectively, a first oxide layer covering
the first fin structure and the second fin structure, next a first
protective layer and a second protective layer are entirely formed
on the substrate and the first oxide layer in sequence, the second
protective layer within the first region is removed, the first
protective layer within the first region is then removed,
afterwards, the first oxide layer covering the first fin structure
and the second protective layer within the second region are
removed simultaneously, and a second oxide layer is formed to cover
the first fin structure.
[0009] The features of the present invention further comprise a
first protective layer and a second protective layer, which are
made of different materials, for example, in the embodiment
mentioned above. The first protective layer comprises silicon
nitride, and the second protective layer comprises silicon oxide,
and these two dielectric layers protect the oxide region disposed
in the substrate and surrounding the fin structure from the damages
occurring during the etching processes. Besides, since the silicon
nitride first protective layer has high selectivity with the first
oxide layer disposed on the fin structure and the oxide region, so
during the process for removing the silicon nitride first
protective layer, the first oxide layer and the oxide region will
not be ruined by the etching processes, thereby enhancing the yield
and the performance of the FinFET.
[0010] These and other objectives of the present invention will no
doubt become obvious to those of ordinary skill in the art after
reading the following detailed description of the preferred
embodiment that is illustrated in the various figures and
drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0011] FIGS. 1-9 are schematic diagrams showing the manufacturing
process for forming a FinFET structure according to one preferred
embodiment of the present invention.
DETAILED DESCRIPTION
[0012] To provide a better understanding of the present invention
to users skilled in the technology of the present invention,
preferred embodiments are detailed as follows. The preferred
embodiments of the present invention are illustrated in the
accompanying drawings with numbered elements to clarify the
contents and effects to be achieved.
[0013] Please note that the figures are only for illustration and
the figures may not be to scale. The scale may be further modified
according to different design considerations. When referring to the
words "up" or "down" that describe the relationship between
components in the text, it is well known in the art and should be
clearly understood that these words refer to relative positions
that can be inverted to obtain a similar structure, and these
structures should therefore not be precluded from the scope of the
claims in the present invention.
[0014] FIGS. 1-9 are schematic diagrams showing the manufacturing
process for forming a FinFET structure according to one preferred
embodiment of the present invention. As shown in FIG. 1, first, a
substrate 10 is provided, such as a silicon substrate. There are at
least two fin structures 12 on the substrate 10, and an oxide
region 14, disposed on the substrate 10 and surrounding the fin
structure 12. Usually, the oxide region such as the shallow trench
isolation (STI), is used to isolate different components on the
substrate 10. A first oxide layer 16 is disposed on the fin
structures 12, but does not cover the oxide region 14. In other
words, the oxide region 14 is exposed. In addition, there are two
regions: a first region A and a second region B which are defined
on the substrate, the region A and region B comprising at least one
fin structure 12 therein. It is worth noting that in the following
process, devices with different oxide layer thicknesses will be
formed in the region A and in the region B respectively, such as
the low voltage (LV) devices, the memory, the core devices,
electrostatic-sensitive device (ESD), IO devices or high voltage
(HV) devices, and these devices have different oxide layer
thicknesses.
[0015] Please refer to FIGS. 2-3, a first protective layer 18 and a
second protective layer 20 are then formed in sequence, covering
the first oxide layer 16 and the oxide region 14. In this
embodiment, the first protective layer 18 comprises silicon
nitride, and the second protective layer 20 comprises silicon
oxide. The first protective layer 18 and the second protective
layer 20 are preferably formed through an atomic layer deposition
(ALD) process, but not limited thereto.
[0016] Next, please refer to FIGS. 4-5. As shown in FIG. 4, a
patterned photoresist layer 22 is formed on the second protective
layer 20 within the second region B. As shown in FIG. 5, an etching
process (not shown) is then performed, to remove parts of the
second protective layer 20 which are not covered by the photoresist
layer 22. In other words, only the second protective layer 20
within the first region A is removed. Afterwards, the patterned
photoresist layer 22 is then removed. In this embodiment, the
etching process for removing the second protective layer 20
comprises a dilute hydrofluoric acid (DHF) containing cleaning
process, a sulfuric acid-hydrogen peroxide mixture (SPM) containing
cleaning process or a standard clean 1 (SC1) process, but not
limited thereto. It is worth noting that, in this step, the first
protective layer 18 still remains on the oxide region 14 and on the
first oxide layer 16, helping protect the first oxide layer 16 and
the oxide region 14 from damages occurring during the etching
process.
[0017] Please refer to FIG. 6. Another etching process is then
performed to remove the first protective layer 18 within the first
region A. In this step, the etching process uses the solvent such
as phosphate (H3PO4) which has high selectivity to the silicon
nitride and the silicon oxide. In other words, only the first
protective layer 18 mainly made of silicon nitride can easily be
removed by the etching process, but the second protective layer 20
and the oxide region 14 mainly made of silicon oxide are hardly
removed by the etching process, so the oxide region 14 disposed
under the first protective layer 18 is not easily ruined by the
etching process.
[0018] Please refer to FIG. 7. An etching process (not shown) is
performed, to remove the first oxide layer 16 disposed on the fin
structure 12 within the region A, and the second protective layer
20 within the second region B simultaneously, so as to completely
remove the first oxide layer 16 and to expose the fin structure 12
within the first region A. Since in this embodiment, both the first
oxide layer 16 and the second protective layer 20 mainly comprise
silicon oxide, they can be removed in a same etching process
simultaneously. It is worth noting that, in order to avoid the
oxide region 14 being damaged by the etching process, in this step,
the etching process preferably selects a dry-etching process.
Usually, a dry-etching process has a better performance in
controlling the etching rate, so compared with a wet-etching
process, a dry-etching process is a preferred choice to avoid the
oxide region 14 from being damaged.
[0019] Afterwards, referring to FIGS. 8-9, the first protective
layer 18 within the first region B is then removed, and as shown in
FIG. 9, a second oxide layer 24 is then formed to cover the exposed
fin structure 12 within the first region A. It is worth noting that
the thickness of the first oxide layer 16 and the second oxide
layer 24 are different. Preferably, the first oxide layer 16 is
thicker than the second oxide layer 24, thereby achieving two
individual FinFETs on one substrate 10. For example, a FinFET 1 and
a FinFET 2 are a n-FET device and a p-FET device respectively, or
selected from the group of the low voltage (LV) devices, the
memory, the core devices, electrostatic-sensitive device (ESD), IO
devices or high voltage (HV) devices, and these devices have
different oxide layer thicknesses, having individual work
functions.
[0020] In another case of the present invention, after the second
protective layer 20 within the second region B is removed
(corresponding to FIG. 7), the second oxide layer 24 can be formed
before the first protective layer 18 within the second region B is
removed. In other words, the first protective layer 18 within the
second region B may remain until the second oxide layer 24 is
formed. This process should be contained in the scope of the
present invention. However, preferably forming the second oxide
layer 24 is the final process in order to avoid the second oxide
layer 24 being exposed in air for a long time and influencing the
performance of the FinFET caused by oxidation.
[0021] In summary, the distinguishing feature of the present
invention is the use of a first protective layer and a second
protective layer, which are made of different materials. For
example, in the embodiment mentioned above, the first protective
layer comprises silicon nitride, and the second protective layer
comprises silicon oxide. These two dielectric layers protect the
oxide region disposed in the substrate and surround the fin
structure from the damages occurring during the etching processes.
Besides, since the silicon nitride first protective layer has high
selectivity with the first oxide layer disposed on the fin
structure and the oxide region, during the process for removing the
silicon nitride first protective layer, the first oxide layer and
the oxide region are not ruined by the etching processes, thereby
enhancing the yield and the performance of the FinFET.
[0022] Those skilled in the art will readily observe that numerous
modifications and alterations of the device and method may be made
while retaining the teachings of the invention. Accordingly, the
above disclosure should be construed as limited only by the metes
and bounds of the appended claims.
* * * * *