U.S. patent application number 14/231459 was filed with the patent office on 2015-05-14 for dual gate fd-soi transistor.
This patent application is currently assigned to STMicroelectronics International N.V.. The applicant listed for this patent is STMicroelectronics International N.V.. Invention is credited to Ankit Agrawal, Anand Kumar.
Application Number | 20150129967 14/231459 |
Document ID | / |
Family ID | 53043022 |
Filed Date | 2015-05-14 |
United States Patent
Application |
20150129967 |
Kind Code |
A1 |
Kumar; Anand ; et
al. |
May 14, 2015 |
DUAL GATE FD-SOI TRANSISTOR
Abstract
Circuit module designs that incorporate dual gate field effect
transistors are implemented with fully depleted
silicon-on-insulator (FD-SOI) technology. Lowering the threshold
voltages of the transistors can be accomplished through dynamic
secondary gate control in which a back-biasing technique is used to
operate the dual gate FD-SOI transistors with enhanced switching
performance. Consequently, such transistors can operate at very low
core voltage supply levels, down to as low as about 0.4 V, which
allows the transistors to respond quickly and to switch at higher
speeds. Performance improvements are shown in circuit simulations
of an inverter, an amplifier, a level shifter, and a voltage
detection circuit module.
Inventors: |
Kumar; Anand; (Noida,
IN) ; Agrawal; Ankit; (Greater Noida, IN) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
STMicroelectronics International N.V. |
Amsterdam |
|
NL |
|
|
Assignee: |
STMicroelectronics International
N.V.
Amsterdam
NL
|
Family ID: |
53043022 |
Appl. No.: |
14/231459 |
Filed: |
March 31, 2014 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
14078236 |
Nov 12, 2013 |
|
|
|
14231459 |
|
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Current U.S.
Class: |
257/350 ;
257/347; 438/154; 438/157 |
Current CPC
Class: |
H01L 29/66484 20130101;
H01L 21/7624 20130101; H01L 21/84 20130101; H01L 29/78648 20130101;
H01L 29/51 20130101; H01L 21/31111 20130101; H01L 21/26513
20130101; H01L 29/0649 20130101; H01L 29/7831 20130101; H01L 29/517
20130101; H01L 27/1203 20130101 |
Class at
Publication: |
257/350 ;
438/154; 438/157; 257/347 |
International
Class: |
H01L 27/12 20060101
H01L027/12; H01L 29/78 20060101 H01L029/78; H01L 21/265 20060101
H01L021/265; H01L 21/8238 20060101 H01L021/8238; H01L 21/762
20060101 H01L021/762; H01L 21/266 20060101 H01L021/266; H01L 27/092
20060101 H01L027/092; H01L 21/84 20060101 H01L021/84 |
Claims
1. A method of forming a silicon-on-insulator dual gate transistor
circuit, the method comprising: electrically coupling together
primary and secondary gates of a silicon-on-insulator dual gate
transistor; electrically coupling a source terminal of the
silicon-on-insulator dual gate transistor to a first circuit
element; and electrically coupling a drain terminal of the
silicon-on-insulator dual gate transistor to a second circuit
element.
2. The method of claim 1 wherein the first and second circuit
elements include one or more of a power supply, another electronic
device, or a connection to ground.
3. The method of claim 1 wherein the dual gate transistor includes
a buried oxide layer adjacent to the secondary gate.
4. The method of claim 1 wherein the dual gate transistor is an
NMOS dual gate transistor, the primary and secondary gates are both
coupled to a core power supply, the drain terminal is grounded, and
the source terminal is coupled to a PMOS transistor.
5. The method of claim 1 wherein the dual gate transistor is an
NMOS dual gate transistor, the primary and secondary gates are both
coupled to an input, the drain terminal is grounded, and the source
terminal is coupled to a PMOS transistor.
6. The method of claim 1 wherein the dual gate transistor is a PMOS
dual gate transistor, the primary and secondary gates are both
coupled to an input, the source terminal is coupled to a power
supply, and the drain terminal is coupled to an NMOS
transistor.
7. The method of claim 1 wherein the dual gate transistor is an
NMOS dual gate transistor, the primary and secondary gates are both
coupled to an input, the drain terminal is grounded, and the source
terminal is coupled to an output load.
8. The method of claim 1 wherein the dual gate transistor is an
NMOS dual gate transistor, the primary and secondary gates are both
coupled to an input of an inverter, the drain terminal is grounded,
and the source terminal is coupled to a power supply through a PMOS
transistor.
9. The method of claim 1 wherein the dual gate transistor is an
NMOS dual gate transistor, the primary and secondary gates are both
coupled to an output of an inverter, the drain terminal is
grounded, and the source terminal is coupled to a power supply
through a PMOS transistor.
10. The method of claim 1 wherein the dual gate transistor is a
first PMOS dual gate transistor, the primary and secondary gates
are both coupled to a second PMOS dual gate transistor, the drain
terminal is coupled to an NMOS dual gate transistor, and the source
terminal is coupled to a power supply.
11. A circuit module, comprising: a silicon-on-insulator dual gate
transistor; a first circuit element coupled to a source terminal of
the silicon-on-insulator dual gate transistor; a second circuit
element coupled to a drain terminal of the silicon-on-insulator
dual gate transistor; and an electrical conductor extending from
the primary gate to the secondary gate that electrically couples
the primary and secondary gates to one another.
12. The circuit module of claim 11 wherein the dual gate transistor
includes a buried oxide layer adjacent to the secondary gate.
13. The circuit module of claim 11 wherein the first circuit
element is a PMOS transistor, the second circuit element is a
ground connection, and the dual gate transistor is an NMOS dual
gate transistor configured with the primary and secondary gates
coupled to a core supply.
14. The circuit module of claim 11 wherein the first circuit
element is a power supply coupled to the source through a resistor,
the second circuit element is a ground connection, and the dual
gate transistor is an NMOS dual gate transistor configured with
primary and secondary gates coupled to an input terminal of the
amplifier circuit module.
15. The circuit module of claim 11 wherein the dual gate transistor
is part of a level shifter circuit in which the first circuit
element is power supply coupled to the source through a PMOS
transistor, the second circuit element is a ground connection, and
the dual gate transistor is an NMOS dual gate transistor configured
with primary and secondary gates coupled to an input terminal of an
inverter.
16. The circuit module of claim 11 wherein the dual gate transistor
is part of a level shifter circuit in which the first circuit
element is power supply coupled to the source through a PMOS
transistor, the second circuit element is a ground connection, and
the dual gate transistor is an NMOS dual gate transistor configured
with primary and secondary gates coupled to an output terminal of
an inverter.
17. An inverter circuit module, comprising: a PMOS dual gate
transistor having primary and secondary gates coupled to an input
terminal and a source terminal coupled to a power supply; and an
NMOS dual gate transistor having primary and secondary gates
coupled to the input terminal, and a drain terminal coupled to
ground, an output terminal of the inverter coupled to both a drain
terminal of the PMOS dual gate transistor and a source terminal of
the NMOS dual gate transistor.
18. A pass gate comprising an NMOS dual gate transistor configured
with primary and secondary gates coupled together.
19. A pass gate comprising a PMOS dual gate transistor configured
with primary and secondary gates coupled together.
20. A method of making a silicon-on-insulator dual gate transistor,
the method comprising: providing a silicon-on-insulator substrate
including a buried oxide layer over an N-doped region; forming a
primary gate that includes a gate electrode and a gate oxide;
implanting source and drain regions with dopant ions using the
primary gate as a mask; forming a front side contact to the N-doped
region for use of the N-doped region as a secondary gate; and
coupling the primary gate to the secondary gate.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] The present patent application is a continuation-in-part of
U.S. patent application Ser. No. 14/078,236, filed on Nov. 12,
2013, which is hereby incorporated by reference in its
entirety.
BACKGROUND
[0002] 1. Technical Field
[0003] The present disclosure relates to dual gate transistors
built on substrates having a buried oxide layer and, in particular,
to the use of such dual gate transistors in integrated circuits to
improve circuit performance.
[0004] 2. Description of the Related Art
[0005] Integrated circuits typically incorporate N-doped and
P-doped metal oxide semiconductor field effect transistor (MOSFET)
devices in which current flows through a semiconducting channel
between a source and a drain, in response to a bias voltage applied
to a gate. When the applied voltage exceeds a characteristic
threshold voltage V.sub.t, the device switches on. Ideally, such a
switch: a) passes zero current when it is off; b) supplies large
current flow when it is on; and c) switches instantly between the
on and off states. Unfortunately, a transistor is not ideal as
constructed in an integrated circuit and tends to leak current even
when it is off. Current that leaks through, or out of, the device
tends to drain the battery that supplies power to the device.
[0006] For many years, integrated circuit transistor performance
was improved by shrinking critical dimensions to increase switching
speed. However, as dimensions of silicon-based transistors continue
to shrink, maintaining control of various electrical
characteristics, including off-state leakage, becomes increasingly
more challenging, while performance benefits derived from shrinking
the device dimensions have become less significant. It is therefore
advantageous, in general, to increase switching speed and to reduce
leakage current in the transistor by alternative means, including
changes in materials and device geometry.
[0007] One technology that has been developed to control current
leakage is the silicon-on-insulator (SOI) transistor. Examples of
conventional planar (2-D) SOI transistor structures built on
substrates having a buried oxide (BOX) layer are shown in FIGS. 1A
and 1B and described below in greater detail. To provide better
control of the current flow in the channel, dual gate SOI
transistors have been developed, such as the exemplary dual gate
SOI transistor shown in FIG. 2, described in U.S. Patent
Publication No. 2010/0264492. A dual gate transistor is an
electronic switching device in which current flow within the
semiconducting channel of a traditional FET is controlled by two
gates instead of one, so as to influence the current flow from two
opposing surfaces instead of one.
[0008] Extending this idea further, 3-D tri-gate transistors have
been developed in which the planar semiconducting channel of a
traditional FET is replaced by a 3-D semiconducting fin that
extends outward, normal to the substrate surface. In such a device,
the gate, which controls current flow in the fin, wraps around
three sides of the fin so as to influence the current flow from
three surfaces instead of one or two. The improved control achieved
with such dual gate and tri-gate designs results in lower threshold
voltages, faster switching performance, and reduced current
leakage.
BRIEF SUMMARY
[0009] According to principles of the various embodiments as
discussed herein, an apparatus and method of making are described
that incorporate dual gate field effect transistors implemented
with fully depleted silicon-on-insulator (FD-SOI) technology. The
FD-SOI dual gate devices include a BOX layer adjacent to the
secondary gate that acts as a gate oxide for the secondary gate.
Lowering the V.sub.t of the transistors can be accomplished through
dynamic secondary gate control in which a back-biasing technique is
used to operate the dual gate FD-SOI transistors with enhanced
switching performance. By coupling both primary and secondary gates
of the dual gate FD-SOI devices together, the threshold voltage of
the device is lowered during the transition from the off state to
the on state, by enhancing the amount of charge required to form an
inversion region in the channel of the transistor. Meanwhile,
conventional direct current (DC) conditions are maintained during
steady state operation. Consequently, such transistors can operate
at very low core voltage supply levels, down to as low as 0.4 V,
which allows the transistors to respond quickly and to switch at
higher speeds. Such high performance devices run on a much wider
range of power supplies and can operate at higher frequencies.
Because no components are added, integrated circuits that
incorporate the dual gate FD-SOI devices are more area
efficient.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
[0010] In the drawings, identical reference numbers identify
similar elements. The sizes and relative positions of elements in
the drawings are not necessarily drawn to scale.
[0011] FIGS. 1A and 1B are cross sections of existing
silicon-on-insulator devices that illustrate partially depleted and
fully depleted channels.
[0012] FIG. 2 is a cross section of a typical dual gate SOI
transistor according to the prior art.
[0013] FIGS. 3A and 3B are cross-sectional and schematic diagrams
of a dual gate FD-SOI PMOS transistor, as described herein.
[0014] FIGS. 4A and 4B are cross-sectional and schematic diagrams
of a dual gate FD-SOI NMOS flip-well transistor, respectively, as
described herein.
[0015] FIG. 5 is a flow diagram showing steps in a method of making
a dual gate FD-SOI device, as described herein.
[0016] FIG. 6A is a schematic diagram of a dual gate FD-SOI
inverter circuit module as described herein.
[0017] FIG. 6B is a plot of simulated voltage waveforms associated
with the dual gate FD-SOI inverter circuit module shown in FIG.
6A.
[0018] FIG. 7A is a schematic diagram of a dual gate FD-SOI
amplifier circuit module as described herein.
[0019] FIG. 7B is a plot of simulated amplifier performance
associated with the dual gate FD-SOI amplifier circuit module shown
in FIG. 7A.
[0020] FIG. 8A is a schematic diagram of a level shifter circuit
configured with a dual gate transistor circuit module, as described
herein.
[0021] FIG. 8B is a plot of simulated performance associated with
the dual gate FD-SOI level shifter circuit module shown in FIG.
8A.
[0022] FIG. 9A is a schematic diagram of a core supply detection
circuit configured with a dual gate transistor circuit module, as
described herein.
[0023] FIG. 9B is a plot of simulated performance associated with
the core supply detection circuit module shown in FIG. 9A.
DETAILED DESCRIPTION
[0024] In the following description, certain specific details are
set forth in order to provide a thorough understanding of various
disclosed embodiments. However, one skilled in the relevant art
will recognize that embodiments may be practiced without one or
more of these specific details, or with other methods, components,
materials, etc. In other instances, well-known structures
associated with NMOS and PMOS transistors and associated circuits
have not been shown or described in detail to avoid unnecessarily
obscuring descriptions of the embodiments.
[0025] Unless the context requires otherwise, throughout the
specification and claims which follow, the word "comprise" and
variations thereof, such as, "comprises" and "comprising" are to be
construed in an open, inclusive sense, that is as "including, but
not limited to."
[0026] Reference throughout the specification to "one embodiment"
or "an embodiment" means that a particular feature, structure, or
characteristic described in connection with the embodiment is
included in at least one embodiment. Thus, the appearance of the
phrases "in one embodiment" or "in an embodiment" in various places
throughout the specification are not necessarily all referring to
the same aspect. Furthermore, the particular features, structures,
or characteristics may be combined in any suitable manner in one or
more aspects of the present disclosure.
[0027] Reference throughout the specification to integrated
circuits is generally intended to include integrated circuit
components built on semiconducting substrates, whether or not the
components are coupled together into a circuit or able to be
interconnected. Throughout the specification, the term "layer" is
used in its broadest sense to include a thin film, a cap, or the
like and one layer may be composed of multiple sub-layers.
[0028] Reference throughout the specification to conventional thin
film deposition techniques for depositing silicon nitride, silicon
dioxide, metals, or similar materials include such processes as
chemical vapor deposition (CVD), low-pressure chemical vapor
deposition (LPCVD), metal organic chemical vapor deposition
(MOCVD), plasma-enhanced chemical vapor deposition (PECVD), plasma
vapor deposition (PVD), atomic layer deposition (ALD), molecular
beam epitaxy (MBE), electroplating, electro-less plating, and the
like. Specific embodiments are described herein with reference to
examples of such processes. However, the present disclosure and the
reference to certain deposition techniques should not be limited to
those described. For example, in some circumstances, a description
that references CVD may alternatively be done using PVD, or a
description that specifies electroplating may alternatively be
accomplished using electro-less plating. Furthermore, reference to
conventional techniques of thin film formation may include growing
a film in-situ. For example, in some embodiments, controlled growth
of an oxide to a desired thickness can be achieved by exposing a
silicon surface to oxygen gas or to moisture in a heated
chamber.
[0029] Reference throughout the specification to conventional
photolithography techniques, known in the art of semiconductor
fabrication for patterning various thin films, includes a
spin-expose-develop process sequence typically followed by an etch
process. Alternatively or additionally, photoresist can also be
used to pattern a hard mask (e.g., a silicon nitride hard mask),
which, in turn, can be used to pattern an underlying film.
[0030] Reference throughout the specification to conventional
etching techniques known in the art of semiconductor fabrication
for selective removal of polysilicon, silicon nitride, silicon
dioxide, metals, photoresist, polyimide, or similar materials
includes such processes as wet chemical etching, reactive ion
(plasma) etching (RIE), washing, wet cleaning, pre-cleaning, spray
cleaning, chemical-mechanical planarization (CMP) and the like.
Specific embodiments are described herein with reference to
examples of such processes. However, the present disclosure and the
reference to certain deposition techniques should not be limited to
those described. In some instances, two such techniques may be
interchangeable. For example, stripping photoresist may entail
immersing a sample in a wet chemical bath or, alternatively,
spraying wet chemicals directly onto the sample.
[0031] Specific embodiments are described herein with reference to
dual gate FD-SOI transistors that have been produced; however, the
present disclosure and the reference to certain materials,
dimensions, and the details and ordering of processing steps are
exemplary and should not be limited to those shown.
[0032] FIGS. 1A and 1B provide general information about SOI
transistors, familiar to those skilled in the art of transistor
design. In particular, FIGS. 1A and 1B illustrate what is meant by
the terms "partially depleted" and "fully depleted" transistors.
FIG. 1A shows a partially depleted MOS SOI transistor 100 in cross
section. Like standard bulk MOS transistors, the partially depleted
SOI transistor 100 is a three-terminal device in which a voltage
applied to a gate 102 causes current to flow from a source 104 to a
drain 106 through a channel 108. The gate 102 is separated from the
rest of the device by a thin capacitive gate oxide layer 110. A
bulk silicon substrate 114 may be doped, for example, with negative
ions, to form an NWELL region. The partially depleted SOI
transistor 100 differs from a bulk MOS transistor in that there
exists a buried oxide (BOX) layer 112 between the channel 108 and
the bulk silicon substrate 114. A depletion region 116, depleted of
charge, that forms below the channel 108, between the source and
drain regions 104 and 106, is then bounded below by the BOX layer
112. The depletion region can also be referred to as an inversion
region. Normally, the presence of the BOX layer prevents the
substrate voltage from electrically influencing the channel 108.
The extent of the depletion region then depends on the relative
dimensions of the various layers, as well as source and drain
doping profiles, 117 and 118, respectively, and doping
concentrations of the source and drain regions. In the case of the
partially-depleted SOI device shown in FIG. 1A, the depletion
region 116 does not fill all of the material between the source and
the drain, wherein an un-depleted portion 119 remains at an
undetermined floating electric potential. The presence of the
un-depleted portion 119 is generally undesirable because it is not
well controlled, and yet the associated floating electric potential
can electrically influence the channel and degrade the transistor
performance.
[0033] A fully depleted SOI (FD-SOI) transistor 120 is shown in
FIG. 1B in cross section. Like the partially depleted SOI
transistor 100 shown in FIG. 1A, the FD-SOI transistor 120 also has
a BOX layer 112. However, the source and drain regions of the
FD-SOI device, 124 and 126 respectively, are shallower than the
source and drain regions 104 and 106 of the FD-SOI device 120. As a
result, doping profiles 127 and 128 are effectively vertical, and
the charge characteristics of the channel can be set by the doping
concentrations such that a fully charge-depleted region 116 forms
between the shallow source and drain regions 124 and 126, bounded
below by the BOX layer 112, in response to application of a bias
voltage to the gate 102. Because all of the material between the
source and drain is charge-depleted, the un-depleted portion 119
shown in FIG. 1A has been eliminated as a possible cause of
transistor degradation.
[0034] FIG. 2 shows a generalized example of the architecture of a
typical dual gate SOI transistor 130 as shown in U.S. Patent
Publication No. 2010/0264492. Like the conventional MOS and SOI
devices, the dual gate SOI transistor 130 has a primary gate 102, a
source 104 and a drain 106 on either side of a channel 108, wherein
the primary gate 102 is separated by a thin primary gate oxide
layer 110. In addition, the dual gate SOI transistor 130 includes a
secondary gate 132, which is separated from the channel region 108
by a thin, secondary gate oxide layer 134. Both the primary and
secondary gates 102 and 132 can be biased so as to influence
current flow in the channel region 108. The dual gate SOI
transistor 130 is usually operated by coupling the secondary gate
132 to a supply voltage or to ground, while a bias voltage is
applied to the primary gate 102.
[0035] FIGS. 3A and 4A show cross-sectional representations of a
dual gate PMOS FD-SOI transistor 136 and a dual gate NMOS FD-SOI
transistor 138, respectively, as disclosed herein. The
cross-sectional views more clearly show the structure of the dual
gate FD-SOI transistors for direct comparison with the conventional
dual gate transistor 130 shown in FIG. 2. Like the dual gate SOI
transistor 130, dual gate FD-SOI transistors are four-terminal
devices having a source S, a drain D, a primary gate G1, and a
secondary gate G2. In the dual gate PMOS FD-SOI transistor 136
shown in FIG. 3A, for example, the channel 137 can be controlled by
a bias voltage applied to either the primary gate G1, or the
secondary gate G2, or both.
[0036] Unlike the dual gate SOI transistor 130, in the embodiment
shown in FIG. 3A, the secondary gate G2 is the substrate, which is
doped to form the NWELL region 114, as is customary and well known
in the art. Furthermore, the secondary gate G2 can be biased by
applying a voltage to the NWELL region 114 of the substrate via a
front side NWELL contact 140. The secondary gate G2 is spaced apart
from the channel 137 by a secondary gate oxide layer which, in the
embodiment shown, is the BOX layer 112. Thus, between G1 and G2,
there exist two capacitances, C.sub.gate across the primary gate
oxide layer 110, and C.sub.box across the BOX layer 112. The BOX
layer 112 provides a much thicker capacitive dielectric than does
the gate oxide layer 110.
[0037] It is noted that the PMOS FD-SOI device shown in FIG. 3A is
formed in the NWELL region 114, in the conventional way that is
well known in the art, whereas the NMOS FD-SOI device shown in FIG.
4A is also formed in an NWELL region 114, which is unconventional.
Typically an N-type transistor is formed in a PWELL region.
Depending on the circuit application of the FD-SOI device, the
polarity of the well doping, as well as the doping concentration,
can be adjusted so as to produce the most desirable electrical
effect. Consequences of such design choices can be evaluated using
device simulations.
[0038] In the circuit applications disclosed herein, the secondary
gates of each of the dual gate FD-SOI transistors can be thought of
as being short-circuited to their respective primary gates. Hence,
G1 and G2 are shown as tied together in FIGS. 3A and 4A by
electrical connections 142 and 144, respectively. The effect of
coupling the primary and secondary gates together is that the
secondary gate back-biases the transistor to create an inversion
layer in the channel region faster than usual. This causes the
threshold voltage to be lower so that the device turns on easier,
and the transition time from the low state to the high state is
therefore shorter. Because the primary gate is also biased high at
the same time, the back-biasing translates to an improvement in the
switching performance.
[0039] The back-biasing technique is not effective when used with
dual gate bulk transistors because the performance of bulk devices
is subject to limitations that do not affect FD-SOI devices. One
such limitation is that the bias voltage is limited to a range of
about 200-300 mV in bulk technologies, because the gate oxide is so
thin. This limitation does not exist in an FD-SOI device because
the source and drain are fully isolated from the substrate by the
BOX layer 112. Another limitation that affects bulk transistors is
that the effectiveness of a body bias degrades as transistor
dimensions shrink in subsequent technology generations. The body
bias becomes ineffective at about the 20 nm node.
[0040] The dual gate FD-SOI transistors 136 and 138 as described
herein are represented schematically in FIGS. 3B and 4B, configured
as pass gates. It is noted that the gate terminals G1 and G2 are
coupled together by the electrical connectors 142, 144 during
operation of both the PMOS and NMOS devices. The output voltage of
a pass gate has the same value as its input. Thus, a pass gate can
be made by coupling together the primary and secondary gates of the
dual gate FD-SOI transistors 136 and 138. It is further noted that
the PMOS FD-SOI transistor 136 switches on in response to a
negative voltage applied to the gates G1 and G2, because in a PMOS
device, charge carriers in the channel 137 are positively charged
holes. Thus, the PMOS device is shown as having an inverted input
at the primary gate G1.
[0041] FIG. 5 shows high level steps in a method 150 of making the
dual gate FD-SOI transistors 136 and 138 shown in FIGS. 3A and 4A,
respectively.
[0042] At 152, a starting material is provided as a
silicon-on-insulator (SOI) wafer that includes the BOX layer 112
over a heavily N-doped region, which is the NWELL region 114. In
one embodiment, the BOX layer 112 has a thickness within the range
of about 15-30 nm so that it can sustain application of up to about
.+-.3.3 V to the NWELL region 114 without experiencing a structural
breakdown. The thickness of the BOX layer 112 is large compared
with the gate oxide layer 110 separating the primary gate G1 from
the channel 137. However, the BOX layer 112 is thin compared with a
typical BOX layer, which can be as thick as about 100 nm. An SOI
wafer of the ultrathin body and buried oxide (UTBB) type, for
example, will provide the desired thickness of the BOX layer. The
SOI wafer includes an active region above the BOX layer 112 in
which the transistor is formed. The active region thickness can be
in the range of about 10-200 nm, but is desirably between 10 and 50
nm for the devices described herein.
[0043] At 153, the gate oxide layer 110 is formed on the surface of
the active region of silicon by depositing a thin layer of silicon
dioxide, or a high-k dielectric material such as halfnium oxide,
for example. The gate oxide thickness is typically about 10 nm.
[0044] At 154, the primary gate 102 is deposited and both the gate
102 and the gate oxide layer 110 are patterned using standard
deposition, lithography, and etching techniques well known in the
art. The primary gate 102 can be made of polysilicon or metal,
common materials well known in the art.
[0045] At 156, the primary gate 102 is used as a mask for doping
the source and drain regions 104 and 106, respectively, by
implanting either positive ions or negative ions, as is known in
the art. The penetration depth of ions implanted into the silicon
substrate is limited by the location of the BOX layer 112.
[0046] At 158, the front side NWELL contact 140 is formed by
etching and filling a trench that extends through the BOX layer 112
to the top of the NWELL region 114.
[0047] At 159, the primary gate G1 (102) is coupled to the
secondary gate G2 by the electrical connection 142. The electrical
connection 142 can be an integral connection made according to a
wiring design at an interconnect layer, for example, metal 1,
formed after the transistor is complete.
[0048] While the techniques used to form layers within the dual
gate FD-SOI transistors 136 and 138 are well known, formation of
the structures is unique to the disclosed embodiments. In
particular, such structures include the contact 140 to the NWELL
region 114 for use as a secondary gate, and separation of the
secondary gate from the channel 137 by the BOX layer 112.
[0049] FIGS. 6A-9 show exemplary embodiments of different circuit
elements implemented using the dual gate FD-SOI devices 136 and
138, and demonstrate their advantages over conventional circuit
elements. In each circuit application, performance improvements are
achieved by back-biasing the devices i.e., biasing the secondary
gate G2 by connecting it to the primary gate G1, and applying a
bias voltage to both gates. Through such a back-biasing technique,
current within the channel 137 is controlled from both the top side
and the back side, instead of only from one side. The channel 137
is therefore more responsive to the biasing voltage. Furthermore,
instead of the BOX layer isolating the substrate 114 from the
active region, the substrate 114 is used to control the active
region dynamically, through the BOX layer 112. The greater degree
of sensitivity achieved by the BOX-controlled back-biasing
technique means that the device turns on at a lower bias threshold
voltage V.sub.t, and the current in the channel responds more
quickly to voltage changes, which means that the device can operate
at higher frequencies.
[0050] Such performance enhancements are evident in the plots
below, which are derived from circuit simulations. Simulation
results were obtained using ELDO circuit simulation software
available from Mentor Graphics, Inc. of Wilsonville, Oreg. In the
circuit simulations, conventional transistor parameters are
replaced by parameters describing the dual gate FD-SOI transistors,
which are then driven using the back-biasing technique.
[0051] FIG. 6A shows a dual gate inverter 160 created by coupling
together the PMOS dual gate FD-SOI device 136 and the NMOS dual
gate FD-SOI device 138 in a standard inverter configuration. The
standard inverter configuration includes a supply voltage V.sub.DD
applied to the source terminal of the PMOS device 136, ground
applied to the drain terminal of the NMOS device 138, an input
voltage V.sub.in applied to both the primary gates, and the drain
terminal of the PMOS device 136 coupled to the source terminal of
the NMOS device 138 at the output of the inverter. In addition, in
the present dual gate inverter 160, the primary and secondary gates
G1 and G2 of each device are shorted together at 142 and 144,
respectively.
[0052] FIG. 6B shows simulation results testing the performance of
the dual gate inverter 160 as shown in FIG. 6A. FIG. 6B includes a
top panel 168 and a bottom panel 169. The top panel 168 shows a
time-varying input voltage signal V.sub.in, which resembles a
triangular wave having a maximum amplitude of 2 V and a frequency
of 1 GHz. The bottom panel 169 shows time-varying output voltage
signals V.sub.out0, which correspond to a conventional inverter
circuit element, and V.sub.out1, which corresponds to the dual gate
inverter 160 as described herein. An ideal inverter output signal
would look like an upside-down V.sub.in, such that whenever
V.sub.in is on at 2.0 V, V.sub.out is off at 0 V, and vice
versa.
[0053] By comparing the bottom panel 169 with the top panel 168, it
is clear that the signal V.sub.out1 responds faster than does the
signal V.sub.out to changes in the input voltage signal V.sub.in.
For example, as soon as V.sub.in rises, V.sub.out1 drops, whereas
there is a delay .DELTA.t 171 before V.sub.out responds. Taking
into account both the rise time and fall time delays associated
with V.sub.out, a performance improvement of nearly 30% is evident
in the simulation of the dual gate inverter 160. The faster
response associated with the dual gate inverter 160 can be
attributed to the channels 137 in each of the NMOS and PMOS devices
being influenced simultaneously from both sides by the primary and
secondary gates G1 and G2, wherein G2 is the N-doped substrate
acting through the BOX layer 112. Under the influence of both G1
and G2, formation of the inversion region that provides a
conduction path from source to drain via the channel 137 occurs
faster.
[0054] FIG. 7A shows a dual gate amplifier 170 created by coupling
the PMOS dual gate FD-SOI device 136 and a reference resistor
R.sub.ref in a standard amplifier configuration. The standard
amplifier configuration includes a supply voltage V.sub.DD applied
to the source terminal of the PMOS device 136 through the reference
resistor R.sub.ref, ground applied to the drain terminal of the
PMOS device 136, and an input voltage V.sub.in applied to the
primary gate G1. In addition, in the present dual gate amplifier
170, the primary and secondary gates G1 and G2 of the PMOS device
136 are shorted together at 142.
[0055] FIG. 7B shows simulation results testing the performance of
the dual gate amplifier 170 as shown in FIG. 7A. The expected
behavior of an amplifier is to boost the magnitude of the input
signal to a higher value. FIG. 7B shows the magnitude in decibels
of the amplifier gain, which is the ratio of V.sub.out/V.sub.in.
The bottom gain value V.sub.out0/V.sub.in=2.66 dB corresponds to a
conventional amplifier circuit element and the top gain value
V.sub.out1/V.sub.in=7.07 dB corresponds to the dual gate amplifier
170 as described herein. The dual gate amplifier 170 therefore
shows a gain that is about 2.7 times larger than the conventional
amplifier gain. By coupling the primary and secondary gates G1 and
G2 together, the threshold voltage of the dual gate transistor is
effectively lowered, which boosts the output voltage.
[0056] FIG. 8A shows a dual gate level shifter circuit 180 created
by coupling two conventional PMOS devices and two NMOS dual gate
FD-SOI devices 138a and 138b in the level shifter configuration
shown. The level shifter configuration includes applying a supply
voltage V.sub.DD to the source terminals of the PMOS devices, and
cross-coupling the PMOS devices to the source terminals of the NMOS
dual gate FD-SOI devices 138a,b. The level shifter configuration
further includes coupling the gates of the NMOS dual gate FD-SOI
devices 138a,b across an inverter 182, and grounding the drain
terminals of the NMOS dual gate FD-SOI devices 138a,b. In the
present dual gate level shifter circuit 180, the primary and
secondary gates G1 and G2 in each of the NMOS devices 138a,b are
shorted together at 144a and 144b, respectively, so that a bias
voltage applied to the primary gate activates the secondary gate
simultaneously, resulting in a faster turn-on time for the
transistor.
[0057] FIG. 8B shows simulation results testing the performance of
the dual gate level shifter circuit 180 as shown in FIG. 8A against
that of a conventional level shifter that includes conventional
NMOS devices. Expected behavior of the level shifter circuit is to
shift the magnitude of the input signal to a higher value so that a
low core supply voltage is sufficient to operate the circuit.
[0058] FIG. 8B includes a top panel 188 and a bottom panel 189. The
top panel 188 shows a time-varying input voltage signal V.sub.in,
which resembles a square wave having a maximum amplitude of about
0.4 V and a frequency of 1 MHz, corresponding to a period of 1.0
.mu.s. An ideal level shifter output signal would look similar to
V.sub.in, except the amplitude would be shifted to a higher value.
It is observed that the top panel 188 shows an output signal
V.sub.out0 that is shifted to a higher voltage level of about 1.8
V, but that V.sub.out0 remains at 1.8 V continuously.
[0059] In contrast, the bottom panel 189, which corresponds to the
dual gate level shifter circuit 180 as described herein, shows that
the improved output voltage signal V.sub.out0 also boosts the 0.4 V
input signal up to about 1.8 V, but the dual gate level shifter
circuit 180 is able to respond to the input signal with only about
a 0.3 .mu.s delay. At the relatively low frequency of 1 MHz,
V.sub.out1 has the desired square wave shape. The faster response
associated with the dual gate level shifter 180 can be attributed
to the channel 137 in each of the NMOS devices being influenced
simultaneously from both sides by primary and secondary gates.
Further discussion of level shifter circuit configurations that use
dual gate transistors is found in U.S. patent application Ser. No.
14/078,236.
[0060] FIG. 9A shows a core supply detection circuit 190. A core
supply detection circuit is a voltage detection circuit for low
voltage levels, for example, a low voltage core supply. At the
input stage a dual gate inverter 160 of the type shown and
described with respect to FIG. 6A receives an input voltage
V.sub.in. In some embodiments V.sub.in can be coupled to V.sub.DD
as the input voltage. In other embodiments, V.sub.in can be other
voltages. The core supply detection circuit 190 can be configured
with one or more dual gate inverters 160 at different locations
beyond the one example shown. Again, the NMOS device interconnect
is formed with the primary and secondary gates coupled together for
improved performance in detecting low voltages, as explained
herein. When both the primary and secondary gates are influencing
the channel 137 through the BOX layer 112, the threshold voltage of
the device is effectively lowered, such that the dual gate inverter
160 turns on in response to application of a lower bias voltage. As
a result, the detection circuit 190 is more sensitive to low
voltages than is a conventional detection circuit.
[0061] FIG. 9B shows simulation results testing the performance of
the core supply detection circuit 190 as shown in FIG. 9A against
that of a conventional core supply detection circuit that includes
conventional inverters at every stage. Expected behavior of the
core supply detection circuit is to turn on when V.sub.IN switches
off, and remain high until V.sub.IN switches on again. FIG. 9B
includes a top panel 198 and a bottom panel 199. The top panel 198
shows a time-varying input voltage signal V.sub.IN, which resembles
a square wave having a maximum amplitude of about 0.3 V and a
frequency of 1 MHz, corresponding to a period of 1.0 .mu.s. An
ideal core supply detection circuit output signal would look
similar to V.sub.IN, except the signal amplitude would be boosted
to a higher value, and inverted with respect to V.sub.IN. It is
observed that the top panel 198 shows an output signal V.sub.COFF
that remains at 1.8 V continuously, indicating failure at a core
supply of 0.3 V.
[0062] In contrast, the bottom panel 199, which corresponds to the
core supply detection circuit 190 as described herein, shows that
the improved output voltage signal V.sub.COFF2 also boosts the 0.3
V input signal up to about 1.8 V, but the core supply detection
circuit 190 is able to respond to the input signal with
substantially no delay. At the relatively low frequency of 1 MHz,
V.sub.COFF2 has the desired inverted square wave shape and greater
amplitude. The faster response associated with the dual gate core
supply detection circuit 190 can be attributed to the channel 137
in the dual gate NMOS device within the inverter 160 being
influenced simultaneously from both sides by primary and secondary
gates.
[0063] The various embodiments described above can be combined to
provide further embodiments. All of the U.S. patents, U.S. patent
application publications, U.S. patent applications, foreign
patents, foreign patent applications and non-patent publications
referred to in this specification and/or listed in the Application
Data Sheet are incorporated herein by reference, in their entirety.
Aspects of the embodiments can be modified, if necessary to employ
concepts of the various patents, applications and publications to
provide yet further embodiments.
[0064] It will be appreciated that, although specific embodiments
of the present disclosure are described herein for purposes of
illustration, various modifications may be made without departing
from the spirit and scope of the present disclosure. Accordingly,
the present disclosure is not limited except as by the appended
claims.
[0065] These and other changes can be made to the embodiments in
light of the above-detailed description. In general, in the
following claims, the terms used should not be construed to limit
the claims to the specific embodiments disclosed in the
specification and the claims, but should be construed to include
all possible embodiments along with the full scope of equivalents
to which such claims are entitled. Accordingly, the claims are not
limited by the disclosure.
* * * * *