U.S. patent application number 14/596991 was filed with the patent office on 2015-05-07 for semiconductor device.
The applicant listed for this patent is Renesas Electronics Corporation. Invention is credited to Hidenori EGAWA.
Application Number | 20150123274 14/596991 |
Document ID | / |
Family ID | 43464699 |
Filed Date | 2015-05-07 |
United States Patent
Application |
20150123274 |
Kind Code |
A1 |
EGAWA; Hidenori |
May 7, 2015 |
SEMICONDUCTOR DEVICE
Abstract
A semiconductor device includes a substantially rectangular
semiconductor chip having an obverse surface, a first long side, a
second long side opposite the first long side, a first short side
and a second short side, and a plurality of bump electrodes. A
wiring substrate has a main surface, a first side disposed outside
of the semiconductor chip and extending substantially parallel with
the first long side, a second side disposed outside of the
semiconductor chip and extending substantially parallel with the
second long side, and a plurality of wiring groups, each including
a plurality of wirings. A semiconductor chip is mounted on the
wiring substrate such that the obverse surface of the semiconductor
chip is faced to the main surface of the wiring substrate and the
first long side is located between the first side of the wiring
substrate and the second long side, in a plan view.
Inventors: |
EGAWA; Hidenori; (Kanagawa,
JP) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Renesas Electronics Corporation |
Kawasaki-shi |
|
JP |
|
|
Family ID: |
43464699 |
Appl. No.: |
14/596991 |
Filed: |
January 14, 2015 |
Related U.S. Patent Documents
|
|
|
|
|
|
Application
Number |
Filing Date |
Patent Number |
|
|
14186592 |
Feb 21, 2014 |
8975762 |
|
|
14596991 |
|
|
|
|
13762512 |
Feb 8, 2013 |
8686574 |
|
|
14186592 |
|
|
|
|
12801303 |
Jun 2, 2010 |
8384230 |
|
|
13762512 |
|
|
|
|
Current U.S.
Class: |
257/737 |
Current CPC
Class: |
H01L 24/14 20130101;
H01L 2924/14 20130101; H01L 23/12 20130101; H01L 2224/81385
20130101; H01L 23/50 20130101; H01L 2924/01079 20130101; H01L 24/16
20130101; H01L 23/4985 20130101; H01L 23/49838 20130101; H01L 23/34
20130101; H01L 2924/014 20130101; H01L 2224/131 20130101; H01L
23/3735 20130101; H01L 2224/131 20130101; H01L 24/17 20130101 |
Class at
Publication: |
257/737 |
International
Class: |
H01L 23/34 20060101
H01L023/34; H01L 23/50 20060101 H01L023/50; H01L 23/12 20060101
H01L023/12; H01L 23/00 20060101 H01L023/00 |
Foreign Application Data
Date |
Code |
Application Number |
Jul 15, 2009 |
JP |
2009-166975 |
Claims
1. A semiconductor device, comprising: a semiconductor chip of a
substantially rectangular shape having an obverse surface, a first
long side, a second long side opposite the first long side, a first
short side and a second short side, which intersect the first and
second long sides, and a plurality of bump electrodes formed on the
obverse surface, the plurality of bump electrodes including first
bump electrodes arranged along the first long side, second bump
electrodes arranged along the first long side and arranged closer
to the first short side than the first bump electrodes, third bump
electrodes arranged along the first long side and arranged closer
to the second short side than the first bump electrodes; and a
wiring substrate having a main surface, a first side disposed
outside of the semiconductor chip and extending substantially
parallel with the first long side of the semiconductor chip, a
second side disposed outside of the semiconductor chip and
extending substantially parallel with the second long side of the
semiconductor chip, and a plurality of wiring groups, each said
wiring group including a plurality of wirings formed on the main
surface thereof, the semiconductor chip being mounted on the wiring
substrate such that the obverse surface of the semiconductor chip
is faced to the main surface of the wiring substrate and the first
long side of the semiconductor chip is located between the first
side of the wiring substrate and the second long side of the
semiconductor chip, in a plan view, the plurality of wiring groups
including a first wiring group, a second wiring group, and a third
wiring group, the first wiring group including first wirings, for
heat dissipation, whose one end portions are electrically and
mechanically connected to respective ones of the first bump
electrodes, the second wiring group including second wirings, for
signals, whose one end portions are electrically connected to
respective ones of the second bump electrodes, the third wiring
group including third wirings, for signals, whose one end portions
are electrically connected to respective ones of the third bump
electrodes, the first wirings being extended from the first long
side of the semiconductor chip toward the first side of the wiring
substrate, and each of the other end portions of the first wirings
being terminated between the first long side of the semiconductor
chip and the first side of the wiring substrate, in the plan view
the second and third wirings being extended from the first long
side of the semiconductor chip toward the first side of the wiring
substrate, in the plan view, wherein the first wiring group further
includes a wiring pattern for power supply, whose one portions are
electrically connected to respective ones of the first bump
electrodes, wherein one end portions of the first wirings are
arranged between the one portions of the wiring pattern, and
wherein, in the plan view, the second and third wiring groups are
arranged to surround the first wiring group.
Description
[0001] This application is a Continuation application of U.S.
patent application Ser. No. 14/186,592, filed on Feb. 21, 2014,
which is a Continuation application of U.S. patent application Ser.
No. 13/762,512, (Now U.S. Pat. No. 8,686,574) filed on Feb. 8,
2013, which is a Continuation application of U.S. patent
application Ser. No. 12/801,303 (Now U.S. Pat. No. 8,384,230) and
which claims priority from JPA No. 2009-166975, incorporated herein
by reference.
INCORPORATION BY REFERENCE
[0002] This application is based upon and claims the benefit of
priority from Japanese patent application No. 2009-166975, filed on
Jul. 15, 2009, the disclosure of which is incorporated herein in
its entirety by reference.
BACKGROUND
[0003] 1. Field of the Invention
[0004] The present invention relates to a semiconductor device that
includes a wiring board and an integrated circuit (IC) chip mounted
thereon and, particularly, to a heat dissipation structure in a
semiconductor device.
[0005] 2. Description of Related Art
[0006] The heat value of an IC chip such as a liquid crystal driver
IC during operation is on the increase. The increase in the IC chip
heat value is particularly significant in a semiconductor device
using a flexible wiring board compared to a semiconductor device
using a rigid wiring board. Therefore, a heat dissipation structure
in a semiconductor device becomes increasingly important.
[0007] A flexible wiring board has a structure in which a conductor
layer such as lines is formed on a flexible insulating film. For
example, the conductor layer is formed by applying copper foil to a
polyimide film, which is the insulating film. The flexible wiring
board has a lower heat capacity and a lower mechanical strength
compared to the rigid wiring board for its thin profile. It is thus
generally difficult to mount heavy parts such as a heat sink on the
flexible wiring board.
[0008] In order to deal with the heat issue when using a flexible
wiring board, Japanese Unexamined Patent Application Publications
Nos. 2007-158001 and 2004-111996 disclose a heat dissipation
structure of a tape carrier package (TCP), which is one type of a
semiconductor device using a flexible wiring board. The TCP
disclosed in Japanese Unexamined Patent Application Publication No.
2007-158001 (JP 2007-158001 A) has the following structure. Namely,
an IC chip that has an electrode for heat dissipation separately
from an electrode used for signal input/output with an external
device is mounted on a flexible wiring board. Further, a heat
dissipation conductive pattern that is physically isolated from a
signal line pattern is formed on the surface of the flexible wiring
board. The heat dissipation electrode of the IC chip and the heat
dissipation conductive pattern of the wiring board are connected
through a conductor (gold bump, solder etc.). In this
specification, connection through a conductor such as gold bump or
solder is referred to as "conductor connection".
[0009] Japanese Unexamined Patent Application Publication No.
2004-111996 (JP 2004-111996 A) also discloses a technique that
forms a heat dissipation conductive pattern on the surface of a
flexible wiring board for the purpose of heat dissipation of an IC
chip mounted on the flexible wiring board. However, in JP
2004-111996 A, no electrodes of the IC chip and the heat
dissipation conductive pattern are connected. Specifically, JP
2004-111996 A discloses a structure in which the IC chip and the
heat dissipation conductive pattern are physically spaced (FIG. 3
in JP 2004-111996 A) and a structure in which the IC chip and the
heat dissipation conductive pattern are physically contacted (FIG.
6 in JP 2004-111996 A). More specifically, FIGS. 3 and 6 of JP
2004-111996 A show structures in which no electrodes of the IC chip
and the heat dissipation conductive pattern are in conductor
connection and the heat dissipation conductive pattern is formed
opposite to all over the length of the short side of the
rectangular IC chip.
SUMMARY
[0010] As described above, the semiconductor device disclosed in JP
2007-158001 A has the heat dissipation structure in which the heat
dissipation conductive pattern that is formed on the flexible
wiring board and the heat dissipation electrode of the IC chip are
connected by a conductor with a low heat resistance. The heat
resistance between the IC chip and the heat dissipation conductive
pattern thereby decreases, which allows improvement in heat
dissipation effect. However, there are many cases where conductor
connection cannot be made between the electrode of the IC chip and
the heat dissipation conductive pattern, such as when terminals
with different potentials are arranged irregularly in the vicinity
of the IC chip or when there is a concern about electro-static
discharge (ESD). For example, when the IC chip is a driver IC that
drives a liquid crystal display panel, the driver IC can suffer
damage from discharge when a charged human body comes into contact
with the liquid crystal display panel. Because the heat dissipation
conductive pattern generally has a large surface area to enhance
the heat dissipation effect, conductor connection between the heat
dissipation conductive pattern and the IC chip causes an increase
in the probability that the IC chip is damaged by ESD.
[0011] On the other hand, as described above, the heat dissipation
structures disclosed in JP 2004-111996 A are structures in which
conductor connection is not made between the electrode of the IC
chip and the heat dissipation conductive pattern. Specifically,
FIGS. 3 and 6 of JP 2004-111996 A show the structures in which the
heat dissipation conductive pattern and the chip electrode are
electrically insulated, and the heat dissipation conductive pattern
is formed opposite to all over the length of one side of the
rectangular chip. The structure has an advantage that it can
reliably avoid the damage of the IC chip by ESD, and it is thus
effective in the case where conductor connection cannot be made
between the electrode of the IC chip and the heat dissipation
conductive pattern.
[0012] However, it is considered to be difficult in practice to
adopt the structure in which the IC chip and the heat dissipation
conductive pattern are physically in contact without contact
between the electrode of the IC chip and the heat dissipation
conductive pattern (FIG. 6 in JP 2004-111996 A), which is one of
the heat dissipation structures disclosed in JP 2004-111996 A. It
is particularly difficult in a flip-chip package (face-down
package) where the IC chip is mounted with the surface on which a
functional circuit and an electrode are formed facing the wiring
board. A large number of electrode pads are often arranged in the
peripheral part of the IC chip, which is required to decrease in
size, in terms of ensuring stable connection, and it is normally
difficult to make physical contact between the heat dissipation
conductive pattern and the IC chip by avoiding contact with the
electrode.
[0013] On the other hand, regarding the structure in which the IC
chip and the heat dissipation conductive pattern are physically
spaced (FIG. 3 in JP 2004-111996 A), which is the other one of the
heat dissipation structures disclosed in JP 2004-111996 A, the
length of the interface at which the rectangular IC chip and the
heat dissipation conductive pattern are placed opposite to each
other is as short as the length of the short side of the IC chip.
Thus, heat conduction from the IC chip to the heat dissipation
conductive pattern is not sufficient, which raises the IC chip
temperature and thus causes an increase in the temperature gradient
near the IC chip.
[0014] As described above, the heat dissipation structures
disclosed in JP 2007-158001 A and JP 2004-111996 A have a problem
that heat conduction from the IC chip to the heat dissipation
conductive pattern is not sufficient when conductor connection
cannot be made between the electrode of the IC chip and the heat
dissipation conductive pattern.
[0015] An exemplary aspect of the present invention is a
semiconductor device which includes a wiring board that has a
conductive pattern formed on at least one principal surface, and an
IC chip that is mounted on the wiring board. The IC chip includes a
plurality of electrodes to make conductor connection with the
wiring board.
[0016] The conductive pattern includes a lead line pattern and a
heat dissipation pattern. The lead line pattern is connected with
at least one of the plurality of electrodes through a conductor.
The heat dissipation pattern is physically spaced from each of the
IC chip and the lead line pattern and has a larger surface area
than the lead line pattern.
[0017] Further, the lead line pattern and the heat dissipation
pattern are placed opposite to each other with a gap therebetween,
and opposite parts of the lead line pattern and the heat
dissipation pattern respectively have interdigitated shapes and are
arranged with the respective interdigitated shapes engaging with
each other with the gap therebetween.
[0018] According to the exemplary aspect of the present invention
described above, it is possible to efficiently release heat from
the IC chip by the conductive lead line pattern that is in
conductor connection with the electrode of the IC chip. Further,
because the lead line pattern and the heat dissipation pattern are
arranged in such a way that their interdigitated shapes engage with
each other with a gap therebetween, it is possible to make the
total extension of the gap long enough and reduce the heat
resistance between the lead line pattern and the heat dissipation
pattern. It is thereby possible to reduce the heat resistance from
the IC chip to the heat dissipation pattern, thereby enhancing the
heat dissipation effect. Further, it is easy to make the total
extension of the longitudinal length of the gap longer than the
length of the short side of the IC chip.
[0019] According to the exemplary aspect of the present invention
described above, even when conductor connection cannot be made
between the electrode of the IC chip and the heat dissipation
pattern, it is possible to reduce the heat resistance between the
IC chip and the heat dissipation conductive pattern and enhance the
heat dissipation effect.
BRIEF DESCRIPTION OF THE DRAWINGS
[0020] The above and other exemplary aspects, advantages and
features will be more apparent from the following description of
certain exemplary embodiments taken in conjunction with the
accompanying drawings, in which:
[0021] FIG. 1 is a plan view schematically showing the structure of
a semiconductor device according to a first exemplary embodiment of
the invention;
[0022] FIG. 2 is a plan view schematically showing an example of
electrode layout of an IC chip included in the semiconductor device
shown in FIG. 1;
[0023] FIG. 3 is an enlarged plan view showing the vicinity of a
lead line pattern and a heat dissipation pattern included in the
semiconductor device shown in FIG. 1;
[0024] FIG. 4 is a schematic cross-sectional view along line A-A in
FIG. 3;
[0025] FIGS. 5A and 5B are a plan view and a temperature
distribution graph of a semiconductor device to describe the heat
dissipation effect of the semiconductor device shown in FIG. 1;
[0026] FIGS. 5C and 5D are a plan view and a temperature
distribution graph of a semiconductor device according to a
comparative example;
[0027] FIG. 6 is a view showing an alternative example of a lead
line pattern and a heat dissipation pattern;
[0028] FIGS. 7A to 7D are views showing alternative examples of a
lead line pattern and a heat dissipation pattern;
[0029] FIGS. 8A to 8E are views showing alternative examples of a
lead line pattern and a heat dissipation pattern;
[0030] FIGS. 9A and 9B are views showing alternative examples of a
lead line pattern and a heat dissipation pattern;
[0031] FIGS. 10A and 10B are views showing alternative examples of
a lead line pattern and a heat dissipation pattern;
[0032] FIGS. 11A and 11B are views showing alternative examples of
a lead line pattern and a heat dissipation pattern;
[0033] FIG. 12 is a plan view schematically showing the structure
of a semiconductor device according to a second exemplary
embodiment of the invention; and
[0034] FIG. 13 is an enlarged plan view showing the vicinity of a
lead line pattern and a heat dissipation pattern included in the
semiconductor device shown in FIG. 12.
DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS
[0035] Hereinafter, exemplary embodiments of the present invention
will be described in detail with reference to the appended
drawings. Note that, in the appended drawings, structural elements
that have substantially the same function and structure are denoted
with the same reference numerals, and repeated explanation of these
structural elements is omitted.
First Exemplary Embodiment
[0036] A semiconductor device according to this exemplary
embodiment is a tape carrier package (TCP) and, specifically, a TCP
that incorporates a driver IC for driving a liquid crystal display
panel. FIG. 1 is a schematic plan view of a TCP 1 according to the
exemplary embodiment. The TCP 1 includes a flexible wiring board 10
and an IC chip 11. The wiring board 10 has a structure in which a
conductive pattern is formed by copper foil or the like on a
flexible insulating film such as a polyimide film. The conductive
pattern includes an input signal line pattern 12, an output signal
line pattern 13, a lead line pattern 14 and a heat dissipation
pattern 15. Note that a plurality of sprocket holes 100 made at
regular intervals along both ends of the flexible wiring board 10
are used for carrying and positioning of a carrier tape before the
TCP 1 is cut out.
[0037] The IC chip 11 is flip-chip mounted on the principal surface
of the flexible wiring board 10 where the conductive pattern is
formed. The IC chip 11 has a plurality of first electrodes 111 that
are used for inputting and outputting power supply, display data,
control signals or the like to and from an external device (e.g. a
display controller on the input side, a liquid crystal display
panel on the output side etc.) and a plurality of second electrodes
112 that are usually not connected with an external device and
principally used for the purpose of ensuring stable connection and
dissipating heat.
[0038] FIG. 2 is a plan view showing an example of layout of the
electrodes 111 and 112 formed on the principal surface of the IC
chip 11. In the example of FIG. 2, the plurality of first
electrodes 111 are arranged along the long side of the rectangular
principal surface of the IC chip 11, and the plurality of second
electrodes 112 are arranged along the short side of the principal
surface of the IC chip 11. Each of the plurality of first
electrodes 111 is joined to the input signal line pattern 12 or the
output signal line pattern 13 by a conductor bump (Au bump, solder
bump etc.). Further, each of the plurality of second electrodes 112
is joined to the lead line pattern 14 by a conductor bump. Note
that the arrangement is just an example, and the second electrodes
112 are not necessarily arranged along the short side only but may
be arranged along the long side or arranged along the both
sides.
[0039] Referring back to FIG. 1, the input signal line pattern 12
and the output signal line pattern 13 are used for inputting and
outputting power supply, display data, control signals or the like
between the IC chip 11 and an external device (e.g. a display
controller on the input side, a liquid crystal display panel on the
output side etc.). Although not shown in FIG. 1, the input signal
line pattern 12 includes a plurality of fine input lines, and the
output signal line pattern 13 includes a plurality of fine output
lines.
[0040] The lead line pattern 14 is in conductor connection with at
least one electrode of the first electrodes 111 and the second
electrodes 112. The heat dissipation pattern 15 is physically
spaced from each of the IC chip 11, the signal line patterns 12 and
13 and the lead line pattern 14, and it has a larger surface area
than the lead line pattern 14. Further, the lead line pattern 14
and the heat dissipation pattern 15 are placed opposite to each
other with a gap therebetween. The respective parts of the lead
line pattern 14 and the heat dissipation pattern 15 which are
opposite to each other have an interdigitated shape, and they are
arranged in such a way that the respective interdigitated shapes
engage with each other with a gap therebetween. In other words, the
boundary line of the opposite parts of the lead line pattern 14 and
the heat dissipation pattern 15 has an interdigitated shape. The
shape of the boundary line may be also regarded as a corrugated,
zigzag, meandering or star-like shape.
[0041] FIG. 3 is an enlarged plan view showing the vicinity of the
lead line pattern 14 and the heat dissipation pattern 15 located on
the right side of the IC chip 11 shown in FIG. 1. In the example of
FIG. 3, the lead line pattern 14 is made up of five lead lines 141
to 145 that are separated from one another. FIG. 4 is a schematic
cross-sectional view along line A-A in FIG. 3. In FIG. 4, sealing
resin is not shown. As shown in FIG. 4, the lead line 145 is formed
on a flexible insulating film 101 and joined to the electrode 112
by a conductor bump 113. The other lead lines 141 to 144 are also
joined to the IC chip 11 by the conductor bump 113 in the same
manner as the lead line 145.
[0042] Further, as shown in FIG. 3, the lead lines 141 to 145 are
arranged to radiate out from the short side of the IC chip 11. The
radial end parts of the lead lines 141 to 145 correspond to
projecting parts of the lead line pattern 14. Further, the heat
dissipation pattern 15 is arranged to surround the end parts of the
lead lines 141 to 145 with a gap 16 therebetween. In other words,
the lead lines 141 to 145 are arranged to come inside the heat
dissipation pattern 15. Specifically, projecting parts 151 to 156
of the heat dissipation pattern 15 extend between the respective
lead lines 141 to 145, between the chip 11 and the line 141 and
between the chip 11 and the line 145.
[0043] In this manner, the opposite parts of the lead line pattern
14 (the lead lines 141 to 145) and the heat dissipation pattern 15
are designed with an interdigitated structure and arranged to
engage with each other with the gap 16 therebetween, thereby
increasing the length of the opposite parts of the pattern 14 and
the pattern 15 (i.e. the length of the boundary line or the length
of the gap 16). Because the gap 16, which is the insulating film,
has a lower heat conductivity than the patterns 14 and 15 made of a
conductor such as copper or aluminum, it causes an increase in heat
resistance at the boundary between the patterns 14 and 15. However,
by making the total extension of the longitudinal length of the gap
16 long enough, it is possible to reduce the heat resistance
between the lead line pattern 14 and the heat dissipation pattern
15. Note that it is easy to make the total extension of the
longitudinal length of the gap 16 longer than the length of the
short side of the IC chip 11. Thus, when conductor connection
cannot be made between the IC chip 11 and the heat dissipation
pattern 15, the higher heat dissipation effect can be expected in
the heat dissipation structure according to the exemplary
embodiment compared to the heat dissipation structure disclosed in
JP 2004-111996 A (the structure in which the length of the
interface between the IC chip and the heat dissipation conductive
pattern is about the length of the short side of the IC chip).
[0044] Hereinafter, the heat dissipation effect that is obtained by
the layout of the lead line pattern 14 and the heat dissipation
pattern 15 described in the exemplary embodiment is described with
reference to FIGS. 5A to 5D. FIG. 5A is a plan view where
isothermal lines L1 to L8 are added to the layout of the patterns
14 and 15 shown in FIG. 3. FIG. 5B is a graph showing a temperature
distribution along the X-axis of FIG. 5A. On the other hand, FIG.
5C is a plan view related to a comparative example in the case
where the boundary line between the patterns 14 and 15 does not
have an interdigitated shape. FIG. 5D is a graph showing a
temperature distribution along the X-axis of FIG. 5C. It should be
noted that the structure shown in FIG. 5C is designed by the
inventor of the present invention for the purpose of comparison
with the TCP 1 and it is thus not a publicly known structure.
[0045] As is obvious from comparison between FIGS. 5B and 5D,
according to the exemplary embodiment, heat is efficiently released
from the IC chip 11 to the heat dissipation pattern 15, so that the
temperature of the IC chip 11 falls and the temperature of the heat
dissipation pattern 15 rises. The temperature gradient along the
boundary P1 of the IC chip 11 thereby becomes less steep as shown
in FIG. 5B.
[0046] Because the temperature gradient near the IC chip 11, which
is a heat source, is steep in FIGS. 5C and 5D, reducing the
temperature gradient leads to efficient heat dissipation. By
forming the lead line pattern 14 so as to radically spread out from
the IC chip 11 as shown in FIGS. 1 and 3, it is possible to improve
the heat dissipation effect. This is because the radial line layout
is along the diffusion direction of heat current. By placing the
radial lead line pattern 14 along the heat current diffusion
direction in close proximity to the IC chip 11, the temperature
gradient near the IC chip 11 becomes less steep as shown in FIGS.
5A and 5B, which allows efficient heat dissipation.
[0047] Further, with use of the radial lead line pattern 14, the
total area of the lead line pattern 14 can be small. Therefore, the
radial lead line pattern 14 is particularly effective when there is
a concern about breakdown of the IC chip 11 due to ESD.
[0048] According to the exemplary embodiment, even when conductor
connection of the heat dissipation pattern 15 to the IC chip 11 is
unavailable for the countermeasure to ESD, the constraints on the
electrode layout of the IC chip 11 or the like, it is possible to
reduce the heat resistance between the IC chip 11 and the heat
dissipation pattern 15 and increase the heat dissipation effect.
Further, by making the total extension of the gap 16 long enough,
it is possible to obtain the heat dissipation effect which is equal
to when making conductor connection between the IC chip 11 and the
heat dissipation pattern 15.
[0049] Noted that the shape of the lead line pattern 14 shown in
FIGS. 1, 3 and 5 is just an example. For example, when an
electrical connection can be made, the lead line pattern 14 may
have an integral conductive pattern in which the lead lines 141 to
145 are connected at a center part 146 as shown in FIG. 6.
[0050] Alternative examples of the lead line pattern 14 are shown
in FIGS. 7A to 7D and FIGS. 8A to 8E. FIGS. 7A to 7D show
alternative examples of the lead line pattern 14 having the radial
lead lines 141 to 145. FIG. 7A is an example in which each of the
lead lines 141 to 145 shown in FIG. 3 branches off to thereby
further increase the boundary length. FIG. 7B is an example in
which each of the lead lines 141 to 145 becomes wider toward their
ends. FIGS. 7C and 7D are examples in which the end of each of the
lead lines 141 to 145 is wider than the root and each has a
corrugated rim to thereby further increase the boundary length.
[0051] FIGS. 8A to 8E show alternative examples of the lead line
pattern 14 having the non-radial lead lines 141 to 145. Although
the non-radial lead line pattern 14 is likely to be less
advantageous than the radial pattern in terms of heat current
diffusion characteristics, it is effective when it is difficult to
adopt the radial lead line pattern 14 due to layout
constraints.
[0052] Further, the heat dissipation pattern 15 may be electrically
floating or provided with a certain potential. For example, the
heat dissipation pattern 15 may be grounded. In the heat
dissipation structure according to the exemplary embodiment, the
lead line pattern 14 and the heat dissipation pattern 15 are
physically spaced from each other. Therefore, the heat dissipation
structure is applicable also when a given potential is provided to
the heat dissipation pattern 15.
[0053] Furthermore, the electrodes 112 for heat dissipation may be
connected to a power supply potential, a ground potential or the
like inside the IC chip 11. Stated differently, the lead line
pattern 14 (the lead lines 141 to 145) may be electrically
connected to an external device through an internal line of the IC
chip 11. In the heat dissipation structure according to the
exemplary embodiment, the respective lead lines 141 to 145 of the
lead line pattern 14, and the lead line pattern 14 and the heat
dissipation pattern 15 are respectively physically spaced from each
other. Therefore, the heat dissipation structure is applicable also
when a given potential is supplied to the respective lead lines 141
to 145 of the lead line pattern 14.
[0054] Although the case where the heat dissipation pattern 15 is
one island pattern is described above, the heat dissipation pattern
15 may be divided into a plurality of island patterns.
[0055] One feature of the heat dissipation structure according to
the exemplary embodiment is that the boundary line between the lead
line pattern 14 and the heat dissipation pattern 15 has an
interdigitated shape (including a corrugated, zigzag, meandering or
star-like shape). The layout is generally applicable to the part
where the lead line pattern 14 and the heat dissipation pattern 15
are arranged in close proximity to each other.
[0056] Specifically, it is more preferable that the boundary line
(L22) between the lead line pattern 14 and the heat dissipation
pattern 15 opposite to each other with a gap therebetween has an
interdigitated shape as shown in FIG. 9B, compared to that the
boundary line (L21) between the patterns 14 and 15 is a straight
line as shown in FIG. 9A. Further, when the lead line pattern 14
includes a plurality of fine lines (FIG. 10A), it is preferred to
vary the lengths of the respective fine lines and make a comb
shape, so that the boundary line (L22) between the patterns 14 and
15 has an interdigitated shape (FIG. 10B). Furthermore, when the
lead line pattern 14 and the heat dissipation pattern 15 both
include a plurality of fine lines, it is preferred to make the
respective patterns have a comb shape and engage with each other
with a gap therebetween, so that the boundary line (L22) between
the patterns 14 and 15 has an interdigitated shape (FIG. 11B).
Second Exemplary Embodiment
[0057] In this exemplary embodiment, applications of the conductive
pattern layout shown in FIGS. 9B, 10B and 11B are described. FIG.
12 is a schematic plan view of a TCP 2 according to the exemplary
embodiment. In the example of FIG. 12, dummy lines (dummy leads)
are formed in an area 21 where the signal input/output patterns 13
and 14 are not formed. It is generally practiced in a semiconductor
device such as a TCP using a flexible wiring board to form dummy
lines in an open part. The dummy lines contribute also to the heat
dissipation of the IC chip 11.
[0058] Further, in the example of FIG. 12, a folded line 24 is
formed in the area 21. The folded line 24 connects between the two
electrodes 112 which are not connected to an external device among
the electrodes of the IC chip 11 in a folded fashion. The folded
line 24 is placed for power supply, for example. When the folded
line 24 exists, the dummy lines are divided by the folded line 24.
In this exemplary embodiment, the layout of the conductive pattern
shown in FIGS. 9 to 11 is used for improving the heat conductivity
between the divided dummy lines and the folded line 24.
[0059] FIG. 13 is an enlarged plan view showing the vicinity of the
folded line 24 placed in the area 21. The folded line 24 is not
connected to an external device and in conductor connection to the
electrode 112 of the IC chip 11. Thus, the folded line 24
corresponds to the lead line pattern 14. Further, dummy lines 25
are physically spaced from each of the IC chip 11, the signal line
patterns 12 and 13 and the folded line 24 (which corresponds to the
lead line pattern 14), and it has a larger surface area than the
folded line 24. Thus, the dummy lines 25 correspond to the heat
dissipation pattern 15. Dummy lines 26 are connected to a dummy
electrode of the IC chip 11 through a conductor bump to ensure
stable connection with the flexible wiring board 10. Note that the
dummy lines 26 are not necessarily in conductor connection to the
electrode of the IC chip 11.
[0060] As shown in FIG. 13, the opposite parts of the folded line
24 (which corresponds to the lead line pattern 14) and the dummy
lines 25 (which correspond to the heat dissipation pattern 15) have
an interdigitated shape and engage with each other with a gap
therebetween, thereby reducing heat resistance. Likewise, it is
preferred that the boundary line between the dummy lines 26 and the
folded line 24 on the IC chip 11 side also has an interdigitated
shape. It is thereby possible to reduce the heat resistance from
the IC chip 11 to the dummy lines 25.
[0061] In the first and second exemplary embodiments of the present
invention, the structure in which the lead line pattern is in
conductor connection with the electrodes 112 which are placed
separately from the electrodes 111 being connected to an external
device and principally used for the purpose of ensuring stable
connection and dissipating heat without being connected to an
external device is described. However, at least one of the input
signal line pattern 12 and the output signal line pattern 13 which
are connected to the electrodes 111 being connected to an external
device may be placed opposite to the heat dissipation pattern 15
with a gap therebetween. In other words, at least one of the input
signal line pattern 12 and the output signal line pattern 13 may
serve also as the lead line pattern.
[0062] As described above, in the TCP 1 and the TCP 2, the lead
line pattern 14 and the heat dissipation pattern 15 are arranged to
engage with each other with a gap therebetween, and it is thus
possible to reduce heat resistance without making electrical
connection between the lead line pattern 14 and the heat
dissipation pattern 15. Thus, the input signal line pattern 12 and
the output signal line pattern 13 which should avoid electrical
connection with the heat dissipation pattern 15 may be used as the
lead line pattern 14. In this manner, because the signal line
patterns 12 and 13 or the like that are connected to an external
device can be used as the lead line pattern 14, the heat
dissipation structure with the lead line pattern 14 and the heat
dissipation pattern 15 has an advantage of less constraints on
layout.
[0063] Further, the heat dissipation structure of the semiconductor
device described in the above first and second exemplary
embodiments of the present invention is especially effective in a
semiconductor device using a flexible wiring board, particularly in
a TCP having a structure in which a conductive layer formed on an
insulating film is a single layer and an IC chip is flip-chip
mounted on the same principal surface as the conductive layer. This
packaging is called chip on film (COF). In the COF, there is no
need to make a hole in a part of the insulating film opposite to
the IC chip and there is no need to use a flying lead. The COF in
which the conductive layer is formed only on the principal surface
of the film and the IC chip is mounted on the principal surface is
a generally used package type for its compatibility with a fine
pitch structure and its ability to reduce the manufacturing cost of
the TCP and ensure the flexibility. On the other hand, in the TCP
having such a structure, severe layout constraints are imposed on
the conductive pattern, and the IC chip temperature is likely to
rise. However, by using the heat dissipation structure described in
the first and second exemplary embodiments, it is possible to
enhance the heat dissipation effect when conductor connection
cannot be made between the IC chip 11 and the heat dissipation
pattern 15.
[0064] However, the heat dissipation structure of the semiconductor
device described in the first and second exemplary embodiments is
also applicable to a semiconductor device that uses a flexible
wiring board different from a TCP. Further, a wiring layer
(conductive layer) of a flexible wiring board may have a
multi-layer structure. Furthermore, a conductive layer may be
formed on both principal surfaces of a flexible wiring board. In
addition, mounting of the IC chip 11 into the flexible wiring board
10 is not limited to the flip-chip mounting described above. For
example, it is applicable to tape automated bonding (TAB) mounting.
Further, the heat dissipation structure is also applicable to a
semiconductor device that uses a rigid wiring board, not limited to
a flexible wiring board.
[0065] The first and second exemplary embodiments can be combined
as desirable by one of ordinary skill in the art.
[0066] While the invention has been described in terms of several
exemplary embodiments, those skilled in the art will recognize that
the invention can be practiced with various modifications within
the spirit and scope of the appended claims and the invention is
not limited to the examples described above.
[0067] Further, the scope of the claims is not limited by the
exemplary embodiments described above.
[0068] Furthermore, it is noted that, Applicant's intent is to
encompass equivalents of all claim elements, even if amended later
during prosecution.
* * * * *