U.S. patent application number 14/536783 was filed with the patent office on 2015-05-07 for electronic device, stacked structure, and manufacturing method of the same.
This patent application is currently assigned to NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY. The applicant listed for this patent is National Institute of Advanced Industrial Science and Technology. Invention is credited to Junichi YAMAGUCHI.
Application Number | 20150123080 14/536783 |
Document ID | / |
Family ID | 49550687 |
Filed Date | 2015-05-07 |
United States Patent
Application |
20150123080 |
Kind Code |
A1 |
YAMAGUCHI; Junichi |
May 7, 2015 |
ELECTRONIC DEVICE, STACKED STRUCTURE, AND MANUFACTURING METHOD OF
THE SAME
Abstract
A stacked structure includes: an insulating substrate; a
graphene film that is formed on the insulating substrate; and a
protective film that is formed on the graphene film and is made of
a transition metal oxide, which is, for example, Cr.sub.2O.sub.3.
Thereby, at the time of transfer of the graphene, polymeric
materials such as a resist are prevented from directly coming into
contact with the graphene and nonessential carrier doping on the
graphene caused by a polymeric residue of the resist is
suppressed.
Inventors: |
YAMAGUCHI; Junichi;
(Tsukuba-shi, JP) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
National Institute of Advanced Industrial Science and
Technology |
Tokyo |
|
JP |
|
|
Assignee: |
NATIONAL INSTITUTE OF ADVANCED
INDUSTRIAL SCIENCE AND TECHNOLOGY
Tokyo
JP
|
Family ID: |
49550687 |
Appl. No.: |
14/536783 |
Filed: |
November 10, 2014 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
PCT/JP2013/062657 |
Apr 30, 2013 |
|
|
|
14536783 |
|
|
|
|
Current U.S.
Class: |
257/29 ;
438/478 |
Current CPC
Class: |
H01L 21/02636 20130101;
H01L 29/1606 20130101; H01L 29/66431 20130101; H01L 51/0558
20130101; H01L 21/02502 20130101; H01L 21/02664 20130101; H01L
29/42368 20130101; H01L 29/78696 20130101; H01L 29/4908 20130101;
H01L 21/02527 20130101; H01L 21/02491 20130101; H01L 29/78684
20130101; H01L 21/02381 20130101; H01L 21/02488 20130101; H01L
29/78603 20130101; H01L 29/78606 20130101; H01L 21/02439 20130101;
H01L 21/0262 20130101; H01L 29/517 20130101; H01L 51/0533 20130101;
H01L 29/7781 20130101; H01L 51/0045 20130101; H01L 21/7806
20130101; H01L 29/66742 20130101; H01L 29/42376 20130101; B82Y
10/00 20130101 |
Class at
Publication: |
257/29 ;
438/478 |
International
Class: |
H01L 29/51 20060101
H01L029/51; H01L 29/786 20060101 H01L029/786; H01L 21/02 20060101
H01L021/02; H01L 29/16 20060101 H01L029/16 |
Foreign Application Data
Date |
Code |
Application Number |
May 10, 2012 |
JP |
2012-108730 |
Claims
1. An electronic device, comprising: a substrate a graphene film
that is formed on the substrate; a protective film that is formed
on the graphene film and is made of a transition metal oxide; an
insulating layer that is formed on the protective film; and an
electrode that is formed on the insulating layer.
2. The electronic device according to claim 1, wherein the
insulating layer is made of a high dielectric constant
material.
3. The electronic device according to claim 2, wherein the
insulating layer has a thickness being a value falling within a
range of 5 nm to 10 nm.
4. The electronic device according to claim 1, wherein a transition
metal constituting the transition metal oxide of the protective
film is one type selected from Sc, Cr, Mn, Co, Zn, Y, Zr, Mo, and
Ru.
5. A manufacturing method of a stacked structure, comprising:
forming a catalyst on a growth substrate; forming a graphene film
on the growth substrate by using the catalyst; forming, on the
graphene film, a protective film made of a transition metal oxide;
and peeling the graphene film and the protective film off the
growth substrate and transferring the graphene film and the
protective film onto a substrate.
6. the manufacturing method of the stacked structure according to
claim 5, wherein a transition metal constituting the transition
metal oxide of the protective film is one type selected from Sc,
Cr, Mn, Co, Zn, Y, Zr, Mo, and Ru.
7. A stacked structure, comprising: a substrate; a graphene film
that is formed on the substrate; and a protective film that is
formed on the graphene film and is made of a transition metal
oxide.
8. The stacked structure according to a claim 7, wherein a
transition metal constituting the transition metal oxide of the
protective film is one type selected from Sc, Cr, Mn, Co, Zn, Y,
Zr, Mo, and Ru.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is a continuation application of
International Application PCT/JP2013/062657 filed on Apr. 30, 2013
and designated the U.S., which claims the benefit of priority of
the prior Japanese Patent Application No. 2012-108730, filed on May
10, 2012, the entire contents of which are incorporated herein by
reference.
FIELD
[0002] The embodiments discussed herein are directed to an
electronic device and a stacked structure that use graphene, and a
manufacturing method of the same.
BACKGROUND
[0003] When a graphene sheet formed by a chemical vapor deposition
method (CVD method) or a thermal decomposition treatment method of
a SiC substrate is used for an electronic device such as a
transistor, a process of transferring graphene onto an insulating
substrate from a growth substrate is needed. For example, in Patent
Document 1, the following transfer process has been disclosed. On a
graphene formed on a catalyst layer by a CVD method, a protective
film of polymethyl methacrylate (PMMA), a photoresist, an
electron-beam resist, and the like is formed, and then a support
layer made of an acrylic resin, an epoxy resin, a thermal release
tape, an adhesive tape, and the like is formed. Next, there is
taken a method in which among the support layer, the protective
film, the graphene film, and the catalyst layer, the catalyst layer
is wet etched, and thereby the support layer, the protective film,
and the graphene film are peeled off a growth substrate to be
transferred onto another insulating substrate, and then the support
layer and the protective film, are removed. On the other hand, in
Patent Documents 2 and 3, there is disclosed a manufacturing
technique of a field-effect transistor using graphene for a channel
layer of the transistor and using a high dielectric constant
material (high-k material) for a gate insulating layer.
[0004] Patent Document 1: Japanese Laid-open Patent Publication No.
2011-105590
[0005] Patent Document 2: Japanese Laid-open Patent Publication No.
2011-175996
[0006] Patent Document 3: Japanese Laid-open Patent Publication No.
2011-114299
[0007] In a transfer process of graphene that has been widely used
generally, as a protective film for graphene to be used at the time
of transfer, various resists constituted by polymeric materials are
used. However, there is a concern that the polymeric materials
remain on the graphene as a residue even after a removal process,
and when a polymeric residue is adsorbed to an edge portion and a
local defect portion of the graphene in particular, removal of the
residue is conceived to be very difficult. The polymeric residue
causes nonessential carrier doping on the graphene. Therefore, in
the graphene transistor using graphene for a channel, for example,
deterioration of electrical conduction property and unstable
operation are caused.
[0008] Further, for efficiently controlling carrier concentration
of the graphene transistor, a larger gate capacitance is needed, so
that a high dielectric constant material (high-k material) such as
HfO.sub.2 is used as a gate insulating layer. However, it is
difficult to directly form a thin film of the high-k material on
graphene, and the gate insulating layer of the high-k material
needs to be formed thickly in some degree. As the film thickness of
the gate insulating layer increases, the gate capacitance
decreases, so that thinning of the gate insulating layer of the
high-k material is desired. Further, also from a viewpoint of
low-voltage operation of the transistor, thinning of the gate
insulating layer of the high-k material is requested.
SUMMARY
[0009] An electronic device of the embodiment includes: a
substrate; a graphene film that is formed on the substrate; a
protective film that is formed on the graphene film and is made of
a transition metal oxide; an insulating layer that is formed on the
protective film; and an electrode that is formed on the insulating
layer.
[0010] A manufacturing method of a stacked structure of the
embodiment includes: forming a catalyst on a growth substrate;
forming a graphene film on the growth substrate by using the
catalyst; forming, on the graphene film, a protective film made of
a transition metal oxide; and peeling the graphene film and the
protective film off the growth substrate and transferring the
graphene film and the protective film onto a substrate.
[0011] A stacked structure of the embodiment includes: a substrate;
a graphene film that is formed on the substrate; and a protective
film that is formed on the graphene film and is made of a
transition metal oxide.
[0012] The object and advantages of the invention will be realized
and attained by means of the elements and combinations particularly
pointed out in the claims.
[0013] It is to be understood that both the foregoing general
description and the following detailed description are exemplary
and explanatory and are not restrictive of the invention.
BRIEF DESCRIPTION OF DRAWINGS
[0014] FIG. 1A is a schematic cross-sectional view illustrating a
manufacturing method of a stacked structure according to a first
embodiment;
[0015] FIG. 1B is, subsequent to FIG. 1A, a schematic
cross-sectional view illustrating the manufacturing method of the
stacked structure according to the first embodiment;
[0016] FIG. 1C is, subsequent to FIG. 1B, a schematic
cross-sectional view illustrating the manufacturing method of the
stacked structure according to the first embodiment;
[0017] FIG. 2A is, subsequent to FIG. 1C, a schematic
cross-sectional view illustrating the manufacturing method of the
stacked structure according to the first embodiment;
[0018] FIG. 2B is, subsequent to FIG. 2A, a schematic
cross-sectional view illustrating the manufacturing method of the
stacked structure according to the first embodiment;
[0019] FIG. 2C is, subsequent to FIG. 2B, a schematic
cross-sectional, view illustrating the manufacturing method of the
stacked structure according to the first embodiment;
[0020] FIG. 3A is a schematic cross-sectional view illustrating a
main step of a manufacturing method of a graphene transistor
according to a second embodiment;
[0021] FIG. 3B is, subsequent to FIG. 3A, a schematic
cross-sectional view illustrating the main step of the
manufacturing method of the graphene transistor according to the
second embodiment;
[0022] FIG. 3C is, subsequent to FIG. 3B, a schematic
cross-sectional view illustrating the main step of the
manufacturing method of the graphene transistor according to the
second embodiment;
[0023] FIG. 4A is, subsequent to FIG. 3C, a schematic
cross-sectional view illustrating the main step of the
manufacturing method of the graphene transistor according to the
second embodiment; and
[0024] FIG. 4B is, subsequent to FIG. 4A, a schematic
cross-sectional view illustrating the main step of the
manufacturing method of the graphene transistor according to the
second embodiment.
DESCRIPTION OF EMBODIMENT
[0025] Hereinafter, there will be explained preferred various
embodiments having the embodiments applied thereto in detail with
reference to the drawings.
First Embodiment
[0026] In this embodiment, there will be explained a stacked
structure using graphene together with a manufacturing method of
the same. FIG. 1A to FIG. 2C are schematic cross-sectional views
illustrating a manufacturing method of a stacked structure
according to a first embodiment in order of steps.
[0027] First, as illustrated in FIG. 1A, on a growth substrate 11,
a catalyst layer 12 is deposited by using a sputtering method.
[0028] For the growth substrate 11, a Si substrate having a
thermally-oxidized film having a film thickness of 100 nm to 300 nm
or so formed thereon is used. For the catalyst layer 12, Cu having
a film thickness of 500 nm to 1 .mu.m or so is used. Besides Cu, a
metal material containing one type of Fe, Co, Ni, Ru, and Pt can
also be used as the catalyst layer.
[0029] Subsequently, as illustrated in FIG. 1B, a graphene film 13
is formed by using the catalyst layer 12.
[0030] By using a CVD method, the catalyst layer 12 and the growth
substrate 11 are heat-treated at about 300.degree. C. in a hydrogen
(H.sub.2) atmosphere diluted with Ar, and in a state of maintaining
the same temperature, CH.sub.4 is introduced as a source gas.
Thereby, the graphene film 13 is formed. Here, the graphene film 13
is formed into a single layer or two layers. As the source gas,
besides CH.sub.4, C.sub.2H.sub.2, C.sub.2H.sub.4, CO each
containing C, or the like can be used.
[0031] Subsequently, as illustrated in FIG. 1C, a protective film
14 made of a transition metal oxide is formed on the graphene film
13.
[0032] By using an electron-beam deposition method, a transition
metal is deposited on the graphene film 13 to have a thickness of 1
nm to 5 nm or so to form a transition metal film. The transition
metal film on the graphene film 13 is naturally oxidized by being
exposed to the atmosphere, or is oxidized by performing a
low-temperature heat treatment (at 200.degree. C. to 300.degree. C.
or so) in an oxygen atmosphere, and thereby the protective film 14
is formed.
[0033] Besides, as a method of directly forming the protective film
14 of the transition metal oxide on the graphene film 13, an atomic
layer deposition method (ALD method), a sputtering method, a pulse
laser deposition method (PLD method), or the like can also be used.
The transition metal material needs to have both a physical
property in which it is oxidized easily and a physical property in
which it is not easily chemically bonded with C constituting
graphene, namely it does not easily become carbide. For the
transition metal (oxide; material, for example,
Sc(Sc.sub.2O.sub.3), Cr(Cr.sub.2O.sub.3), Mn(MnO.sub.2), Co(CoO),
Zn(ZnO), Y(Y.sub.2O.sub.3), Zr(ZrO.sub.2), Mo(MoO.sub.3), and
Ru(RuO.sub.2) can be used.
[0034] In this embodiment, Cr.sub.2O.sub.3 obtained after Cr is
deposited on the graphene film 13 by an electron-beam deposition
method and then is naturally oxidized is used for the protective
film 14. Ti is well known to be easily oxidized to become
TiO.sub.2, but when Ti is deposited on graphene, TiCx is formed on
an interface between Ti and graphene to destroy crystallinity of
the graphene. Therefore, TiO.sub.2 is not useful as the material of
the protective film.
[0035] Subsequently, as illustrated in FIG. 2A, on the protective
film 14, an adhesive layer 15 and a support layer 16 are
sequentially formed.
[0036] On the protective film 14, a photoresist having a thickness
of 1 .mu.m to 2 .mu.m or so and an acrylic resin having a thickness
of 100 .mu.m to 500 .mu.m or so are sequentially spin-coated.
Thereby, the adhesive layer 15 and the support layer 16 are formed
on the protective film 14. For the adhesive layer 15, besides the
photoresist, PMMA, an electron beam resist, or the like may also be
used. Further, for the support layer 16, besides the acrylic resin,
an epoxy resin, a thermal, release tape, an adhesive tape, or the
like can also be used.
[0037] Subsequently, the thermally-oxidized film on the growth
substrate 11 is wet-etched by using BHF, and the catalyst layer 12,
the graphene film 13, the protective film 14, the adhesive layer
15, and the support layer 16 are integrally peeled off the growth
substrate 11.
[0038] Subsequently, among the catalyst layer 12, the graphene film
13, the protective film 14, the adhesive layer 15, and the support
layer 16 peeled off the growth substrate 11, the catalyst layer 12
is wet-etched to be removed. For an etchant, a FeCl.sub.3 aqueous
solution or dilute HCl is used. For the removal of the catalyst
layer 12, besides the wet etching, dry etching such as reactive ion
etching or ion milling can also be used. The graphene film 13, the
protective film 14, the adhesive layer 15, and the support layer 16
obtained after the removal of the catalyst layer 12 are subjected
to rinsing by using a pure water.
[0039] Subsequently, as illustrated in FIG. 2B, the graphene film
13, the protective film 14, the adhesive layer 15, and the support
layer 16 are transferred onto an insulating substrate 17.
[0040] The rinsed graphene film 13, protective film 1A, adhesive
layer 15, and support layer 16 are transferred onto the surface of
the insulating substrate 17 in the orientation in which the
graphene film 13 comes into contact with the insulating substrate
17 being a transfer destination. Thereafter, a uniform stress is
applied from the upper surface of the support layer 16 toward the
insulating substrate 17, and thereby adhesiveness between the
graphene film 13 and the insulating substrate 17 is increased. For
the insulating substrate 17 being a transfer destination, a Si
substrate having a thermally-oxidized film having a thickness of 90
nm or so formed thereon is used. This thermally-oxidized film has
an insulating function. The insulating substrate 17 needs to have
surface flatness but does not have restrictions on material and the
like, in particular, and for example, a sapphire substrate, a
quartz substrate, a MgO substrate, a PET substrate, or the like can
also be used.
[0041] Subsequently, as illustrated in FIG. 2C, a stacked structure
having the graphene film 13 and the protective film 14 on the
insulating substrate 17 is formed.
[0042] After the transfer onto the insulating substrate 17, the
adhesive layer 15 and the support layer 16 among the graphene film
13, the protective film 14, the adhesive layer 15, and the support
layer 16 are removed. When an acrylic resin is used for the support
layer 16 and a photoresist is used for the adhesive layer 15, they
are immersed in an acetone having a temperature of about 70.degree.
C. to be removed and rinsing is performed by using an isopropyl
alcohol or ethanol. In the above manner, the stacked structure
having the graphene film 13 and the protective film 14 on the
insulating substrate 17 is formed.
[0043] As explained above, according to this embodiment, there is
fabricated a highly reliable stacked structure in which at the time
of transfer of the graphene film 13, polymeric materials such as
the resist are prevented from directly coming into contact with the
graphene film 13, nonessential carrier doping on the graphene film
13 caused by a polymeric residue of the resist, is suppressed, and
the graphene film 13 is provided.
Second Embodiment
[0044] In this embodiment, as an electronic device using the
stacked structure according to the first embodiment, a graphene
transistor is described as an example and its constitution is
explained together with its manufacturing method. FIG. 3A to FIG.
4B are schematic cross-sectional views sequentially illustrating a
main step of a manufacturing method of a graphene transistor
according to a second embodiment.
[0045] The stacked structure having the graphene film 13 and the
protective film 14 on the insulating substrate 17 according to the
first embodiment is prepared. As illustrated in FIG. 3A, the
graphene film 13 and the protective film 14 of the stacked
structure are worked to a desired channel size of the
transistor.
[0046] Concretely, by using electron-beam lithography, an
electron-beam resist is patterned into a desired channel size, and
by using the electron-beam resist as a mask, the graphene film 13
and the protective film 14 are etched. On the protective film 14 of
Cr.sub.2O.sub.3, wet etching is performed by using ceric ammonium
nitrate or a mixed aqueous solution of HNO.sub.3 and HCl heated to
about 50.degree. C. or so as an etchant. Thereafter, on the
graphene film 13, dry etching is performed by O.sub.2 plasma. The
channel size is set to 100 nm to 1 .mu.m or so in width and 1 .mu.m
to 5 .mu.m or so in length.
[0047] Subsequently, as illustrated in FIG. 3B, the protective film
14 is etched to form electrode formation portions 14a and 14b.
[0048] Both end portions of the protective film 14 are etched to
form the electrode formation portions 14a and 14b. The graphene
film 13 is exposed, from the electrode formation portions 14a and
14b, a source electrode and a drain electrode to be described later
electrically come into contact with exposed portions of the
graphene film 13, and contact resistance decreases.
[0049] Subsequently, as illustrated in FIG. 3C, a source electrode
21 and a drain electrode 22 are formed.
[0050] By electron-beam lithography, a resist mask opening regions
containing the electrode formation portions 14a and 14b is formed
on the protective film 14, and an electrode metal of Pd, for
example, is deposited, to have a thickness of 50 nm or so. By
liftoff, the resist mask and the Pd thereon are removed. Thereby,
the source electrode 21 and the drain electrode 22 electrically
connected to the exposed portions, of the graphene film 13, being
the electrode formation portions 14a and 14b, are formed. As
another electrode material, a single-layer electrode of Cr, Ni, or
Pt, or a two-layer electrode of Au and Ti or the like can also be
used. Further, a film-forming method of the electrode is not also
restricted in particular, and besides the deposition method, a PLD
method, a sputtering method, or the like can also be used.
[0051] Subsequently, as illustrated in FIG. 4A, a gate insulating
layer 23 made of a high dielectric constant material (high-k
material) is formed on the protective film 14.
[0052] By using an ALD method, on the protective film 14, a high-k
material, which is HfO.sub.2 here, is deposited to have a thickness
of 5 nm to 50 nm or so, which is preferably 5 nm to 10 nm or so and
is 5 nm or so here. Thereby, the gate insulating layer 23 is formed
on the protective film 14.
[0053] It has been said that it is difficult to directly form a
thin film of the high-k material on graphene. In this embodiment,
on the graphene film 13, the protective film 14 made of the
transition metal oxide is formed, and on the protective film 14,
the gate insulating layer 23 is formed. Therefore, thinning of the
gate insulating layer 23 is enabled. That is, the protective film
14 not only has a function of protecting the graphene film 13 at
the time of a transfer process, but also functions as a seed layer
used for thinly forming the gate insulating layer 23 made of the
high-k material. As the high-k material, besides the above,
Al.sub.2O.sub.3, Si.sub.3N.sub.4, HfSiO, HfAlON, Y.sub.2O.sub.3,
SrTiO.sub.3, PbZrTiO.sub.3, BaTiO.sub.3, or the like can be used.
Further, with regard also to the film-forming method, a CVD method,
a deposition method, an ALD method, a PLD method, a sputtering
method, or the like can be selected appropriately according to the
type of the high-k material.
[0054] Subsequently, as illustrated in FIG. 4B, a gate electrode 24
is formed on the gate insulating layer 23.
[0055] By the forming method similar to that of the source
electrode 21 and the drain electrode 22, the gate electrode 24 made
of Pd is formed on the gate insulating layer 23 to have a thickness
of 50 nm or so. By the above method, the top-gate type graphene
transistor is obtained.
[0056] According to this embodiment, the stacked structure obtained
in the first embodiment is used to constitute the graphene
transistor, to thereby obtain a highly reliable graphene transistor
whose improvement in electrical property and stable operation are
achieved. Further, in the graphene transistor, the protective film
14 that is formed on the graphene film 13 and is made of the
transition metal oxide functions as a seed layer of the gate
insulating layer 23 of the high-k material, thinning of the gate
insulating layer 23 is enabled, and improvement in control
efficiency of carrier concentration of the graphene film 13 and
low-voltage operation are achieved.
[0057] Incidentally, in this embodiment, as the electronic device
using the stacked structure according to the first embodiment, the
graphene transistor has been described as an example, but the
embodiment is not limited to this. The embodiment is applicable to,
for example, a display using the stacked structure for a display
electrode, and the like.
[0058] According to the embodiments, there is fabricated a stacked
structure in which at the time of transfer of graphene, polymeric
materials such as a resist are prevented from directly coming into
contact with the graphene and nonessential carrier doping on the
graphene caused by a polymeric residue of the resist is
suppressed.
[0059] According to the embodiments, an electronic device is
constituted by the above-described stacked structure, to thereby
obtain a highly reliable electronic device whose improvement in
electrical property and stable operation are achieved. Further, in
the above-described electronic device, the protective film that is
formed on the graphene film and is made of the transition metal
oxide functions as a seed layer of the gate insulating layer of the
high-k material, thinning of the gate insulating layer of the
high-k material is enabled, and improvement in control efficiency
of carrier concentration of the graphene film and low-voltage
operation are achieved.
[0060] All examples and conditional language provided herein are
intended for the pedagogical purposes of aiding the reader in
understanding the invention and the concepts contributed by the
inventor to further the art, and are not to be construed as
limitations to such specifically recited examples and conditions,
nor does the organization of such examples in the specification
relate to a showing of the superiority and inferiority of the
invention. Although one or more embodiments of the present
invention have been described in detail, it should be understood
that the various changes, substitutions, and alterations could be
made hereto without departing from the spirit and scope of the
invention.
* * * * *