U.S. patent application number 14/229612 was filed with the patent office on 2015-04-30 for semiconductor device and method for fabricating the same.
This patent application is currently assigned to SK HYNIX INC.. The applicant listed for this patent is SK HYNIX INC.. Invention is credited to Woong CHOI, Yun Seok CHUN, Young Bog KIM, Woo Jun LEE, Jae Man YOON.
Application Number | 20150115392 14/229612 |
Document ID | / |
Family ID | 52994439 |
Filed Date | 2015-04-30 |
United States Patent
Application |
20150115392 |
Kind Code |
A1 |
YOON; Jae Man ; et
al. |
April 30, 2015 |
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
Abstract
A semiconductor device includes a bit line disposed over a
semiconductor substrate, a supporting film being perpendicular to
the bit line, a first storage node contact disposed at a lower part
of a region disposed between the bit line and the supporting film,
and a second storage node contact having a line shape, disposed
over the first storage node contact and the bit line, isolated by
the supporting film, and patterned in a diagonal direction across
the bit line.
Inventors: |
YOON; Jae Man; (Seoul,
KR) ; KIM; Young Bog; (Yongin, KR) ; CHUN; Yun
Seok; (Seongnam, KR) ; CHOI; Woong; (Seoul,
KR) ; LEE; Woo Jun; (Icheon, KR) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
SK HYNIX INC. |
Icheon |
|
KR |
|
|
Assignee: |
SK HYNIX INC.
Icheon
KR
|
Family ID: |
52994439 |
Appl. No.: |
14/229612 |
Filed: |
March 28, 2014 |
Current U.S.
Class: |
257/499 |
Current CPC
Class: |
H01L 27/10894 20130101;
H01L 21/28525 20130101; H01L 27/1085 20130101; H01L 21/02282
20130101; H01L 21/31144 20130101; H01L 21/768 20130101; H01L
27/10855 20130101; H01L 27/0207 20130101; H01L 27/10814 20130101;
H01L 27/10823 20130101; H01L 27/10885 20130101 |
Class at
Publication: |
257/499 |
International
Class: |
H01L 29/41 20060101
H01L029/41; H01L 27/02 20060101 H01L027/02; H01L 23/48 20060101
H01L023/48 |
Foreign Application Data
Date |
Code |
Application Number |
Oct 28, 2013 |
KR |
10-2013-0128665 |
Claims
1. A semiconductor device comprising: a bit line disposed over a
semiconductor substrate; a supporting film perpendicular to the bit
line and partially covering a top surface of the bit line; a first
storage node contact disposed at a lower part of a region disposed
between the bit line and the supporting film; and a second storage
node contact having a line shape, disposed over the first storage
node contact and the bit line, isolated by the supporting film, and
patterned to extend diagonally across the bit line.
2. The semiconductor device according to claim 1, wherein the
supporting film is patterned when the second storage node contact
is patterned in a diagonal direction, such that an upper portion of
the supporting film is alternately arranged with the second storage
node contact in the diagonal direction.
3. The semiconductor device according to claim 1, wherein the
patterned second storage node contact has a first top surface and a
second top surface that have a step difference therebetween.
4. The semiconductor device according to claim 3, wherein the first
top surface is located at a higher level than the top surface of
the bit line, and the second top surface is located at a lower
level than the top surface of the bit line.
5. The semiconductor device according to claim 2, wherein the
patterned supporting film has a first top surface and a second top
surface that have step difference therebetween.
6. The semiconductor device according to claim 5, wherein the first
top surface is located over the bit line, and the second top
surface is located at substantially the same level as the top
surface of the bit line or located below the top surface of the bit
line.
7. The semiconductor device according to claim 5, wherein the first
top surface is located at a higher level than the top surface of
the bit line, and the second top surface is located at a higher
level than a top surface of the first storage node contact.
8. The semiconductor device according to claim 4, wherein an area
of the first top surface of the second storage node contact is
smaller than an area of a top surface of the first storage node
contact.
9. A semiconductor device comprising: first and second bit lines
spaced apart from each other by a first distance over a
semiconductor substrate; first and second supporting films
perpendicular to the first and second bit lines, spaced apart from
each other by a second distance, and having a line shape to
partially cover the first and second bit lines; and first and
second storage node contacts that are self-aligned and deposited
between the first and second supporting films.
10. The semiconductor device according to claim 9, wherein the
first storage node contact has an island type over the
semiconductor substrate and is disposed among the first and second
bit lines and the first and second supporting films.
11. The semiconductor device according to claim 10, wherein the
second storage node contact has a line shape and is disposed over
the first storage node contact and the first and second bit
lines.
12. The semiconductor device according to claim 11, wherein the
second storage node contact is disposed between the first and
second supporting films.
13. The semiconductor device according to claim 9, further
comprising: a storage node disposed over the second storage node
contact.
14. The semiconductor device according to claim 9, wherein an area
of a top surface of the second storage node contact is smaller than
an area of a top surface of the first storage node contact.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] The priority of Korean patent application No.
10-2013-0128665 filed on 28 Oct. 2013, the disclosure of which is
hereby incorporated by reference in its entirety, is claimed.
BACKGROUND
[0002] The present invention relates to a semiconductor device and
a method for fabricating the same, and more particularly to a
technology for forming a storage node contact.
[0003] A semiconductor is a material having electrical
characteristics between that of a conductor and a nonconductor. A
semiconductor is used to form a semiconductor device such as a
transistor through impurity implantation and conductor
connection.
[0004] As the degree of integration of the semiconductor device
increases, the size of the semiconductor device is gradually
reduced and thus the size of a semiconductor chip including a
plurality of semiconductor devices is also gradually reduced.
[0005] As the size of a semiconductor device is gradually reduced,
a contact margin between a storage node and a storage node contact
disposed below the storage node is also reduced.
SUMMARY
[0006] Embodiments of the present invention are directed to a
semiconductor device and a method for fabricating the same, which
substantially obviate one or more problems due to limitations and
disadvantages of the related art.
[0007] Embodiments of the present invention relate to a
semiconductor device and a method for fabricating the same, which
simplify a process for forming storage node contact. Embodiments of
the present invention relate to a semiconductor device and a method
for fabricating the same, which facilitate self-alignment of the
storage node contact.
[0008] In accordance with an aspect of the embodiment, a
semiconductor device includes: a bit line formed over a
semiconductor substrate; a supporting film perpendicular to the bit
line and partially covering a top surface of the bit line; a first
storage node contact formed at a lower part of a region disposed
between the bit line and the supporting film; and a second storage
node contact formed in a line shape over the first storage node
contact and the bit line, isolated by the supporting film, and
patterned to extend diagonally across the bit line.
[0009] In accordance with another aspect of the embodiment, a
semiconductor device includes: first and second bit lines spaced
apart from each other by a first distance over a semiconductor
substrate; first and second supporting films perpendicular to the
first and second bit lines, spaced apart from each other by a
second distance, and formed in a line shape to partially cover the
first and second bit lines; and first and second storage node
contacts that are self-aligned and deposited between the first and
second supporting films.
[0010] In accordance with another aspect of the embodiment, a
method for forming a semiconductor device includes: forming first
and second bit lines spaced apart from each other by a first
distance over a semiconductor substrate; forming first and second
supporting films spaced apart from each other by a second distance
in a direction perpendicular to the first and second bit lines,
wherein top surfaces of the first and second supporting films are
located at higher levels than top surfaces of the first and second
bit lines; forming a first storage node contact and a second
storage node contact between the first supporting film and the
second supporting film; and patterning upper portions of the second
storage node contact and the first and second supporting films in a
diagonal direction across the bit line.
[0011] The forming the first and second supporting films includes:
forming an interlayer insulation film to fill a space between the
first bit line and the second bit line; forming a capping film over
the first and second bit lines and the interlayer insulation film;
forming first and second holes spaced apart from each other by the
second distance in a direction perpendicular to the first and
second bit lines; forming the first supporting film and the second
supporting film by filling the first hole and the second hole with
an insulation material; and removing the interlayer insulation film
and the capping film.
[0012] In the forming of the first and second supporting film, the
first hole and the second hole are formed in a cell region using a
cell-opening mask.
[0013] The forming the first and second storage node contacts
includes: forming the first storage node contact at a lower part of
a region surrounded by the first and second supporting films and
the first and second bit lines; and forming the second storage node
contact over the first storage node contact and the first and
second bit lines.
[0014] A top surface of the second storage node contact is located
at substantially the same level as the top surfaces of the first
and second supporting films or located below the top surfaces of
the first and second supporting films.
[0015] The first storage node contact is formed of a polysilicon
material, and the second storage node contact is formed of a metal
material.
[0016] The patterning includes: patterning the second storage node
using a Spacer Patterning Technology (SPT) or a Double Patterning
Technology (DPT).
[0017] The patterning includes: sequentially depositing a first
interlayer insulation film, a first etch stop film, a second
interlayer insulation film, and a second etch stop film over the
second storage node contact; forming first patterns by etching the
second etch stop film and the second interlayer insulation film;
depositing a spacer material along a step difference of the first
patterns; depositing a Spin On Carbon (SOC) material in a space
disposed between the first patterns on which the spacer material is
deposited; forming second patterns by etching the spacer material
and the first etch stop film; forming third patterns by etching the
first interlayer insulation film using the second patterns as a
mask; and patterning the upper portion of the second storage node
contact using the third patterns as a mask.
[0018] A distance between the first patterns is at least two times
greater than a distance between the second patterns.
[0019] It is to be understood that both the foregoing general
description and the following detailed description of embodiments
are intended to provide further explanation of the invention as
claimed.
BRIEF DESCRIPTION OF THE DRAWINGS
[0020] FIG. 1(i) shows a perspective view of a semiconductor device
according to an embodiment. FIGS. 1(ii) and 1(iii) are
cross-sectional views of a semiconductor device according to an
embodiment taken along line X-X' and Y-Y' of FIG. 1(i),
respectively.
[0021] FIG. 2 is a perspective view illustrating a storage node
according to an embodiment.
[0022] FIGS. 3A to 3N are views illustrating a method for forming a
semiconductor device according to an embodiment. For each of FIGS.
3A to 3N, (i) shows a perspective view of the semiconductor device,
(ii) shows a cross-sectional view taken along line X-X' of view
(i), and (iii) shows a cross-sectional view taken along line Y-Y'
of view (i).
[0023] FIG. 4 is a block diagram illustrating a memory system
including a semiconductor device according to an embodiment.
DESCRIPTION OF EMBODIMENTS
[0024] Reference will now be made in detail to embodiments of the
present invention, examples of which are illustrated in the
accompanying drawings. Wherever possible, the same reference
numbers are used throughout the drawings to refer to the same or
like portions. In the following description, a detailed description
of related known configurations or functions incorporated herein
may be omitted for clarity of the subject matter of the present
disclosure.
[0025] An embodiment relates to a storage node contact in which
storage nodes may be arranged, for example, in a zigzag pattern or
other pattern to increase a cell capacity. When forming a storage
node to be directly aligned with a storage node contact, a process
margin between the storage node and the storage node contact may be
deteriorated. To improve the process margin, the storage node
contact is formed through two processing steps.
[0026] However, in order to form the storage node contact through
two processing steps, a mask process for forming a second storage
node contact should be performed after a first storage node contact
is formed.
[0027] An embodiment is directed to a method for forming a
semiconductor device including a storage node contact. In a method
in accordance with an embodiment, when forming the storage node
contact through two processing steps, a second storage node contact
is formed using a supporting film without using an additional mask
after a first storage node contact is formed. As a result, a
fabrication method can be simplified, and self-alignment of the
storage node contact can be facilitated using the supporting
film.
[0028] FIG. 1 shows a perspective view and cross-sectional views
illustrating a semiconductor device according to an embodiment.
[0029] In FIG. 1, (i) illustrates a perspective view of the
semiconductor device, (ii) illustrates a cross-sectional view of
the semiconductor device taken along a line X-X' in FIG. 1(i), and
(iii) illustrates a cross-sectional view of the semiconductor
device taken along a line Y-Y' in FIG. 1(i).
[0030] Referring to FIG. 1(i), the semiconductor device includes a
bit line 210 arranged in a first direction on a semiconductor
substrate 101, a gate (not shown) buried along a direction
perpendicular to the bit line 210, a supporting film 217 formed
over the semiconductor substrate 101 along a direction
perpendicular to the bit line 210, and a storage node contact
including a first storage node contact 221 and a second storage
node contact 223 that are deposited between the bit line 210 and
the supporting film 217 located adjacent to the bit line 210. The
bit line 210 includes a polysilicon layer 201, a bit-line metal
layer 203, a bit-line hard mask layer 205, and a spacer 207 formed
at sidewalls of the layers 201, 203, and 205.
[0031] The first storage node contact 221 is formed at a lower part
of a region disposed between the supporting film 217 and the bit
line 210. The second storage node contact 223 is formed over the
first storage node contact 221. The second storage node contact 223
crosses the bit line 210 diagonally and has a first top surface 247
and a second top surface 249 that have a step difference
therebetween. In an embodiment, the first top surface 247 is
located above a top surface 255 of the bit line 210, and the second
top surface 249 is located below the top surface 255 of the bit
line 210.
[0032] The supporting film 217 insulates the first storage node
contacts 221 from each other or the second storage node contacts
223 from each other or both. Upper portions of the supporting film
217 and the second storage node contact 223 are etched to form line
patterns that extend diagonally across the bit line 210. The line
patterns include line-shaped trenches, i.e., elongated trenches
extending lengthwise along a line, separated by line-shaped pillars
comprised of alternating upper portions of the supporting film 217
and the second storage node contacts 223. These line patterns are
provided over the bit lines 210 to cross the bit lines 210
diagonally.
[0033] Thus, the supporting film 217 also has a first top surface
251 and a second top surface 253 with a step difference
therebetween. The first top surface 251 is formed over the top
surface 255 of the bit line 210. The second top surface 253 may be
formed at the same level as the top surface 255 of the bit line
210, or may be formed below the top surface 255 of the bit line
210. The second top surface 253 of the supporting film 217 may be
located at a higher level than a top surface of the first storage
node contact 221.
[0034] In another embodiment, the top surface 247 of the second
storage node contact 223 is located at substantially the same level
as the top surface 251 of the supporting film 217 or located below
the top surface 251 of the supporting film 217.
[0035] A detailed configuration of a lower structure 110 is shown
in the cross-sectional views FIG. 1(ii) and FIG. 1(iii). The lower
structure 110 includes an active region 103 defined by a device
isolation film 102 formed in the semiconductor substrate 101, and a
bit line contact 105 coupled to the bit line 210. Thus, the bit
line 210 is formed over the bit line contact 105. An oxide film 104
is formed along a border between the device isolation film 102 and
the active region 103. Although not shown in the cross-sectional
views FIG. 1(ii) and FIG. 1(iii), a buried gate is formed in the
semiconductor substrate 101, and the buried gate is formed to be
perpendicular to the bit line 210.
[0036] In FIG. 1(ii), `C` indicates a cell region, and `P`
indicates a peripheral region of the semiconductor device. A
structure formed in the peripheral region P in accordance with an
embodiment will be described later with reference to FIGS. 3A to
3N.
[0037] FIG. 2 is a perspective view illustrating a storage node 224
formed according to an embodiment. Referring to FIG. 2, the storage
node 224 is formed over a second storage node contact 223. As
described above with reference to FIG. 1(i), the second storage
node contact 223 is patterned in a diagonal direction so that a
step difference is formed between a first top surface and a second
top surface thereof, resulting in improvement of the contact margin
between the storage node 224 and the second storage node contact
223.
[0038] In an embodiment, six storage nodes 224 are arranged within
substantially the same distance from one storage node as shown in
FIG. 2, and two adjacent storage nodes are spaced from each other
by substantially the same distance.
[0039] Since the storage node contact is formed through two
processing steps, a contact margin between the storage node contact
and the storage node 224 is improved. In addition, since the
storage node contact, i.e., the first storage node contact 221 and
the second storage node contact 223, is formed through the two
processing steps using the supporting film 217 without using an
additional mask, a fabrication process for forming the storage node
contact can be simplified, and self-alignment is facilitated.
[0040] A method for forming the semiconductor device of FIG. 1
according to an embodiment will hereinafter be described with
reference to FIGS. 3A to 3N. In FIG. 3A, (i) is a perspective view
of the semiconductor device, (ii) is a cross-sectional view of the
semiconductor device taken along a line X-X' in FIG. 3A(i).
[0041] In an embodiment, a lower structure 110 disposed under a bit
line 210 shown in FIG. 3A(i) includes an active region 103 and a
device isolation film 102 as shown in FIG. 3A(ii). In addition, the
lower structure 110 includes a buried gate (not shown) formed to
cross the active region 103 and a bit line contact 105 coupled to
the bit line 210. Since the lower structure 110 is shown and
described with reference to FIG. 3A(ii), a detailed description
thereof will not be repeated in subsequent descriptions of
structures of FIG. 3 for illustrative convenience. Instead,
subsequent descriptions of FIG. 3 will be directed primarily to an
upper structure, which is provided over the lower structure
110.
[0042] As can be seen from FIG. 3A(i), bit lines 210 spaced apart
from each other by a predetermined distance are formed over the
semiconductor substrate 101 in which the lower structure 110 of a
cell region C is formed. In an embodiment, a barrier metal layer
201, a bit line metal layer 203, and a bit line hard mask layer 205
are sequentially deposited over the semiconductor substrate 101,
and then they are patterned using a mask (not shown). After that, a
spacer 207 is formed on a sidewall and a top surface of the
patterned structure. The bit line 210 may be formed to be
perpendicular to the buried gate (not shown).
[0043] In an embodiment, when the barrier metal layer 201, the bit
line metal layer 203, and the bit line hard mask layer 205 are
sequentially deposited over the bit line contact 105 of the cell
region C, a polysilicon layer 301, a barrier metal layer 303, a
gate conductive layer 305, and a hard mask layer 307 are
sequentially deposited over the active region 103 of a peripheral
region (also called a peri region) P. After the layers 301, 303,
305, and 307 are patterned, a spacer 308 is formed on a sidewall of
the patterned structure, and an oxide film 309 is deposited on a
sidewall and a top surface of a resultant structure including the
spacer 308. The gate conductive layer 305 may be formed of a
conductive material such as tungsten (W) or the like, and the hard
mask layer 307 may be formed of a nitride film. Here, a gate
insulation film 302 may be formed below the polysilicon layer
301.
[0044] In FIG. 3B, (i) is a perspective view of the semiconductor
device, and (ii) is a cross-sectional view of the semiconductor
device taken along a line X-X' in FIG. 3B(i). Referring to FIG. 3B,
an interlayer insulation film 211 is deposited to fill a space
between the bit lines 210 and planarized until the bit line hard
mask layer 205 in the cell region C and the hard mask layer 307 in
the peripheral region P are exposed, and then a capping film 213 is
deposited over the bit lines 210 and the interlayer insulation film
211. The capping film 213 may be formed of a nitride film.
[0045] In FIG. 3C, (i) is a perspective view of the semiconductor
device, (ii) is a cross-sectional view of the semiconductor device
taken along a line X-X' in FIG. 3C(i), and (iii) is a
cross-sectional view of the semiconductor device taken along a line
Y-Y' in FIG. 3C(i). Referring to FIG. 3C(i), (ii), and (iii), the
interlayer insulation film 211 and the capping film 213 are etched
so that line-shaped holes 215 and 216 are formed to be
perpendicular to the bit line 210.
[0046] In FIG. 3D, (i) is a perspective view of the semiconductor
device, (ii) is a cross-sectional view of the semiconductor device
taken along a line X-X' in FIG. 3D(i), and (iii) is a
cross-sectional view of the semiconductor device taken along a line
Y-Y' in FIG. 3D(i). Referring to FIG. 3D, a nitride material is
buried in the line-shaped holes 215 and 216 so that a supporting
film 217 is formed. In addition, the nitride material is deposited
to cover the capping film 213. The supporting films 217 buried in
the holes 215 and 216 are spaced apart from one another by a
predetermined distance in a direction perpendicular to the bit line
210, resulting in formation of the line-shaped supporting films
217. The supporting films 217 may cover the top surfaces of the bit
lines 210 partially.
[0047] In FIG. 3E, (i) is a perspective view of the semiconductor
device, (ii) is a cross-sectional view of the semiconductor device
taken along a line X-X' in FIG. 3E(i), and (iii) is a
cross-sectional view of the semiconductor device taken along a line
Y-Y' in FIG. 3E(i). Referring to FIG. 3E, a cell opening mask (not
shown) is formed, and then the interlayer insulation film 211 and
the capping film 213 disposed between the supporting films 217 are
removed using the supporting films 217 in the cell region C as an
etch mask. As a result, line-shaped holes 219 are formed between
the supporting films 217, and a top surface of the supporting film
217 is located at a higher level than a top surface of the bit line
210. In other words, a step difference between the top surface of
the supporting film 217 and the top surface of the bit line 210 is
formed.
[0048] In FIG. 3F, (i) is a perspective view of the semiconductor
device, (ii) is a cross-sectional view of the semiconductor device
taken along a line X-X' of FIG. 3F(i), and (iii) is a
cross-sectional view of the semiconductor device taken along a line
Y-Y' in FIG. 3F(i). Referring to FIG. 3F, a first storage node
contact 221 is formed at a lower part of the hole 219, and a second
storage node contact 223 is formed over the first storage node
contact 221. In an embodiment, the first storage node contact 221
is formed as island type contacts separated from each other and
provided between the bit lines 210 and the supporting film 217. In
an embodiment, the first storage node contact 221 may be formed of
a polysilicon material or the like. The second storage node contact
223 is formed in the holes 219 between the bit lines 210 and over
the bit lines 210. The second storage node contact 223 is formed as
a line type, and may be formed of a metal material or the like.
[0049] Although not shown in the drawings, an air spacer, i.e., an
unfilled gap or space, may be formed between the first storage node
contact 223 and the bit line 210. In addition, a cobalt silicide
(CoSix) material may be deposited between the first storage node
contact 221 and the second storage node contact 223.
[0050] FIGS. 3G to 3M are cross-sectional views illustrating a
method for patterning the second storage node contact 223 in a
diagonal direction using a Spacer Patterning Technology (SPT) and a
Double Patterning Technology (DPT). In more detail, FIGS. 3G to 3M
are cross-sectional views illustrating the semiconductor device
taken along the line X-X' in the cell region C.
[0051] Referring to FIG. 3G, a first interlayer insulation film
227, a first etch stop film 229, a second interlayer insulation
film 231, and a second etch stop film 233 are sequentially
deposited over a resultant structure where the second storage node
contact 223 is formed. After that, a photoresist pattern 237 is
formed over the second etch stop film 233. In an embodiment, the
first or second etch stop film 229 or 233 may be formed of a
silicon oxynitride (SiON) film or the like.
[0052] Referring to FIG. 3H, the second etch stop film 233 and the
second interlayer insulation film 231 in the cell region C are
etched using the photoresist pattern 237 as a mask until the first
etch stop film 229 is exposed. As a result, first patterns 239
spaced apart from each other by a predetermined distance are formed
over the first etch stop film 229 in the cell region C. During this
process, only the cell region C is opened.
[0053] Referring to FIG. 31, a spacer material 241 is deposited
conformally over the first patterns 239. The spacer material 241
has good step coverage to form holes 242 between the first patterns
239 and between the first pattern 239 and the second interlayer
insulation film 231. Referring to FIG. 33, a spin on carbon (SOC)
material 243 is buried in the holes 242. In an embodiment, the SOC
material 243 partially fills the holes 242 so that a top surface of
the SOC material 243 is at substantially the same level as a top
surface of the first pattern 239.
[0054] Thereafter, as shown in FIG. 3K, second patterns 240a and
240b are formed by etching the spacer material 241 and the first
etch stop film 229. During this etch process, the second etch stop
film 233 remaining at a top part of the first patterns 239 is also
removed. The second pattern 240a is formed from the first pattern
239 of FIG. 31, and the second pattern 240b is formed from the SOC
material 243. The second patterns 240a and 240b may be formed to
have substantially the same width as the first pattern 239.
[0055] A distance between the first patterns 239 is at least two
times greater than a distance between the second patterns 240a and
240b.
[0056] In an embodiment, when the spacer material 241 and the first
etch stop film 229 are removed, the spacer material 241 and the
second etch stop film 233 that are formed in the peripheral region
P are also removed.
[0057] Referring to FIG. 3L, third patterns 245a and 245b are
formed by etching the first interlayer insulation film 227 using
the second patterns 240a and 240b as a mask. During this etching
process, the second interlayer insulation film 231 formed at a top
part of the third pattern 245a and the SOC material 243 formed at a
top part of the third pattern 245b are simultaneously removed. The
third patterns 245a and 245b may have substantially the same width
as the first pattern 239.
[0058] When the third patterns 245a and 245b are formed, the second
interlayer insulation film 231 that is formed in the peripheral
region P is also removed.
[0059] Referring to FIG. 3M, the second storage node contact 223
formed as a line type is etched using the third patterns 245a and
245b as a mask. When the second storage node contact 223 is etched,
the first etch stop film 229 that is formed in the peripheral
region P is also removed.
[0060] After that, the third patterns 245a and 245b and the first
interlayer insulation film 227 formed in the peripheral region P
are removed.
[0061] In FIG. 3N, (i) is a perspective view of the semiconductor
device, (ii) is a cross-sectional view of the semiconductor device
taken along a line X-X' in FIG. 3N(i), and (iii) is a
cross-sectional view of the semiconductor device taken along a line
Y-Y' in FIG. 3N(i). Referring to FIG. 3N, the second storage node
contact 223 includes a first top surface 247 and a second top
surface 249 that are formed to have a step difference therebetween.
The first top surface 247 is located at a higher level than a top
surface 255 of the bit line 210, and the second top surface 249 is
located at a lower level than the top surface 255 of the bit line
210. The supporting film 217 includes a first top surface 251 and a
second stop surface 253 that are formed to have a step difference
therebetween, the first top surface 251 may be formed over the bit
line 210, and the second top surface 253 may be formed at
substantially the same level as the top surface 255 of the bit line
210, or may be formed at a level lower than the top surface 255 of
the bit line 210.
[0062] FIG. 4 is a block diagram illustrating an electronic device
including a semiconductor device according to an embodiment.
[0063] Referring to FIG. 4, the electronic device 800 includes a
data storage unit 810, a memory controller 820, a buffer (cache)
memory 830, and an input/output (I/O) interface 840.
[0064] The data storage unit 810 may store data received from the
memory controller 820 and output the stored data to the memory
controller 820 in response to a control signal from the memory
controller 820. The data storage unit 810 may include various
non-volatile memory units that can get back stored data even when
powered off, for example, a NOR flash memory, a NAND flash memory,
a phase change random access memory (PRAM), a resistive random
access memory (RRAM), a spin transfer torque random access memory
(STTRAM), a magnetic random access memory (MRAM), etc.
[0065] The memory controller 820 may decode a command received from
an external device (e.g., host device) through the I/O interface
840, and may control data I/O operations of the data storage unit
810 and the buffer memory 830. Although the memory controller 820
is denoted by a single block in FIG. 4 for illustrative
convenience, the memory controller 820 may include a first
controller for controlling the data storage unit 810 and a second
controller for controlling the buffer memory 830. Here, the first
controller and the second controller may be arranged independently
from each other.
[0066] The buffer memory 830 may temporarily store data to be
processed by the memory controller 820. In other words, the buffer
memory 830 may temporarily store data to be input to the data
storage unit 810 and data output from the data storage unit 810.
The buffer memory 830 may store data received from the memory
controller 830 and output the stored data to the memory controller
820 in response to a control signal from the memory controller 820.
The buffer memory 830 may include a volatile memory such as a
dynamic random access memory (DRAM), a mobile DRAM, a static random
access memory (SRAM), or the like.
[0067] The I/O interface 840 may provide a physical connection
between the memory controller 820 and the external device (host
device) such that the memory controller 820 receives data I/O
control signals from the external device and exchanges data with
the external device. The I/O interface 840 may include at least one
of interface protocols, for example, a universal serial bus (USB)
protocol, a multimedia card (MMC) protocol, a peripheral component
interconnection (PCI) protocol, a PCI-express (PCI-E) protocol, a
serial attached SCSI (SAS), a serial ATA (SATA) protocol, a
parallel advanced technology attachment (PATA) protocol, a small
computer small interface (SCSI) protocol, an enhanced small disk
interface (ESDI) protocol, and an integrated drive electronics
(IDE) protocol.
[0068] Each of memory cells of the data storage unit 810 or the
buffer memory 830 in the electronic device 800 may include a
supporting film formed to be perpendicular to a bit line, a first
storage node contact formed at a lower part of a region between the
bit line and the supporting film, and a second storage node contact
that is formed in a line shape isolated by the supporting film,
formed over the first storage node contact and the bit line, and
patterned in a diagonal direction. As a result, a process margin
between a storage node and the storage node contact is improved,
and a fabrication process is simplified. Self-alignment of the
storage node contact is also facilitated.
[0069] The electronic device 800 shown in FIG. 4 may be used as an
auxiliary memory device or an external storage device of the host
device. The electronic device 800 may include any of a solid state
disc (SSD), a universal serial bus (USB) memory, a secure digital
(SD) card, a mini secure digital (mSD) card, a micro SD card, a
high-capacity secure digital high capacity (SDHC) card, a memory
stick card (MSC), a smart media (SM) card, a multi media card
(MMC), an embedded MMC (eMMC), a compact flash (CF) card, etc.
[0070] As is apparent from the above description, a semiconductor
device and a method for forming the same according to embodiments
can simplify a storage node contact forming process and facilitate
self-alignment of the storage node contact.
[0071] Those skilled in the art will appreciate that embodiments
may be carried out in other specific ways than those set forth
herein without departing from the spirit and essential
characteristics of the present invention. The above embodiments are
therefore to be construed in all aspects as illustrative and not
restrictive. Embodiments should be determined by the appended
claims and their legal equivalents, not by the above description,
and all changes coming within the meaning and equivalency range of
the appended claims are intended to be embraced therein. Also,
claims that are not explicitly cited in each other in the appended
claims may be presented in combination as an exemplary embodiment
or included as a new claim by a subsequent amendment after the
application is filed.
[0072] The above embodiments of the present invention are
illustrative and not limitative. Various alternatives and
equivalents are possible. The invention is not limited by the type
of deposition, etching polishing, and patterning steps described
herein. Nor is the invention limited to any specific type of
semiconductor device. For example, the present invention may be
implemented in a dynamic random access memory (DRAM) device or non
volatile memory device. Other additions, subtractions, or
modifications are obvious in view of the present disclosure and are
intended to fall within the scope of the appended claims.
* * * * *