U.S. patent application number 14/578704 was filed with the patent office on 2015-04-23 for double patterning method to form sub-lithographic pillars.
The applicant listed for this patent is Micron Technology, Inc.. Invention is credited to Marcello Mariani, Fabio Pellizzer, Giorgio Servalli.
Application Number | 20150108422 14/578704 |
Document ID | / |
Family ID | 40996624 |
Filed Date | 2015-04-23 |
United States Patent
Application |
20150108422 |
Kind Code |
A1 |
Pellizzer; Fabio ; et
al. |
April 23, 2015 |
DOUBLE PATTERNING METHOD TO FORM SUB-LITHOGRAPHIC PILLARS
Abstract
A method and resulting structure, is disclosed to fabricate
vertical bipolar junction transistors including a regular array of
base contact pillars and emitter contact pillars with a at least
one dimension below the minimum lithographical resolution, F, of
the lithographic technique employed. A storage element, such as a
phase change storage element, can be formed above the regular array
of base contact pillars and emitter contact pillars.
Inventors: |
Pellizzer; Fabio; (Cornate
d'Adda, IT) ; Mariani; Marcello; (Milano, IT)
; Servalli; Giorgio; (Ciserano, IT) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Micron Technology, Inc. |
Boise |
ID |
US |
|
|
Family ID: |
40996624 |
Appl. No.: |
14/578704 |
Filed: |
December 22, 2014 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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13132602 |
Jun 2, 2011 |
8921196 |
|
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PCT/IT2008/000813 |
Dec 30, 2008 |
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14578704 |
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Current U.S.
Class: |
257/5 ; 257/2;
438/330 |
Current CPC
Class: |
H01L 29/41708 20130101;
H01L 21/76224 20130101; H01L 21/0338 20130101; H01L 45/1233
20130101; H01L 45/126 20130101; H01L 27/1022 20130101; H01L 29/732
20130101; H01L 45/144 20130101; H01L 29/66272 20130101; H01L
27/2445 20130101; H01L 29/42304 20130101; H01L 45/06 20130101; H01L
29/0649 20130101; H01L 27/2463 20130101; H01L 45/16 20130101 |
Class at
Publication: |
257/5 ; 257/2;
438/330 |
International
Class: |
H01L 27/24 20060101
H01L027/24; H01L 29/732 20060101 H01L029/732; H01L 21/762 20060101
H01L021/762; H01L 29/417 20060101 H01L029/417; H01L 29/423 20060101
H01L029/423; H01L 29/06 20060101 H01L029/06; H01L 45/00 20060101
H01L045/00; H01L 29/66 20060101 H01L029/66 |
Claims
1. A structure of vertical bipolar junction transistors, the
structure comprising: a regular array of base contact pillars and a
regular array of emitter contact pillars, the base contact pillars
and the emitter contact pillars each having a width below a minimum
lithographical resolution, F; a first level base contact plug in
electrical contact with a plurality of the base contact pillars;
and a storage element located above the regular array of base
contact pillars and the regular array of emitter contact
pillars.
2. The structure of claim 1, wherein the storage element is a phase
change storage element.
3. The structure of claim 1, wherein the storage element is located
below a word line.
4. The structure of claim 1, further comprising a first level
emitter contact in electrical contact with a single emitter contact
pillar.
5. A system, comprising: a controller; and a memory array
including: a phase change memory cell; a regular array of base
contact pillars and a regular array of emitter contact pillars, the
base contact pillars and the emitter contact pillars each having a
width below a minimum lithographical resolution, F; and a first
level base contact plug in electrical contact with a plurality of
the base contact pillars.
6. The system of claim 5, wherein the regular array of base contact
pillars and the regular array of emitter contact pillars share a
common collector.
7. The system of claim 5, wherein the regular array of base contact
pillars and the regular array of emitter contact pillars are
defined by a first set of parallel trenches in a first direction
and a second set of parallel trenches in a second direction that is
approximately perpendicular to the first direction.
8. The system of claim 5, wherein the base contact pillars and the
emitter contact pillars have a width of about F/2.
9. The system of claim 5, wherein each row of the emitter contact
pillars is separated from an adjacent row by a shallow trench
isolation region.
10. The system of claim 5, wherein each row of the emitter contact
pillars is separated from an adjacent row by a shallow trench
isolation region.
11. The system of claim 5, further comprising: a first region
having a dopant of a first polarity; and a second region having a
dopant of a second polarity, the second region being formed over
the first region.
12. The system of claim 11, further comprising: a first plurality
of shallow trench isolation regions extending to the first region;
and a second plurality of shallow trench isolation regions
extending at least to an uppermost portion of the second region but
not as far as the first region.
13. The system of claim 5, wherein the regular array of base
contact pillars and a regular array of emitter contact pillars each
have a pitch of about F.
14. A device, comprising: a structure of vertical bipolar
transistors having a regular array including a plurality of base
contact pillars and a plurality emitter contact pillars, the
plurality of base contact pillars and the plurality of emitter
contact pillars each having a width below a minimum lithographical
resolution; a first level base contact plug in electrical contact
with each of the plurality of the base contact pillars; and a
storage element coupled to the regular array of the base contact
pillars and the emitter contact pillars.
15. The device of claim 14, wherein the storage element comprises a
plurality of phase change memory elements, and ones of the vertical
bipolar transistors are coupled to respective ones of the plurality
of phase change memory elements, the vertical bipolar transistors
being configured as switching elements for the respective ones of
the plurality of phase change memory elements.
16. The device of claim 14, wherein the plurality of base contact
pillars include a first set of shallow trench isolation regions
that extend at least to a first doped region, and the plurality of
emitter contact pillars include a second set of shallow trench
isolation regions which do not extend to the first doped
region.
17. The device of claim 16, wherein the first doped region is a
common collector, and the second set of shallow trench isolation
regions are formed substantially perpendicular to the first set of
shallow trench isolation regions.
18. A method of fabricating an electronic device, the method
comprising: forming an array of base contact pillars and an array
of emitter contact pillars, the forming of the array of base
contact pillars and the array of the emitter contact pillars
including a double-patterning technique including forming a first
set of shallow trench isolation regions extending at least to a
first doped region, and forming a second set of shallow trench
isolation regions which do not extend to the first doped region,
the first doped region being a common collector, the second set of
shallow trench isolation regions being formed substantially
perpendicular to the first set of shallow trench isolation
regions.
19. The method of claim 18, wherein the second set of shallow
trench isolation regions extend to a second doped region, the
second doped region having a polarity opposite that of the first
doped region.
20. The method of claim 18, further comprising forming the base
contact pillars and the emitter contact pillars to each have a
width of about F/2, where F is a minimum lithographical resolution
of a lithographic system used to form the electronic device.
21. The method of claim 18, wherein the double-patterning technique
further includes: partially removing a dielectric material from
between a patterned etch stop layer after filling each set of
shallow trench isolation regions with the dielectric material; and
removing the patterned etch stop layer after partially removing the
dielectric material from between the patterned etch stop layer.
22. The method of claim 18, further comprising forming a storage
element above the array of base contact pillars and the array of
emitter contact pillars.
Description
BACKGROUND
[0001] Embodiments of the invention relate to a method of
fabricating a regular array of vertical bipolar junction
transistors with dimensions below the minimum lithographical
resolution. In particular, the present description refers to the
manufacture of a regular array of vertical bipolar junction
transistors operating as selection devices in a phase change
memory.
[0002] Phase change memories are formed by memory cells connected
at the intersections of bit-lines and word-lines and comprising
each a memory element and a selection element. A memory element
comprises a phase change region made of a phase change material,
i.e., a material that may be electrically switched between a
generally amorphous and a generally crystalline state across the
entire spectrum between completely amorphous and completely
crystalline states.
[0003] Typical materials suitable for the phase change region of
the memory elements include various chalcogenide elements. The
state of the phase change materials is non-volatile, absent
application of excess temperatures, such as those in excess of
150.degree. C., for extended times. When the memory is set in
either a crystalline, semi-crystalline, amorphous, or
semi-amorphous state representing a resistance value, that value is
retained until reprogrammed, even if power is removed.
[0004] Selection elements may be formed according to different
technologies. For example, they can be implemented by diodes, metal
oxide semiconductor (MOS) transistors or bipolar transistors.
BRIEF DESCRIPTION OF THE DRAWINGS
[0005] FIG. 1A is a top view illustration of a regular array of
pillars in accordance with an embodiment.
[0006] FIG. 1B is a side view illustration along the BL'-BL'' line
in FIG. 1A.
[0007] FIG. 1C is a side view illustration along the WL'-WL'' line
in FIG. 1A.
[0008] FIG. 2-FIG. 23 are side view illustrations of an embodiment
for fabricating the structure illustrated in FIG. 1A-FIG. 1C.
[0009] FIG. 24A is a top view illustration of a plug landing on
base contact pillars.
[0010] FIG. 24B is a side view illustration along the BL'-BL'' line
in FIG. 24A.
[0011] FIG. 24C is a side view illustration along the WL'-WL'' line
in FIG. 24A.
[0012] FIG. 25 is a side view illustration of a storage element
placed below a word line.
[0013] FIG. 26 is an illustration of a system in accordance with an
embodiment.
DETAILED DESCRIPTION
[0014] Embodiments of the present invention disclose a method of
fabricating a regular array of vertical bipolar junction
transistors with dimensions below the minimum lithographical
resolution.
[0015] Various embodiments described herein are described with
reference to figures. However, certain embodiments may be practiced
without one or more of these specific details, or in combination
with other known methods and configurations. Reference throughout
this specification to "one embodiment" or "an embodiment" means
that a particular feature, configuration, composition, or
characteristic described in connection with the embodiment is
included in at least one embodiment of the invention. Thus, the
appearances of the phrase "in one embodiment" or "an embodiment" in
various places throughout this specification are not necessarily
referring to the same embodiment of the invention. Furthermore, the
particular features, configurations, compositions, or
characteristics may be combined in any suitable manner in one or
more embodiments.
[0016] A method is disclosed for forming a regular array of
vertical bipolar junction transistors. A regular array of base
contact pillars and emitter contact pillars are formed with a
lithographic technique having a minimum lithographical resolution
F. Double patterning techniques can be performed to form the base
contact pillars and emitter contact pillars having a width below
the minimum lithographical resolution F. In an embodiment, the
pillar array features have a dimension of approximately F/2, though
this dimension could be reduced down to other values compatible
with embodiments of the invention. The regular array of base
contact pillars and emitter contact pillars can be defined by a
first set of parallel trenches in a first direction and a second
set of parallel trenches in a second direction perpendicular to the
first direction. A storage element, such as a phase change storage
element, can be formed above the regular array of base contact
pillars and emitter contact pillars.
[0017] FIG. 1A-FIG. 1C illustrate a top view, side view Y-array
(i.e., the array viewed in the Y direction which will become the
bit-line BL'-BL'' of FIG. 1A), and side view X-array (i.e., the
array viewed in the X direction which will become the word-line
WL'-WL'' of FIG. 1A) of a regular array of pillars with dual
shallow trench isolation in accordance with embodiments of the
present invention. A semiconductor substrate is doped by a p-type
collector implant to form a p-type collector (common) 12 under a
shallower base implant that forms an n-type base (word-line) 14
including upper part 14a and lower part 14b. The base implant may
be antimony and arsenic in one embodiment. The collector implant
may be boron in one embodiment.
[0018] A plurality of emitter pillars 16 may be arranged in four
columns, each column extending in the Y-direction, in one
embodiment. Each set of four columns of emitter pillars 16 is
separated by a set of two base electrodes or contact pillars 18.
Thus, a Y-direction column of base contact pillars 18 is followed
in the X-direction by four columns of emitter pillars 16, each
column extending in the Y direction, followed by another column of
base contact pillars 18, and this pattern repeats.
[0019] Each row of emitter pillars 16 is separated from an adjacent
row by shallow trench isolation 22. Likewise, each column of
emitter pillars 16 is separated from adjacent emitter pillars 16 in
the X-direction by shallow trench isolation 20. In this embodiment
the depth of the shallow trench isolation 20 may range between 50
nm and 200 nm and so it may be much shallower than the shallow
trench isolations 22, whose depth may range between 200 nm and 500
nm.
[0020] The deeper shallow trench isolations 22 may extend all the
way into (or alternatively to the top of) the p-type collector 12
while the shallow trench isolations 20 may extend only into the
n-type base or word-line 14, in one embodiment. Thus, the n-type
base or word-line 14 is made up of a lower part 14b which is below
the shallow trench isolation 20, and an upper part 14a which is
above the bottom of shallow trench isolation 20.
[0021] In one embodiment, the base contact pillars 18 have n+ base
contacts 54, the emitter pillars 16 are p-type with p+ emitter
contacts 56, and the word-line is n-type. However, the polarities
may also be reversed in some cases. In addition, the number of
columns of emitter pillars 16 between base contact emitter pillars
18 may be more or less than four.
[0022] As a result, a bipolar junction transistor is formed with
emitter pillars 16, base contact pillars 18, bases or word-lines
14, and collector 12. The collector 12 is common to all the
transistors. The word-line or base 14 is common to each row in the
X-direction. Individual transistors are formed by the segmented
emitter pillars 16 and segmented base contact pillars 18.
[0023] FIG. 2-FIG.23 are illustrations of an embodiment for
fabricating the structure shown in FIG. 1A-FIG. 1C. While the
embodiment illustrates the formation of a first set of parallel
trenches with a first depth and in a first direction, and a second
set of parallel trenches with a second depth and in a second
direction perpendicular to the first direction, embodiments of the
invention are not so limited and the order of forming the trenches
can be reversed. Furthermore, it is to be appreciated that doping
of the base contact pillars and emitter contact pillars can be
performed at various stages, such as before, during, and/or after
the process illustrated in FIG. 2-FIG. 23.
[0024] FIG. 2 is a side view illustration of the layers used for
patterning. As shown, the layers include a substrate 10, dielectric
layer 24, etch stop layer 26, and fin patterning layer 28. In an
embodiment, substrate 10 is a silicon substrate, though other known
semiconductor materials can be used. In an embodiment, the
substrate 10 may be doped with a p-type collector implant to form
the p-type collector (common) 12 under a shallower base implant
that forms the n-type base (word-line) lower part 14b. The base
implant may be antimony and/or arsenic in one embodiment. The
collector implant may be boron in one embodiment.
[0025] Referring again to FIG. 1B, the n-type dopant forming the
word-line 14 does not extend beyond the shallow trench isolation
regions 22, which may be 200-500 nm deep, separating each row of
emitter pillars 16. Stated differently, when shallow trench
isolation regions 22 are formed, they extend in the array all the
way through the n-base or word-line 14 into the underlying p-type
collector 12. In an embodiment, dielectric layer 24 is an oxide
5-10 nm thick, and etch stop layer 26 is a nitride 40-60 nm thick.
In an embodiment, the fin patterning layer 28 is an approximately
160 nm thick polysilicon layer. The polysilicon may be amorphous or
undoped, as two examples. However, fin patterning layer 26 is not
limited to polysilicon, and can be any material, such as a
dielectric or photoresist, which can be selectively removed
relative to the etch stop layer 26.
[0026] Then, as illustrated in FIG. 3, the first shallow trench
isolation mask is exposed to define horizontal strips of active
area. The exposure resolves the minimum lithographical dimension F.
A masking layer 30 such as photoresist or suitable hard-mask is
patterned in strips with the minimum lithographical dimension
F.
[0027] The fin patterning layer 28 is then patterned as illustrated
in FIG. 4 to form fins 32. The fins 32 are etched utilizing a
partially isotropic etching technique such that the dimensions are
reduced to approximately F/2. This dimension will not determine the
width of the Y-direction active area strips, but only their
spacing, as further described.
[0028] A conformal layer 34 is then deposited over the fins 32, as
illustrated in FIG. 5. The conformal layer 34 may be silicon oxide,
for example. In an embodiment, the conformal layer 34 has a
thickness of F/2 on the sidewalls of fins 32 and the distance
between the conformal layer 34 on the sidewalls of adjacent fins 32
is also F/2. The conformal layer 34 is then anisotropically etched
back as shown in FIG. 6, and the fins 32 are selectively removed as
shown in FIG. 7 leaving a regular grid of spacers 36 having a
controlled width of F/2. The regular grid of spacers 36 are
separated by a distance of F/2 and have a pitch of F. In a
particular embodiment, F is approximately 60 nm when utilizing 193
nm lithographic wavelength and immersion lithography techniques.
Though, this dimension could be reduced down to any value
compatible with thickness control of the conformal layer 34 and
spacers 36. The final pitch will not go below F, being definitely
linked to the minimal lithographical dimension (i.e. to the minimum
lithographical half-pitch).
[0029] Spacers 36 are then used as a hard mask to define
Y-direction active area strips with sub-lithographical dimensions.
As shown in FIG. 8, spacers 36 are used as a hard mask to
anisotropically etch the underlying etch stop layer 26, dielectric
layer 24, and substrate 10 to form shallow trench isolations 22
which in turn define the Y-direction active area strips. In an
embodiment, shallow trench isolations 22 are etched approximately
200-500 nm deep into the substrate 10. In an embodiment, shallow
trench isolations 22 are etched to a depth of approximately 270 nm
from the top surface of the substrate 10. In an embodiment, where
word-line 14 and/or collector 12 doping has already been performed,
shallow trench isolations 22 are etched all the way through the
n-base or word-line 14 and into (or alternatively to the top of)
the underlying p-type collector 12. Spacers 36 may then be
selectively removed, though complete removal is not necessary to
the practice of embodiments of the invention. The regular array of
base contact pillars and emitter contact pillars which will
subsequently be formed are partially defined by the first set of
parallel shallow trench isolations 22 in the Y-direction.
[0030] Referring now to FIG. 9, a dielectric layer 38 is blanket
deposited over the substrate, filling the shallow trench isolations
22 and covering the top surface of the patterned etch stop layer
26. In an embodiment, dielectric layer 38 is the same material as
conformal layer 34. For example, both layers may be silicon oxide.
A particular benefit of utilizing the same material for both
dielectric layer 38 and conformal layer 34 is that any residual
spacer 36 material not removed after etching shallow trench
isolations 22 is now included in dielectric layer 38 on top of etch
stop layer 26.
[0031] Chemical mechanical polishing (CMP) is then performed to
remove dielectric layer 38 on top of patterned etch stop layer 26,
forming a planar surface as shown in FIG. 10. In particular, the
etch stop layer 26 performs a dual function. Firstly, etch stop
layer 26 assists in the etching process of fin patterning layer 28
to form fins 32, and additionally functions as a physical stopping
layer during CMP. However, as will become apparent, the presence of
the patterned etch stop layer 26 could potentially be problematic
during subsequent lithographical processes because the presence of
multiple different materials on the top surface of the substrate
can cause wave reflection which is particularly detrimental to
sub-lithographical resolution in embodiments of the present
invention. Moreover the etch stop layer 26 could represent a
discontinuity during etching of the shallow trench 20, because it
would be present only on half of the exposed area. Thus, the etch
stop layer 26 is removed.
[0032] As shown in FIG. 11, prior to removal of patterned etch stop
layer 26, the dielectric material 38 within the patterned etch stop
layer 26 is partially removed, for example by selective wet etch
with a buffered HF solution. Then, as shown in FIG. 12, the
patterned etch stop layer 26 is selectively removed leaving surface
topography including a top surface of dielectric material 38 that
is approximately planar with the top surface of dielectric layer
24. In an embodiment, the top surface of dielectric material 38 is
above or even with the top surface of dielectric layer 24, but is
not below the top surface of dielectric layer 24. In an embodiment,
dielectric material 38 is removed with regard to at least 80% of
the original etch stop layer 26 thickness. For example, where
original etch stop layer is approximately 50 nm thick,
approximately 40 nm of dielectric material 38 is removed so that
the top surface of dielectric material 38 is approximately 10 nm or
less above the top surface of dielectric layer 24. In accordance
with embodiments of the invention, the surface topography is not
chemical mechanical polished at this point because an etch stop
layer is not present to control removal.
[0033] In one embodiment, the substrate 10 is not already doped for
the collector and/or base. In such an embodiment, the substrate 10
including the Y-direction active area strips can be doped by a
p-type collector implant to form a p-type collector (common) 12
under a shallower base implant that forms an n-type base
(word-line) 14. The base implant may be antimony and arsenic in one
embodiment. The collector implant may be boron in one
embodiment.
[0034] Then, as illustrated in FIG. 13 and FIG. 14, another etch
stop layer 40 is deposited over the top surface of dielectric
material 38 and dielectric layer 24, followed by a fin patterning
layer 42, and masking layer 44. Layers 40, 42 and 44 can be the
same materials as layers 26, 28 and 30, respectively. As shown in
FIG. 14, the lithographical exposure of masking layer 44 is rotated
by 90 degrees, with respect to the exposure of masking layer 30 and
the previous procedure is repeated. The exposure resolves the
minimum lithographical dimension F in masking layer 44.
[0035] As illustrated in FIG. 15, the fin patterning layer 42 is
then patterned to form fins 46. The fins 46 are etched utilizing an
isotropic etching technique such that the dimensions are reduced to
approximately F/2. This dimension will not determine the width of
the active areas (pillars), but only their spacing, as further
described.
[0036] A conformal layer 48 is then deposited over the fins 46, as
illustrated in FIG. 16. The conformal layer 48 may be silicon
oxide, for example. In an embodiment, the conformal layer 48 has a
thickness of F/2 on the sidewalls of fins 46 and the distance
between the conformal layer 48 on the sidewalls of adjacent fins 46
is also F/2. The conformal layer 48 is then anisotropically etched
back as shown in FIG. 17, and the fins 46 are selectively removed
as shown in FIG. 18 leaving a regular grid of spacers 50 having a
controlled width of F/2. The regular grid of spacers 50 are
separated by a distance of F/2 and have a pitch of F. In a
particular embodiment, F is approximately 60 nm when utilizing 193
nm lithographic wavelength and immersion lithography techniques.
Though, this dimension could be reduced down to any value
compatible with thickness control of the conformal layer 48 and
spacers 50. The final pitch will not go below F, being definitely
linked to the minimal lithographical dimension (i.e. to the minimum
lithographical half-pitch).
[0037] Spacers 50 are then used as a hard mask to define the
X-direction active area strips with sub-lithographical dimensions.
The X-direction active area strips intersect the Y-direction active
area strips to form the regular array of active area pillars with
sub-lithographical dimensions in accordance with embodiments of the
present invention. As shown in FIG. 19, spacers 50 are used as a
hard mask to anisotropically etch the underlying etch stop layer
40, dielectric layer 24, and substrate 10 to form shallow trench
isolations 20. In an embodiment, shallow trench isolations 20 are
etched approximately 50-200 nm deep into the substrate 10. Spacers
50 may then be selectively removed, though complete removal is not
necessary to the practice of embodiments of the invention.
[0038] Referring now to FIG. 20, a dielectric layer 52 is blanket
deposited over the substrate filling the shallow trench isolations
20 and covering the top surface of the patterned etch stop layer
40. In an embodiment, dielectric layer 52 is the same material as
conformal layer 48. For example, both layers may be silicon oxide.
A particular benefit of utilizing the same material for both
dielectric layer 52 and conformal layer 48 is that any residual
spacer 50 material not removed after etching shallow trench
isolations 20 is now included in dielectric layer 52 on top of etch
stop layer 40.
[0039] Chemical mechanical polishing (CMP) is then performed to
remove dielectric layer 52 on top of patterned etch stop layer 40,
forming a planar surface as shown in FIG. 21. In particular, the
patterned etch stop layer 40 performs a dual function. Firstly,
etch stop layer 40 assists in the etching process of fin patterning
layer 42 to form fins 46, and additionally functions as a physical
stopping layer during CMP. Etch stop layer 40 is subsequently
removed as illustrated in FIG. 23.
[0040] Prior to removal of patterned etch stop layer 40, as shown
in FIG. 22, the dielectric material 52 within the patterned etch
stop layer 40 is partially removed, for example by selective wet
etch with a buffered HF solution. Then, as shown in FIG. 23, the
patterned etch stop layer 40 is selectively removed leaving surface
topography including a top surface of dielectric material 52 that
is approximately planar with the top surface of dielectric layers
24 and 38. In an embodiment, the top surface of dielectric material
52 is above or even with the top surface of dielectric layer 24,
but is not below the top surface of dielectric layer 24. In an
embodiment, dielectric material 52 is removed with regard to at
least 80% of the original etch stop layer 40 thickness. For
example, where original etch stop layer is approximately 50 nm
thick, approximately 40 nm of dielectric material 52 is removed so
that the top surface of dielectric material 52 is approximately 10
nm or less above the top surface of dielectric layer 24. In
accordance with embodiments of the invention, the surface
topography is not chemical mechanical polished at this point
because an etch stop layer is not present to control removal.
[0041] In one embodiment, the substrate 10 is not already doped for
the collector and/or base. In such an embodiment, the substrate 10
including the partially completed structure can be doped by a
p-type collector implant to form a p-type collector (common) 12
under a shallower base implant that forms an n-type base
(word-line) 14. The base implant may be antimony and arsenic in one
embodiment. The collector implant may be boron in one embodiment.
In an embodiment, the emitter pillars 16 are now doped with a
p-type dopant to form p+ emitter contacts 56. In an embodiment the
base pillars 18 are now doped with an n-type implant to form the n+
base contacts 54.
[0042] The regular array of pillars with planar dimensions
F/2.times.F/2 and a pitch F is illustrated in FIG. 1. As previously
described, implants and thermal treatments could be performed in
order to create the vertical pnp BJTs at several times during
processing such as with the original substrate provided in FIG. 2,
after the etch stop layer 26 removal in FIG. 12, and after the etch
stop layer 40 removal in FIG. 23. Likewise, implant and thermal
treatments can be performed in a combination of the above mentioned
periods. In an embodiment, collector 12 p-doping and word-line 14
n-doping is performed in the original substrate prior to. FIG. 2,
while p+ emitter contact 56 doping and n+ base contact 54 doping
are performed after etch stop layer 26 removal in FIG. 23. After
all implants and activation have been completed, the top of all
pillars, both base contacts 18 and emitter 16, may be silicided
(e.g. with Titanium, Cobalt or Nickel)."
[0043] FIG. 24A-FIG. 24C are illustrations of a contact plug 83
landing on the base contact pillars 18. In an embodiment, contact
plug 83 landing is made with two base contact pillars 18, which
gives a workable margin for landing since the base contact pillars
18 are below lithographic resolution. As shown, base contact plugs
83 contact two base contact pillars 18. While the base contact
plugs 83 are illustrates as rectangles, in fabrication the
lithographic resolution can make them elliptical. The contacting
scheme is peculiar to embodiments of the present invention as an
elongated contact is needed to satisfy lithographic requirements
and two base contact pillars 18 are needed to preserve the
regularity of the pillar array and to guarantee margins for
relative registration of these contacts to the underlying active
areas.
[0044] In an embodiment, the string is made of four emitter pillars
and two base contact pillars, though the string can also be made of
2.sup.n emitter pillars (n is an integer>0) or any other
positive number of emitter pillars. In an embodiment, the pillar
array features have a dimension of approximately F/2, though this
dimension could be reduced down to any value compatible with
thickness control of the conformal layers 34, 48 and spacers 36,
50. The final pitch will not go below F, being definitely linked to
the minimal lithographical dimension (i.e. to the minimum
lithographical half-pitch).
[0045] In one embodiment, a non-volatile storage element array may
be formed over the bipolar junction transistors that act as
selection devices for each storage element array. The structure
illustrated in FIG. 24A-FIG. 24C does not illustrate a storage
element, such as phase change memory (PCM), phase-change random
access memory (PRAM or PCRAM), ovonic unified memory (UOM) or
chalcogenide random access memory (C-RAM), though such, a storage
element can be below or above the word-line 82.
[0046] FIG. 25 is an illustration of an embodiment in which a
storage element is placed below the word-line 82. Base contact
pillars 18 and the emitter contact pillars 16 separated by shallow
trench isolations 20 may be covered with a first dielectric layer
71 that may be undoped silicon glass with a thickness of 700 nm,
which is deposited and planarized down to 600 nm, in one
embodiment.
[0047] Thereafter, the first dielectric layer 71 and optional first
nitride layer are etched where contacts may be formed so as to form
openings that reach the silicide region 68. The apertures may be
filled with a barrier layer such as multiple titanium/titanium
nitride layers (not shown), and by a tungsten layer (not shown),
and the deposited layers may be planarized to form first level
plugs 73a and 73b. The first level plugs 73a are in contact with
the base contact pillars 18, and the first level plugs 73b are in
electrical contact with the emitter contact pillars 16.
[0048] Then, a second dielectric layer 76 is deposited. Openings
are formed in the second dielectric layer 76 above the emitter
contact pillars 16. A spacer layer 75 of silicon nitride is formed
on the walls of the openings, using deposition and subsequent
etch-back. Heater layer 77 and a sheath layer 74 may be
subsequently deposited to cover the walls and the bottom of the
openings. A third dielectric layer 67 may be deposited to fill the
openings. The wafer is planarized in one embodiment. Accordingly,
the heaters 77 may generally be cup-shaped. The heaters 77 extend
on a first level plug 73b which is in electric contact with the
emitter contact pillars 16.
[0049] Next, a chalcogenide layer 78, which may be GST
(Ge.sub.2Sb.sub.2Te.sub.5), and a metal layer 79 are deposited and
defined to form resistive bit-lines, which run perpendicularly to
the plane and the sheet. Metal lines 79 then create a first metal
level.
[0050] Then, a sealing level 80 and a fourth dielectric layer 81
may be deposited. Holes are opened, coated with a barrier layer,
and filled by a metal layer 83 of copper in one embodiment.
[0051] Then, word-lines 82 from the second metal layer are formed
on the fourth dielectric layer 81 in electrical contact with the
second level, base plugs 83, and thus the base regions, through the
first level plugs 73a on the base contacts 18. A third nitride
layer 88 may be joined over the word-lines 82.
[0052] The bit-lines BL may be formed in the sixth dielectric layer
89 from a third metal layer.
[0053] Programming to alter the state or phase of the material may
be accomplished by applying voltage potentials to the heater 77 and
the metal layer 79, thereby generating a voltage potential across a
memory element including the chalcogenide layer 78. When the
voltage potential is greater than the threshold voltages of any
select device and memory element, then an electrical current may
flow through the phase change layer 26 in response to the applied
voltage potentials, and may result in heating of the chalcogenide
layer 78.
[0054] This heating may alter the memory state or phase of the
layer 78, in one embodiment. Altering the phase or state of the
phase change layer 78 may alter the electrical characteristic of
memory material, e.g., the resistance of the material may be
altered by altering the phase of the memory material. Memory
material may also be referred to as a programmable resistive
material.
[0055] In the "reset" state, memory material may be in an amorphous
or semi-amorphous state and in the "set" state, memory material may
be in a crystalline or semi-crystalline state. The resistance of
memory material in the amorphous or semi-amorphous state may be
greater than the resistance of memory material in the crystalline
or semi-crystalline state. It is to be appreciated that the
association of reset and set with amorphous and crystalline states,
respectively, is a convention and that at least an opposite
convention may be adopted.
[0056] Using electrical current, memory material may be heated to a
relatively higher temperature to amorphize memory material and
"reset" memory material (e.g., program memory material to a logic
"0" value). Heating the volume of memory material to a relatively
lower crystallization temperature may crystallize memory material
and "set" memory material (e.g., program memory material to a logic
"1" value). Various resistances of memory material may be achieved
to store information by varying the amount of current flow and
duration through the volume of memory material.
[0057] Turning to FIG. 26, a portion of a system 100 in accordance
with an embodiment of the present invention is described. System
100 may be used in wireless devices such as, for example, a
personal digital assistant (PDA), a laptop or portable computer
with wireless capability, a web tablet, a wireless telephone, a
pager, an instant messaging device, a digital music player, a
digital camera, or other devices that may be adapted to transmit
and/or receive information wirelessly. System 100 may be used in
any of the following systems: a wireless local area network (WLAN)
system, a wireless personal area network (WPAN) system, a cellular
network, although the scope of the present invention is not limited
in this respect.
[0058] System 100 may include a controller 110, an input/output
(I/0) device 120 (e.g. a keypad, display), static random access
memory (SRAM) 160, a memory 130, and a wireless interface 140
coupled to each other via a bus 150. A battery 180 may be used in
some embodiments. It should be noted that the scope of the present
invention is not limited to embodiments having any or all of these
components.
[0059] Controller 110 may comprise, for example, one or more
microprocessors, digital signal processors, microcontrollers, or
the like. Memory 130 may be used to store messages transmitted to
or by system 100. Memory 130 may also optionally be used to store
instructions that are executed by controller 110 during the
operation of system 100, and may be used to store user data. Memory
130 may be provided by one or more different types of memory. For
example, memory 130 may comprise any type of random access memory,
a volatile memory, a non-volatile memory such as a flash memory
and/or a memory discussed herein.
[0060] I/O device 120 may be used by a user to generate a message.
System 100 may use wireless interface 140 to transmit and receive
messages to and from a wireless communication network with a radio
frequency (RF) signal. Examples of wireless interface 140 may
include an antenna or a wireless transceiver, although the scope of
the present invention is not limited in this respect.
[0061] In the foregoing specification, various embodiments of the
invention have been described. It will, however, be evident that
various modifications and changes may be made thereto without
departing from the broader spirit and scope of the invention as set
forth in the appended claims. The specification and drawings are,
accordingly, to be regarded in an illustrative sense rather than a
restrictive sense. It is intended that the appended claims cover
all such modifications and variations as fall within the true
spirit and scope of the present invention.
* * * * *