U.S. patent application number 14/253725 was filed with the patent office on 2015-03-19 for amoled display device and driving method thereof.
This patent application is currently assigned to Samsung Display Co., Ltd.. The applicant listed for this patent is Samsung Display Co., Ltd.. Invention is credited to Bo Yeon KIM, Oh Jo KWON, Choong Sun SHIN.
Application Number | 20150077314 14/253725 |
Document ID | / |
Family ID | 52667488 |
Filed Date | 2015-03-19 |
United States Patent
Application |
20150077314 |
Kind Code |
A1 |
KIM; Bo Yeon ; et
al. |
March 19, 2015 |
AMOLED DISPLAY DEVICE AND DRIVING METHOD THEREOF
Abstract
A display device is disclosed. In one aspect, the display device
includes a plurality of pixels, a plurality of data lines
respectively connected to the pixels, and a compensation unit
connected to at least one the data lines. The compensation unit
includes a first capacitor storing a leakage current of a pixel
connected to the data line, a second capacitor storing a difference
current, where the difference current is the difference between a
reference current and a pixel current measured when a data signal
of a reference gray signal is applied to the pixel. The
compensation unit also includes a comparator outputting a
difference value between the voltages stored in the first and
second capacitors. According to embodiments, is possible to measure
an accurate pixel current regardless of a leakage current and
accurately detect deterioration of a pixel.
Inventors: |
KIM; Bo Yeon; (Seoul,
KR) ; KWON; Oh Jo; (Suwon-si, KR) ; SHIN;
Choong Sun; (Yongin-si, KR) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Samsung Display Co., Ltd. |
Yongin-City |
|
KR |
|
|
Assignee: |
Samsung Display Co., Ltd.
Yongin-City
KR
|
Family ID: |
52667488 |
Appl. No.: |
14/253725 |
Filed: |
April 15, 2014 |
Current U.S.
Class: |
345/76 |
Current CPC
Class: |
G09G 3/3233 20130101;
G09G 2320/045 20130101; G09G 2300/0842 20130101 |
Class at
Publication: |
345/76 |
International
Class: |
G09G 3/32 20060101
G09G003/32 |
Foreign Application Data
Date |
Code |
Application Number |
Sep 13, 2013 |
KR |
10-2013-0110680 |
Claims
1. An organic light-emitting diode (OLED) display device,
comprising: a plurality of pixels; a plurality of data lines
respectively connected to the pixels; and a compensation unit
connected to at least one of the data lines, wherein the
compensation unit includes: a first capacitor configured to store a
leakage current of a pixel connected to a corresponding data line;
a second capacitor configured to store a difference current,
wherein the difference current is defined as the difference between
a reference current and a current measured when a reference gray
signal is applied to the pixel; and a comparator configured to
output a voltage difference, wherein the voltage difference value
is defined as the difference between the voltages stored in the
first and second capacitors.
2. The display device of claim 1, wherein the compensation unit
further includes: a first transistor including a gate electrode
connected to a first node, a first electrode connected to a high
level voltage, and a second electrode connected to a second node; a
second transistor including a gate electrode connected to the first
node, a first electrode connected to the second node, and a second
electrode connected to a third node; and a third transistor
including a gate electrode configured to receive a first switching
control signal, a first electrode connected to a corresponding data
line, and a second electrode connected to the second node, wherein
the first and second capacitors are connected to the third
node.
3. The display device of claim 2, wherein the first transistor is a
p-channel field effect transistor and wherein the second transistor
is an n-channel field effect transistor.
4. The display device of claim 2, wherein the compensation unit
further includes a first differential amplifier including a first
input terminal connected to the second node, a second input
terminal configured to receive a reference voltage, and an output
terminal connected to the first node.
5. The display device of claim 4, wherein the compensation unit
further includes: a fourth transistor including a gate electrode
configured to receive a second switching control signal, a first
electrode, and a second electrode connected to the third node; and
a second differential amplifier including a first input terminal
configured to receive a reset voltage, a second input terminal
connected to the first electrode of the fourth transistor, and an
output terminal connected the first electrode of the fourth
transistor.
6. The display device of claim 5, wherein the compensation unit
further includes a sixth transistor including a gate electrode
configured to receive a fourth switching control signal, a first
electrode connected to the third node, and a second electrode
connected to the first capacitor.
7. The display device of claim 6, wherein the compensation unit
further includes a seventh transistor including a gate electrode
configured to receive a fifth switching control signal, a first
electrode connected to the third node, and a second electrode
connected to the second capacitor.
8. The display device of claim 7, wherein the comparator includes:
a first input terminal connected to the second capacitor; a second
input terminal connected to the first capacitor; and an output
terminal configured to output the voltage difference value.
9. The display device of claim 8, wherein the compensation unit
further includes: a fifth transistor including a gate electrode
configured to receive a third switching control signal, a first
electrode connected to the third node and a second electrode; and a
bias circuit connected between the second electrode of the fifth
transistor and ground, wherein the bias circuit is configured to
control a predetermined current to flow from the third node to the
ground when the fifth transistor is turned on.
10. The display device of claim 9, wherein each pixel includes an
organic light-emitting diode (OLED) having an operation point at
which the OLED begins to emit light and wherein the reference
voltage is a voltage corresponding to the operation point of the
OLED included in the pixel.
11. The display device of claim 10, wherein each pixel further
includes a driving transistor, wherein the driving transistor is
configured to apply the reference current to the pixel, and wherein
the predetermined current is substantially the same as the
reference current.
12. The display device of claim 11, wherein the compensation unit
comprises a plurality of compensation units respectively connected
to the data lines.
13. The display device of claim 1, further comprising a multiplexor
(MUX) configured to selectively connect the compensation unit to
each of the data lines.
14. The display device of claim 8, wherein the compensation unit
further includes: a fifth transistor including a gate electrode
configured to receive a third switch control signal, a first
electrode connected to the high level voltage, and a second
electrode; and a bias circuit connected between the second
electrode of the fifth transistor and the second node, wherein the
bias circuit is configured to control a predetermined current to
flow from the high level voltage to the second node when the fifth
transistor is turned on.
15. The display device of claim 14, wherein each pixel includes an
organic light-emitting diode (OLED) having an operation point at
which the OLED begins to emit light and wherein the reference
voltage is a voltage lower than the operation point of the OLED
included in the pixel.
16. A method of driving an organic light-emitting diode (OLED)
display device including a plurality of pixels, first and second
capacitors, and a plurality of data lines respectively connected to
the pixels, each of the data lines including a parasitic capacitor,
the method comprising: charging the parasitic capacitor of a data
line to a reference voltage; storing a leakage current flowing from
the data line in the first capacitor; applying a predetermined
reference gray signal to a pixel via the data line; measuring a
current flowing from the pixel while the predetermined reference
gray signal is applied to the pixel; storing a difference current
in the second capacitor, wherein the difference current is defined
as the difference between a reference current and the measured
current; and outputting a difference value, wherein the difference
value is defined as the difference between the voltages stored in
the first and second capacitors.
17. The method of claim 16, further comprising resetting the
voltages of the first and second capacitors to a reset voltage
before charging the parasitic capacitor.
18. The method of claim 17, wherein each pixel includes an organic
light-emitting diode (OLED) having an operation point at which the
OLED begins to emit light and wherein the reference voltage is a
voltage corresponding to the operation point of the OLED included
in the pixel.
19. The method of claim 17, wherein each pixel includes an organic
light-emitting diode (OLED) having an operation point at which the
OLED begins to emit light and wherein the reference voltage is a
voltage lower than the operation point of the OLED included in the
pixel.
20. The method of claim 19, wherein the storing includes applying
the reference voltage as a voltage at which the OLED emits light at
the predetermined reference gray signal.
21. A display device, comprising: a plurality of pixels; a
compensation unit connected to at least one of the pixels and
configured to output degradation information; and a signal
controller configured to control the pixels based at least in part
on the degradation information; wherein the compensation unit is
further configured to measure a leakage current and a difference
current of the pixel, wherein the difference current is defined as
the difference between a reference current and a current of the
pixel measured when a data signal having a predetermined gray is
applied to the pixel, and wherein the compensation unit is further
configured to generate the degradation information based on at
least one of the leakage current or the difference current.
22. The display device of claim 21, wherein the compensation unit
comprises: a first capacitor configured to store the leakage
current; a second capacitor configured to store the difference
current; and a comparator configured to compare the leakage current
and the difference current, and output the difference as the
degradation information.
23. The display device of claim 22, wherein the compensation unit
further includes: a first transistor including a gate electrode
connected to a first node, a first electrode connected to a high
level voltage, and a second electrode connected to a second node; a
second transistor including a gate electrode connected to the first
node, a first electrode connected to the second node, and a second
electrode connected to a third node; and a third transistor
including a gate electrode configured to receive a first switching
control signal, a first electrode connected to a corresponding data
line, and a second electrode connected to the second node, wherein
the first and second capacitors are connected to the third node.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application claims priority to and the benefit of
Korean Patent Application No. 10-2013-0110680 filed in the Korean
Intellectual Property Office on Sep. 13, 2013, the entire contents
of which are incorporated herein by reference.
BACKGROUND
[0002] 1. Field
[0003] The described technology generally relates to a display
device and a driving method thereof.
[0004] 2. Description of the Related Technology
[0005] Organic light-emitting diode (OLED) displays use OLEDs in
which luminance is controlled by a current or a voltage. OLEDs
generally include an anode layer and a cathode layer for generating
an electric field, and an organic light-emitting material which can
emit light due to the electric field.
[0006] OLED displays can be classified into passive matrix OLED
(PMOLED) and active matrix OLED (AMOLED) displays according to
their driving method.
[0007] The use of AMOLED displays has become widespread since these
displays can emit light for each unit pixel with a favorable
resolution, contrast, and refresh rate.
[0008] Due to their use of organic materials, OLEDs degrade over
time. The amount of light emitted in a degraded OLED can vary over
an initial driving period due to variation in pixel current.
Accordingly, image quality of an OLED display degrades with
time.
SUMMARY OF CERTAIN INVENTIVE ASPECTS
[0009] One inventive aspect is a display device and a driving
method thereof capable of accurately measuring a pixel current.
[0010] Another aspect is a display device and a driving method
thereof having the advantages of accurately detecting the
degradation of a pixel by measuring an accurate pixel current
regardless of a leakage current.
[0011] Another aspect is a display device including a plurality of
pixels, a plurality of data lines respectively connected to the
pixels, and a compensation unit connected to at least one of the
data lines, in which the compensation unit includes a first
capacitor storing a leakage current of the data line, a second
capacitor storing a difference current obtained by subtracting a
reference current from a pixel current measured when a data signal
of a reference gray signal is applied to the data line, and a
comparator outputting a difference value between the voltages
stored in the first and second capacitors.
[0012] The compensation unit may further include a first transistor
including a gate electrode connected to a first node, a first
electrode connected to a high level voltage, and a second electrode
connected to a second node, a second transistor including a gate
electrode connected to the first node, a first electrode connected
to the second node, and a second electrode connected to a third
node, and a third transistor including a gate electrode receiving a
first switching control signal, a first electrode connected to the
data line, and a second electrode connected to the second node, in
which the first and second capacitors may be connected to the third
node.
[0013] The first transistor may be a p-channel field effect
transistor and the second transistor may be an n-channel field
effect transistor.
[0014] The degradation compensating unit may further include a
first differential amplifier including a first input terminal
connected to the second node, a second input terminal receiving a
reference voltage, and an output terminal connected to the first
node.
[0015] The compensation unit may further include a fourth
transistor including a gate electrode receiving a second switching
control signal, a first electrode, and a second electrode connected
to the third node, and a second differential amplifier including a
first input terminal receiving a reset voltage, a second input
terminal connected to the first electrode of the fourth transistor,
and an output terminal connected to the first electrode of the
fourth transistor.
[0016] The compensation unit may further include a sixth transistor
including a gate electrode receiving a fourth switching control
signal, a first electrode connected to the third node, and a second
electrode connected to the first capacitor.
[0017] The compensation unit may further include a seventh
transistor including a gate electrode receiving a fifth switching
control signal, a first electrode connected to the third node, and
a second electrode connected to the second capacitor.
[0018] The comparator may include a first input terminal connected
to the second capacitor, a second input terminal connected to the
first capacitor, and an output terminal outputting the difference
value.
[0019] The compensation unit may further include a fifth transistor
including a gate electrode receiving a third switching control
signal, a first electrode connected to the third node, and a second
electrode, and a bias circuit connected between the second
electrode of the fifth transistor and ground, and controlling a
predetermined current to flow from the third node to the ground
when the fifth transistor is turned on.
[0020] The reference voltage may be a voltage corresponding to an
operation point of an OLED included in the pixel connected to the
data line.
[0021] The predetermined current may be substantially the same as a
reference current flowing through a driving transistor included in
the pixel when applied with the data signal of the reference gray
signal.
[0022] A plurality of compensation units may be provided and be
respectively connected to the data lines.
[0023] The display device may further include a multiplexor (MUX)
selectively connecting the compensation unit to the data lines.
[0024] The compensation unit may further include a fifth transistor
including a gate electrode receiving a third switch control signal,
a first electrode connected to the high level voltage, and a second
electrode, and a bias circuit connected between the second
electrode of the fifth transistor and the second node to control a
predetermined current to flow from the high level voltage to the
second node when the fifth transistor is turned on.
[0025] The reference voltage may be a voltage lower than an
operation point of the OLED included in the pixel connected to the
corresponding data line.
[0026] Another aspect is a method of driving a display device
including charging a parasitic capacitor of a data line to a
reference voltage, storing a leakage current flowing from the data
line in a first capacitor, applying a data signal having a
predetermined reference gray signal to the pixel connected to the
data line, measuring a current flowing from the pixel while the
predetermined reference gray signal is applied to the pixel,
storing a difference current obtained by subtracting a reference
current from the measured current in a second capacitor, and
outputting a difference value between the voltages stored in the
first and second capacitors.
[0027] The method may further include resetting the voltages of the
first and second capacitors to a reset voltage before the charging
of the parasitic capacitor.
[0028] The reference voltage may be a voltage corresponding to an
operation point of an OLED included in the pixel.
[0029] The reference voltage may be a voltage lower than an
operation point of an OLED included in the pixel.
[0030] The charging of the difference current may include applying
the reference voltage as a voltage at which the OLED emits light at
the predetermined reference gray signal.
[0031] Another aspect is a display device including a plurality of
pixels, a compensation unit connected to at least one of the pixels
and configured to output degradation information, and a signal
controller configured to control the pixels based at least in part
on the degradation information, wherein the compensation unit is
further configured to measure a leakage current and a difference
current of the pixel, wherein the difference current is defined as
the difference between a reference current and a current of the
pixel measured when a data signal having a predetermined gray is
applied to the pixel, and wherein the compensation unit is further
configured to generate the degradation information based on at
least one of the leakage current or the difference current.
[0032] The compensation unit may include a first capacitor
configured to store the leakage current, a second capacitor
configured to store the difference current, and a comparator
configured to compare the leakage current and the difference
current, and output the difference as the degradation
information.
[0033] The compensation unit may further include a first transistor
including a gate electrode connected to a first node, a first
electrode connected to a high level voltage, and a second electrode
connected to a second node, a second transistor including a gate
electrode connected to the first node, a first electrode connected
to the second node, and a second electrode connected to a third
node, and a third transistor including a gate electrode configured
to receive a first switching control signal, a first electrode
connected to a corresponding data line, and a second electrode
connected to the second node, wherein the first and second
capacitors are connected to the third node.
[0034] According to at least one embodiment, it is possible to
measure a pixel current accurately regardless of a leakage current
as well as accurately detect the degradation of a pixel.
BRIEF DESCRIPTION OF THE DRAWINGS
[0035] FIG. 1 is a block diagram illustrating a display device
according to an exemplary embodiment.
[0036] FIG. 2 is a circuit diagram illustrating a pixel according
to an exemplary embodiment.
[0037] FIG. 3 is a circuit diagram illustrating a pixel according
to another exemplary embodiment.
[0038] FIG. 4 is a circuit diagram illustrating a compensation unit
according to an exemplary embodiment.
[0039] FIG. 5 is a circuit diagram illustrating a compensation unit
according to another exemplary embodiment.
[0040] FIG. 6 is a block diagram illustrating a connection
configuration of the compensation unit and a plurality of data
lines according to an exemplary embodiment.
[0041] FIG. 7 is a block diagram illustrating a connection
configuration of the compensation unit and a plurality of data
lines according to another exemplary embodiment.
[0042] FIG. 8 is a flowchart illustrating an exemplary operation or
procedure for driving an AMOLED display device according to an
embodiment.
DETAILED DESCRIPTION OF CERTAIN INVENTIVE EMBODIMENTS
[0043] Various methods for compensating aged OLEDs have been
developed. One step of these methods includes measuring a pixel
current. Generally, when measuring pixel current, leakage current
is included in the measured current. An accurate pixel current can
be measured by compensating for the leakage current in the measured
current, however, it is not easy to accurately measure leakage
current.
[0044] Additionally, larger OLED displays are being developed, and
as a result, the resistance and capacitance of components of the
display increases. Consequently, the time required to measure the
pixel current increases. Finally, it can be difficult to accurately
detect the light emitting capability of an OLED based only on
measuring the pixel current.
[0045] The described technology will be described more fully
hereinafter with reference to the accompanying drawings, in which
exemplary embodiments of the described technology are shown. As
those skilled in the art would realize, the described embodiments
may be modified in various different ways, all without departing
from the spirit or scope of the described technology.
[0046] Further, in exemplary embodiments, since like reference
numerals designate like elements having the same configuration, a
first exemplary embodiment is representatively described, and in
other exemplary embodiments, only those configurations different
from the first exemplary embodiment will be described.
[0047] The drawings and description are to be regarded as
illustrative in nature and not restrictive, and like reference
numerals designate like elements throughout the specification.
[0048] Throughout this specification and the claims that follow,
when it is described that an element is "coupled" or "connected" to
another element, the element may be "directly coupled" or "directly
connected" to the other element or "coupled" or "connected" to the
other element through a third element. As used herein, the term
"connected" includes the term "electrically connected." In
addition, unless explicitly described to the contrary, the word
"comprise" and variations such as "comprises" or "comprising," will
be understood to imply the inclusion of stated elements but not the
exclusion of any other elements.
[0049] FIG. 1 is a block diagram illustrating a display device
according to an exemplary embodiment.
[0050] Referring to FIG. 1, a display device 10 includes a signal
controller 100, a scan driver 200, a data driver 300, a power
supply unit (or power supply) 400, a display unit (or display
panel) 500, and a compensation unit 600.
[0051] The signal controller 100 receives an image signal ImS and a
synchronization signal from an external device. The image signal
ImS includes luminance information for a plurality of pixels. The
luminance has a predetermined number of grays, for example,
1024(=2.sup.10), 256(=2.sup.8) or 64(=2.sup.6) grays. The
synchronization signal includes a horizontal synchronization signal
Hsync, a vertical synchronization signal Vsync, and a main clock
signal MCLK.
[0052] The signal controller 100 generates first to fourth driving
control signals CONT1 to CONT4 and an image data signal ImD
according to the image signal ImS, the horizontal synchronization
signal Hsync, the vertical synchronization signal Vsync, and the
main clock signal MCLK. The signal controller 100 divides the image
signal ImS by a frame unit according to the vertical
synchronization signal Vsync and divides the image signal ImS by a
scan line unit according to the horizontal synchronization signal
Hsync to generate image data ImD. The signal controller 100
transfers the image data ImD to the data driver 300 together with
the first driving control signal CONT1.
[0053] The display unit 500 is a display area including a plurality
of pixels. In the display unit 500, a plurality of scan lines
extended in a row direction to be substantially parallel to each
other and a plurality of data lines extended in a column direction
to be substantially parallel to each other. The display unit 500
also includes a plurality of sensing lines extended in a row
direction to be substantially parallel to each other and a
plurality of power lines are formed to be connected to the pixels.
The pixels are arranged in a matrix arrangement.
[0054] The scan driver 200 is connected to the scan lines to
generate a plurality of scanning signals S[1] to S[n] according to
the second driving control signal CONT2. The scan driver 200
sequentially applies the scanning signals S[1] to S[n] including
gate-on voltages to the scan lines.
[0055] The data driver 300 is connected to the data lines to sample
and hold the image data ImD according to the first driving control
signal CONT1 and respectively apply a plurality of data signals
data[1] to data[m] to the data lines. The data driver 300 may apply
the data signals data[1] to data[m] having a predetermined voltage
range to the data lines in response to the scanning signals S[1] to
S[n].
[0056] The power supply unit 400 determines the levels of a first
power voltage ELVDD and a second power voltage ELVSS according to a
third driving control signal CONT3 and supplies the first and
second power voltages ELVDD and ELVSS to the power lines connected
to the pixels. The first and second power voltages ELVDD and ELVSS
provide driving currents to the pixels.
[0057] The compensation unit 600 is connected to the sensing lines
and generates a plurality of sensing signals SE[1] to SE[n]
according to a fourth driving control signal CONT4. The
compensation unit 600 sequentially applies the sensing signals
SE[1] to SE[n] having gate-on voltages. The compensation unit 600
is connected to the data lines to measure a measured current Isense
flowing through the data lines.
[0058] According to some embodiments, the data driver 300 is
connected to one end of the data lines and the compensation unit
600 is connected to the other end of the data lines.
[0059] The compensation unit 600 measures the respective degree of
degradation for each of the pixels by using the measured current
Isense and transfers degradation information Deg indicating the
degree of degradation to the signal controller 100.
[0060] The signal controller 100 reflects the degradation
information Deg of the pixels in generating the image data ImD.
[0061] The aforementioned driving devices 100, 200, 300, 400, and
600 may be directly installed on the display unit 500 in at least
one IC chip form, installed on a flexible printed circuit film,
attached to the display unit 500 in a tape carrier package (TCP)
form, installed on a separate printed circuit board (PCB), or
integrated on the display unit 500.
[0062] FIG. 2 is a circuit diagram illustrating a pixel according
to an exemplary embodiment.
[0063] Referring to FIG. 2, a pixel PX positioned in an i-th row
and a j-th column from among the pixels included in the display
device 10 is illustrated (1.ltoreq.i.ltoreq.n,
1.ltoreq.j.ltoreq.m).
[0064] The pixel PX includes an organic light-emitting diode (OLED)
and a pixel circuit 10 for controlling the OLED. The pixel circuit
10 includes a switching transistor M1, a driving transistor M2, a
sensing transistor M3, and a storage capacitor Cst.
[0065] The switching transistor M1 includes a gate electrode
connected to the scan line Si, one end connected to the data line
Dj, and another end connected to the gate electrode of the driving
transistor M2.
[0066] The driving transistor M2 includes a gate electrode
connected to the other end of the switching transistor M1, one end
connected to the first power voltage ELVDD, and another end
connected to the OLED.
[0067] The sensing transistor M3 includes a gate electrode
connected to the sensing line SEi, one end connected to the other
end of the driving transistor M2, and another end connected to the
data line Dj.
[0068] The storage capacitor Cst includes one end connected to the
gate electrode of the driving transistor M2 and another end
connected to the first power voltage ELVDD. The storage capacitor
Cst is charged with a data voltage applied to the gate electrode of
the driving transistor M2 and maintains the charged data voltage
even after the switching transistor M1 is turned off.
[0069] The OLED includes an anode connected to the other end of the
driving transistor M2 and a cathode connected to the second power
voltage ELVSS. The OLED includes an organic emission layer which
emits light having a primary color. An example of the primary
colors may include three primary colors such as red, green, and
blue, and a desired color may be displayed by a spatial or temporal
sum of the three primary colors.
[0070] The organic emission layer may be made of a low-molecular
organic material or a high-molecular organic material such as poly
3,4-ethylenedioxythiophene (PEDOT). Further, the organic emission
layer may be formed as a multilayer including a light emitting
layer, and one or more of a hole injection layer (HIL), a hole
transporting layer (HTL), an electron transporting layer (ETL), and
an electron injection layer (EIL). In the case where the organic
emission layer includes all of the layers, the hole injection layer
(HIL) is disposed on a pixel electrode which is an anode, and the
hole transporting layer (HTL), the light emitting layer, the
electron transporting layer (ETL), and the electron injection layer
(EIL) are sequentially laminated thereon.
[0071] The organic emission layer may include a red organic
emission layer emitting red light, a green organic emission layer
emitting green light, and a blue organic emission layer emitting
blue light. The red, green, and blue organic emission layers are
respectively formed in red, green, and blue pixels, thereby
implementing a color image.
[0072] Further, the organic emission layer may implement the color
image by laminating each of the red, green, and blue organic
emission layers together in each of the red, green, and blue
pixels, and respectively forming red, green, and blue color filters
for each pixel. As another example, white organic emission layers
emitting white light are formed in each the red, green, and blue
pixels and red, green, and blue color filters are respectively
formed for each pixel, thereby implementing the color image. In
this case, a deposition mask for respectively depositing each of
the red, green, and blue organic emission layers in the
corresponding pixels is not required.
[0073] The white organic emission layer described in another
example may be formed as a single organic emission layer or may
include a configuration formed so as to emit white light by
laminating a plurality of organic emission layers. For example, the
white organic emission layer may include a configuration which may
emit white light by combining at least one of each of yellow and
blue organic emission layers, a configuration which may emit white
light by combining at least one of each of cyan and red organic
emission layers, a configuration which may emit white light by
combining at least one of each of magenta and green organic
emission layers, and the like.
[0074] Each of the switching, driving, and sensing transistors M1
to M3 may be p-channel field effect transistors. In this case, the
gate-on voltages turning on each of the switching driving and
sensing transistors M1 to M3 are low level voltages and the
gate-off voltages turning off each of the transistors are high
level voltages.
[0075] Herein, p-channel field effect transistors are illustrated,
but at least one of the switching driving or sensing transistors M!
to M3 may be an n-channel field effect transistor. In this case,
the gate-on voltage turning on the n-channel field effect
transistor is a high level voltage, and the gate-off voltage
turning off the n-channel field effect transistor is a low level
voltage.
[0076] When the scanning signal S [i] of the gate-on voltage is
applied to the scan line Si, the switching transistor M1 is turned
on, and the data signal applied to the data line Dj is applied to
one end of the storage capacitor Cst through the turned-on
switching transistor M1 to charge the storage capacitor Cst. The
driving transistor M2 controls a pixel current which flows from the
first power voltage ELVDD to the OLED in response to the voltage
charged in the storage capacitor Cst. The OLED emits light
corresponding to magnitude of the pixel current flowing through the
driving transistor M2.
[0077] During normal driving when the display device 10 displays an
image, the sensing signal SE[i] of the gate-off voltage is applied
to the sensing line SEi and the sensing transistor M3 is turned
off.
[0078] Meanwhile, during compensation driving when the display
device 10 measures the pixel current of each of the pixels PX in
order to compensate for the degradation of the pixels PX, the
sensing signal SE[i] of the gate-on voltage is applied to the
sensing line SEi and the sensing transistor M3 is turned on. The
pixel current flows to the data line Dj through the turned-on
sensing transistor M3.
[0079] FIG. 3 is a circuit diagram illustrating a pixel according
to another exemplary embodiment.
[0080] Referring to FIG. 3, among the pixels included in the
display device 10, a first pixel PX1 positioned in an i-th row and
a j-th column and a second pixel PX2 positioned in the i-th row and
a j+1-th column are illustrated (1.ltoreq.i.ltoreq.n,
1.ltoreq.j.ltoreq.m-1).
[0081] In contrast to the embodiment of FIG. 2, the sensing
transistor M3 of this circuit is not connected between the driving
transistor M2 and the data line Dj applying the data signal to the
corresponding pixel; but the sensing transistor M3 is connected
between the driving transistor M2 and a data line Dj+1 applying a
data signal to an adjacent pixel.
[0082] That is, the sensing transistor M3 includes a gate electrode
connected to the sensing line SEi, one end connected to the other
end of the driving transistor M2, and another end connected to the
data line Dj+1 of the adjacent pixel.
[0083] Due to this configuration, during compensation driving of
the display device 10, the sensing signal SE[i] of the gate-on
voltage is applied to the sensing line SEi and thus the pixel
current flows to the data line Dj+1 of the adjacent pixel through
the turned-on sensing transistor M3.
[0084] Since other constituent elements are the same as those
described in FIG. 2, descriptions thereof will be omitted.
[0085] The aforementioned pixels in FIGS. 2 and 3 represent
exemplary embodiments of the structure of the pixels and a proposed
degradation compensating method is not limited to the structure of
the pixels. The display device 10 may include pixels having various
structures and the proposed degradation compensating method may be
applied to a display device 10 including pixels having various
structures.
[0086] Hereinafter, a detailed configuration and an operation of
the compensation unit 600 will be described.
[0087] FIG. 4 is a circuit diagram illustrating a compensation unit
according to an exemplary embodiment.
[0088] Referring to FIG. 4, the compensation unit 600 includes a
plurality of transistors M11 to M17, a first differential amplifier
Amp1, a second differential amplifier Amp2, a bias circuit Ibias, a
first capacitor C1, a second capacitor C2, and a comparator
COMP.
[0089] The first transistor M11 includes a gate electrode connected
to a first node N11, one electrode connected to a high level
voltage VGH, and another electrode connected to a second node
N12.
[0090] The second transistor M12 includes a gate electrode
connected to the first node N11, one electrode connected to the
second node N12, and another electrode connected to a third node
N13.
[0091] The third transistor M13 includes a gate electrode receiving
a first switching control signal SWC1, one electrode connected to
the data line Dj, and another electrode connected to the second
node N12.
[0092] The fourth transistor M14 includes a gate electrode
receiving a second switching control signal SWC2, one electrode
connected to an output terminal of the second differential
amplifier Amp2, and another electrode connected to the third node
N13.
[0093] The fifth transistor M15 includes a gate electrode receiving
a third switching control signal SWC3, one electrode connected to
the third node N13, and another electrode connected to the bias
circuit Ibias.
[0094] The sixth transistor M16 includes a gate electrode receiving
a fourth switching control signal SWC4, one electrode connected to
the third node N13, and another electrode connected to the first
capacitor C1.
[0095] The seventh transistor M17 includes a gate electrode
receiving a fifth switching control signal SWC5, one electrode
connected to the third node N13, and another electrode connected to
the second capacitor C2.
[0096] The first differential amplifier Amp1 includes a first input
terminal (+) connected to the second node N12, a second input
terminal (-) receiving a reference voltage Vset, and an output
terminal connected to the first node N11.
[0097] The second differential amplifier Amp2 includes a first
input terminal (+) receiving a reset voltage Vcmp, a second input
terminal (-) connected to the one electrode of the fourth
transistor M14, and an output terminal connected to the one
electrode of the fourth transistor M14.
[0098] The bias circuit Ibias is connected between the other
electrode of the fifth transistor M15 and a ground, and generates a
predetermined current which flows from the third node N13 to the
ground when the fifth transistor M15 is turned on.
[0099] The first capacitor C1 includes one electrode connected to
the other electrode of the sixth transistor M16 and the other
electrode connected to the ground.
[0100] The second capacitor C2 includes one electrode connected to
the other electrode of the seventh transistor M17 and the other
electrode connected to the ground.
[0101] The comparator COMP includes a first input terminal (+)
connected to the one electrode of the second capacitor C2, a second
input terminal (-) connected to the one electrode of the first
capacitor C1, and an output terminal outputting the degradation
information Deg.
[0102] The first transistor M11 may be a p-channel field effect
transistor, and the second transistor M12 may be an n-channel field
effect transistor. Alternatively, when the first transistor M11 is
an n-channel field effect transistor, the second transistor M12 may
be a p-channel field effect transistor. The other transistors M13
to M17 may be p-channel field effect transistors. Alternatively,
the other transistors M13 to M17 may be n-channel field effect
transistors. A gate-on voltage turning on the p-channel field
effect transistor is a low level voltage, and a gate-off voltage
turning off the p-channel field effect transistor is a high level
voltage. A gate-on voltage turning on the n-channel field effect
transistor is a high level voltage, and a gate-off voltage turning
off the n-channel field effect transistor is a low level
voltage.
[0103] The transistors M11 to M17 may be oxide thin film
transistors (oxide TFTs) in which semiconductor layers are made of
oxide semiconductors.
[0104] The oxide semiconductor may include one of an oxide based on
titanium (Ti), hafnium (Hf), zirconium (Zr), aluminum (Al),
tantalum (Ta), germanium (Ge), zinc (Zn), gallium (Ga), tin (Sn) or
indium (In), and complex oxides thereof such as zinc oxide (ZnO),
indium-gallium-zinc oxide (InGaZnO.sub.4), indium zinc oxide
(In--Zn--O), zinc-tin oxide (Zn--Sn--O), indium gallium oxide
(In--Ga--O), indium-tin oxide (In--Sn--O), indium-zirconium oxide
(In--Zr--O), indium-zirconium-zinc oxide (In--Zr--Zn--O)
indium-zirconium-tin oxide (In--Zr--Sn--O),
indium-zirconium-gallium oxide (In--Zr--Ga--O), indium-aluminum
oxide (In--Al--O), indium-zinc-aluminum oxide (In--Zn--Al--O),
indium-tin-aluminum oxide (In--Sn--Al--O), indium-aluminum-gallium
oxide (In--Al--Ga--O), indium-tantalum oxide (In--Ta--O),
indium-tantalum-zinc oxide (In--Ta--Zn--O), indium-tantalum-tin
oxide (In--Ta--Sn--O), indium-tantalum-gallium oxide
(In--Th--Ga--O), indium-germanium oxide (In--Ge--O),
indium-germanium-zinc oxide (In--Ge--Zn--O), indium-germanium-tin
oxide (In--Ge--Sn--O), indium-germanium gallium oxide
(In--Ge--Ga--O), titanium-indium-zinc oxide (Ti--In--Zn--O), and
hafnium-indium-zinc oxide (Hf--In--Zn--O).
[0105] The semiconductor layer includes a channel region in which
impurities are not doped, and a source region and a drain region
formed when impurities are doped in two sides of the channel
region. Herein, the impurities vary according to a kind of the thin
film transistor, and may be N-type impurities or P-type
impurities.
[0106] In the case where the semiconductor layer is formed of an
oxide semiconductor, in order to protect the oxide semiconductor
which may be vulnerable to ambient environmental conditions, or
when exposed to a high temperature, a separate passivation layer
may be added.
[0107] Next, the operation of the compensation unit 600 will be
described. The compensation unit 600 may generate the first to
fifth switching control signals SWC1 to SWC5 according to a fourth
driving control signal CONT4 applied from the signal controller
100.
[0108] For a first period, the second fourth, and fifth switching
control signals SWC2, SWC4, and SWC5 are applied as the gate-on
voltage. In this case, the first and third switching control
signals SWC1 and SWC3 are applied as the gate-off voltage. The
fourth, sixth, and seventh transistors M14, M16, and M17 are turned
on. When the fourth transistor M14 is turned on, the second
differential amplifier Amp2 is enabled. Accordingly, the first
capacitor C1 is charged by the reset voltage Vcmp through the
turned-on sixth transistor M16, and the second capacitor C2 is
charged by the reset voltage Vcmp through the turned-on seventh
transistor M17. The first period may be a period for resetting the
first and second capacitors C1 and C2 to the reset voltage
Vcmp.
[0109] For a second period, the second, fourth, and fifth switching
control signals SWC2, SWC4, and SWC5 are applied as the gate-off
voltage, and the first and third switching control signals SWC1 and
SWC3 are applied as the gate-on voltage. In this case, the sensing
signal SE[i] of the gate-on voltage may be applied to the gate
electrode of the sensing transistor M3 included in the pixel PX
connected to the data line Dj. In addition, a data signal having a
voltage corresponding to an operation point of the OLED may be
applied to the gate electrode of the driving transistor M2. The
operation point refers to the minimum current or voltage at which
the OLED begins to emit light. For example, a data signal of a
black gray level may be applied to the gate electrode of the
driving transistor M2. Further, a data signal of a predetermined
gray level higher than black can also be applied to the gate
electrode of the driving transistor M2.
[0110] As the first and third switching control signals SWC1 and
SWC3 are turned on, the voltage of the second node N12 becomes the
reference voltage Vset. The voltage of the second node N12 is
stored in a parasitic capacitor Cda of the data line Dj. The
reference voltage Vset is a voltage corresponding to an operation
point of the OLED included in the pixel PX. That is, the parasitic
capacitor Cda of the data line Dj is charged by the voltage
corresponding to an operation point of the OLED.
[0111] For example, in the case where the voltage of the second
node N12 is lower than the reference voltage Vset, a low level
voltage is output from the first differential amplifier Amp1 to the
first node N11. When the voltage of the first node N11 becomes the
low level voltage, the first transistor M11 is turned on, and the
current flows from the high level voltage VGH to the second node
N12 through the turned-on first transistor M11. The voltage of the
second node N12 then rises by the current flowing through the first
transistor M11.
[0112] In the case where the voltage of the second node N12 is
higher than the reference voltage Vset, a high level voltage is
output from the first differential amplifier Amp1 to the first node
N11. When the voltage of the first node N11 becomes the high level
voltage, the second transistor M12 is turned on, and the current
flows from the second node N12 to the third node N13 through the
turned-on second transistor M12. Since fifth transistor M15 is
turned on by the third switching control signal SWC3, a
predetermined current flows from the third node N13 to ground due
to the bias circuit Ibias. In other words, the bias circuit Ibias
controls the predetermined current to flow from the third node N13
to ground. That is, current flows from the second node N12 to
ground and the voltage of the second node N12 drops.
[0113] After the voltage of the second node N12 becomes the
reference voltage Vset, both the first transistor M11 and the
second transistor M12 are turned off. As a result, the voltage of
the second node N12 becomes the reference voltage Vset and the
parasitic capacitor Cda of the data line Dj is charged by the
reference voltage Vset. Thus, the second period may be a period for
pre-charging the parasitic capacitor Cda of the data line Dj by the
reference voltage Vset which is the voltage corresponding to the
operation point of the OLED.
[0114] For a third period, the first and fourth switching control
signals SWC1 and SWC4 are applied as the gate-on voltage. In this
case, the second, third, and fifth switching control signals SWC2,
SWC3, and SWC5 are applied as the gate-off voltage. The third and
sixth transistors M13 and M16 are turned on. A leakage current
I_leak in the data line Dj or the pixel PX flows to the second node
N12 through the turned-on third transistor M13 and the voltage of
the second node N12 set as the reference voltage Vset in the second
period rises by the leakage current I_leak. When the voltage of the
second node N12 rises by the leakage current I_leak, the second
transistor M12 is turned on to allow the flow of current. The
current flowing through the second transistor M12 charges the first
capacitor C1 through the turned-on sixth transistor M16. That is,
the first capacitor C1 is charged by the leakage current I_leak.
After a predetermined sampling period in the third period, the
fourth switching control signal SWC4 is applied as the gate-off
voltage and a charge corresponding to the leakage current I_leak is
maintained in the first capacitor C1. The third period may be a
period for charging the first capacitor C1 by the leakage current
I_leak.
[0115] For a fourth period, the first, third, and fifth switching
control signals SWC1, SWC3, and SWC5 are applied as the gate-on
voltage. In this case, the second and fourth switching control
signals SWC2 and SWC4 are applied as the gate-off voltage. In
addition, the data signal of a predetermined reference gray signal
is applied to the gate electrode of the driving transistor M2
included in the pixel PX and the sensing signal SE[i] of the
gate-on voltage is applied to the gate electrode of the sensing
transistor M3. The pixel current flowing through the turned-on
driving transistor M2 due to the data signal of the reference gray
signal is applied to the data line Dj as the measured current
Isense through the turned-on sensing transistor M3.
[0116] The measured current Isense flows to the second node N12
through the turned-on third transistor M13. The voltage of the
second node N12 rises by the measured current Isense and the second
transistor M12 is turned on in response to the rising voltage and
thus current flows from the second node N12 to the third node N13.
The current flowing from the second node N12 to the third node N13
is the same as the measured current Isense. That is, the measured
current Isense flows to the third node N13 through the second
transistor M12. The fifth transistor M15 is turned on by the third
switching control signal SWC3 and a predetermined current amount
flows from the third node N13 to the ground due to the bias circuit
Ibias. The bias circuit Ibias may be configured to have
substantially the same current as a reference current Iref flowing
through the turned-on driving transistor M2 by the data signal of
the reference gray signal. From the measured current Isense flowing
to the third node N13, the current amount corresponding to the
reference current Iref flows to ground through the bias circuit
Ibias and the difference current Idif (=Isense-Iref) acquired by
subtracting the reference current Iref from the measured current
Isense is stored in the second capacitor C2. After a predetermined
sampling period in the fourth period, the fifth switching control
signal SWC5 is applies as the gate-off voltage and a charge
corresponding to the difference current Idif is maintained in the
second capacitor C2. The sampling period of the third period and
the sampling period of the fourth period may be set to the same
period. The fourth period may be a period for charging the second
capacitor C2 by the difference current Idif.
[0117] For a fifth period, the difference value between the
voltages stored in the first and second capacitors C1 and C2 is
output as the degradation information Deg through the comparator
COMP. The leakage current I_leak is included in the measured
current Isense. That is, the measured current Isense may be the sum
of a pixel current Iref' flowing in the driving transistor M2 due
to the data signal of the reference gray signal and the leakage
current I_leak. When the bias circuit Ibias is configured to
generate substantially the same current as the reference current
Iref, a voltage corresponding to the difference current
Idif=Iref'=I_leak-Iref may be stored in the second capacitor C2.
Finally, the voltage output from the comparator COMP corresponds to
the difference value Deg=Iref'-Iref between the voltage stored in
the first and second capacitors C1 and C2. The degree of
degradation of the pixel may be determined by the difference value
Deg. For example, when the value of Deg is a negative value, the
pixel current Iref' flowing in the transistor M2 is decreased by
the data signal of the reference gray signal, which means that
degradation of the pixel is increased.
[0118] As such, an accurate pixel current may be measured
regardless of the leakage current, and as a result, the degradation
of the pixel may be accurately detected.
[0119] FIG. 5 is a circuit diagram illustrating a deterioration
compensating unit according to another exemplary embodiment.
[0120] In contrast to the embodiment of FIG. 4, the fifth
transistor M15 and the bias circuit Ibias included in the
compensation unit 600 are connected between the high level voltage
VGH and the second node N12.
[0121] The fifth transistor M15 includes a gate electrode receiving
a third switching control signal SWC3, one electrode connected to
the high level voltage VGH, and another electrode connected to the
bias circuit Ibias.
[0122] The bias circuit Ibias is connected between the fifth
transistor M15 and the second node N12 and when the fifth
transistor M15 is turned on, a predetermined current amount flows
from the high level voltage VGH to the second node N12.
[0123] Since other constituent elements are the same as those
described in FIG. 4, detailed descriptions thereof will be
omitted.
[0124] Next, the operation of the compensation unit 600 will be
described.
[0125] For a first period, the second, fourth, and fifth switching
control signals SWC2, SWC4, and SWC5 are applied as the gate-on
voltage. In this case, the first and third switching control
signals SWC1 and SWC3 are applied as the gate-off voltage. The
first and second capacitors C1 and C2 are charged by the reset
voltage Vcmp. The first period may be a period for resetting the
first and second capacitors C1 and C2 to the reset voltage
Vcmp.
[0126] For a second period, the second, fourth, and fifth switching
control signals SWC2, SWC4, and SWC5 are applied as the gate-off
voltage, and the first and third switching control signals SWC1 and
SWC3 are applied as the gate-on voltage. In this case, the sensing
signal SE[i] of the gate-on voltage may be applied to the gate
electrode of the sensing transistor M3 included in the pixel PX
connected to the data line Dj. As the first and third switching
control signals SWC1 and SWC3 are turned on, the voltage of the
second node N12 is set as the reference voltage Vset. The voltage
of the second node N12 is stored in a parasitic capacitor Cda of
the data line Dj. The reference voltage Vset may be a voltage lower
than an operation point of the OLED included in the pixel PX. That
is, the reference voltage Vset may be determined as a voltage
having a level in which the OLED does not emit light.
[0127] For example, in the case where the voltage of the second
node N12 is lower than the reference voltage Vset, a low level
voltage is output from the first differential amplifier Amp1 to the
first node N11. When the voltage of the first node N11 is the low
level voltage, the first transistor M11 is turned on and current
flows from the high level voltage VGH to the second node N12
through the turned-on first transistor M11. The voltage of the
second node N12 rises by the current flowing through the first
transistor M11. When the voltage of the second node N12 is higher
than the reference voltage Vset, current flows from the second node
N12 to the OLED of the pixel PX. In this case, since the reference
voltage Vset is a voltage having a level in which the OLED does not
emit light, the OLED does not emit light. That is, the current
flows from the second node N12 to the second power voltage ELVSS
connected to the cathode of the OLED, and the voltage of the second
node N12 drops.
[0128] After the voltage of the second node N12 becomes the
reference voltage Vset, and the parasitic capacitor Cda of the data
line Dj is charged by the reference voltage Vset. The second period
may be a period for pre-charging the parasitic capacitor Cda of the
data line Dj by the reference voltage Vset.
[0129] For a third period, the first and fourth switching control
signals SWC1 and SWC4 are applied as the gate-on voltage. In this
case, the second, third and fifth switching control signals SWC2,
SWC3, and SWC5 are applied as the gate-off voltage. The first
capacitor C1 is charged by the leakage current I_leak. After a
predetermined sampling period, the fourth switching control signal
SWC4 is applied at the gate-off voltage and a charge corresponding
to the leakage current I_leak is maintained in the first capacitor
C1. The third period may be a period for charging the first
capacitor C1 by the leakage current I_leak.
[0130] For a fourth period, the first, third, and fifth switching
control signals SWC1, SWC3, and SWC5 are applied as the gate-on
voltage and the reference voltage Vset is applied as a voltage at
which the OLED emits light at a predetermined reference gray
signal. In this case, the second and fourth switching control
signals SWC2 and SWC4 are applied as the gate-off voltage. The
sensing signal SE[i] of the gate-on voltage is applied to the gate
electrode of the sensing transistor M3. The bias circuit Ibias
generates substantially the same current as a reference current
Iref flowing through the driving transistor M2 turned on by the
data signal of the reference gray signal.
[0131] The reference current Iref flows from the high level voltage
VGH to the second node N12 through the bias circuit Ibias. The
pixel current Iref' at which the OLED emits light at the reference
gray signal flows from the second node N12 toward the pixel PX. A
difference current Idiff=Iref+I_leak-Iref,' which corresponds to
the difference between the pixel current Iref' flowing toward the
pixel PX from the second node N12 and the sum of the reference
current Iref flowing to the second node N12 through the bias
circuit Ibias and the leakage current I_leak of the data line Dj,
flows to the third node N13 through the second transistor M12. As a
result, the difference current Idiff is stored in the second
capacitor C2. After a predetermined sampling period, the fifth
switching control signal SWC5 is applies as the gate-off voltage
and a charge corresponding to the difference current Idif is
maintained in the second capacitor C2. The sampling periods of the
third and fourth periods may be set to the same period. The fourth
period may be a period for charging the second capacitor C2 by the
difference current Idif.
[0132] For a fifth period, the difference value between the
voltages stored in the first and second capacitors C1 and C2 is
output as the degradation information Deg through the comparator
COMP. The difference value is a voltage corresponding to a
difference value (Deg=Iref'-Iref) between the voltages stored in
the first and second capacitors C1 and C2. The degradation degree
of the pixel may be determined by the difference value Deg. For
example, when the Deg value is a positive value, the pixel current
Iref' flowing in the driving transistor M2 is decreased by the data
signal of the reference gray signal, which means that degradation
of the pixel is increased.
[0133] As such, an accurate pixel current may be measured
regardless of the leakage current, and as a result, the degradation
of the pixel may be accurately detected.
[0134] FIG. 6 is a block diagram illustrating a connection
configuration of the deterioration compensating unit and a
plurality of data lines according to an exemplary embodiment.
[0135] Referring to FIG. 6, the compensation unit 600 described in
FIG. 4 or 5, includes a plurality of compensation units 600-1,
600-2, . . . , 600m to be respectively connected to a plurality of
data lines D1 to Dm. The compensation units 600-1, 600-2, . . . ,
600m may detect degradation information Deg1, Deg2, . . . , Degm of
the pixels PX respectively connected to the data lines D1 to
Dm.
[0136] FIG. 7 is a block diagram illustrating a connection
configuration of the deterioration compensating unit and a
plurality of data lines according to another exemplary
embodiment.
[0137] Referring to FIG. 7, one compensation unit 600 illustrated
in FIG. 4 or 5 is provided and connected to a plurality of data
lines D1 to Dm through a multiplexor (MUX) unit 650. The MUX unit
650 may selectively connect the compensation unit 600 to the data
lines D1 to Dm. The compensation unit 600 is selectively connected
to the data lines D1 to Dm through the MUX unit 650 and may detect
the degradation information of the pixels PX respectively connected
to the data lines D1 to Dm.
[0138] FIG. 8 is a flowchart showing an exemplary operation or
procedure 800 for driving a display device according to one
embodiment. Depending on the embodiment, additional states may be
added, others removed, or the order of the states changed in FIG.
8. In state 810, the parasitic capacitor connected to a data line
is charged to a reference voltage. In state 820, a leakage current
flowing from the data line is stored in the first capacitor. In
state 830, a data signal having a predetermined reference gray
signal is applied to a pixel connected to the data line. In state
840, the current flowing from the pixel is measured while the
predetermined reference gray signal is applied to the pixel. In
state 850, a difference current is stored in the second capacitor.
The difference current is defined as the difference between a
reference current and the measured current. In state 860, a
difference value is output. The difference value is defined as the
difference between the voltages stored in the first and second
capacitors.
[0139] In some embodiments, the procedure 800 is implemented in a
conventional programming language, such as C or C++ or another
suitable programming language. In one embodiment, the program is
stored on a computer accessible storage medium of the display
device. In another embodiment, the program is stored in a separate
storage medium. The storage medium may include any of a variety of
technologies for storing information. In one embodiment, the
storage medium includes a random access memory (RAM), hard disks,
floppy disks, digital video devices, compact discs, video discs,
and/or other optical storage mediums, etc. In another embodiment,
the signal controller 100 is configured to or programmed to perform
at least part of the procedure 800. The program may be stored in
the processor. In various embodiments, the processor may have a
configuration based on, for example, i) an advanced RISC machine
(ARM) microcontroller and ii) Intel Corporation's microprocessors
(e.g., the Pentium family microprocessors). In one embodiment, the
processor is implemented with a variety of computer platforms using
a single chip or multichip microprocessors, digital signal
processors, embedded microprocessors, microcontrollers, etc. In
another embodiment, the processor is implemented with a wide range
of operating systems such as Unix, Linux, Microsoft DOS, Microsoft
Windows 7/Vista/2000/9x/ME/XP, Macintosh OS, OS/2, Android, iOS and
the like. In another embodiment, at least part of the procedure 800
can be implemented with embedded software.
[0140] While the described technology has been described in
connection with what is presently considered to be practical
exemplary embodiments, it is to be understood that the invention is
not limited to the disclosed embodiments, but, on the contrary, is
intended to cover various modifications and equivalent arrangements
included within the spirit and scope of the appended claims.
* * * * *