U.S. patent application number 14/481905 was filed with the patent office on 2015-03-12 for single-poly non-volatile memory cell.
The applicant listed for this patent is GEMBEDDED TECH LTD.. Invention is credited to Chi-Tsai Chen.
Application Number | 20150069483 14/481905 |
Document ID | / |
Family ID | 52597802 |
Filed Date | 2015-03-12 |
United States Patent
Application |
20150069483 |
Kind Code |
A1 |
Chen; Chi-Tsai |
March 12, 2015 |
SINGLE-POLY NON-VOLATILE MEMORY CELL
Abstract
A single-poly NVM cell includes a substrate having an isolation
region separating a first OD region from a second OD region, a read
transistor within the first OD region, and a coupling capacitor
within the second OD region. A first ion well completely overlaps
with the first oxide define region. The read transistor includes a
drain region, a source region, a channel region, a single-poly
floating gate overlying the channel region, and a gate dielectric
layer between the floating gate and the channel region. The
coupling capacitor includes a shallow ion well, a heavily-doped,
ultra-shallow dopant region in the shallow ion well, a single-poly
charge-storage floating gate overlying the heavily-doped,
ultra-shallow dopant region, and a gate dielectric layer under the
charge storage floating gate. The shallow ion well has a junction
depth that is substantially equal to or shallower than a trench
depth of the isolation region.
Inventors: |
Chen; Chi-Tsai; (Taichung
City, TW) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
GEMBEDDED TECH LTD. |
TORTOLA |
|
VG |
|
|
Family ID: |
52597802 |
Appl. No.: |
14/481905 |
Filed: |
September 9, 2014 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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61875700 |
Sep 10, 2013 |
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61876775 |
Sep 12, 2013 |
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61882024 |
Sep 25, 2013 |
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61887470 |
Oct 7, 2013 |
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61892425 |
Oct 17, 2013 |
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Current U.S.
Class: |
257/298 |
Current CPC
Class: |
H01L 27/11558
20130101 |
Class at
Publication: |
257/298 |
International
Class: |
H01L 27/115 20060101
H01L027/115; H01L 29/94 20060101 H01L029/94 |
Claims
1. A single-poly non-volatile memory (NVM) cell, comprising: a
semiconductor substrate of a first conductivity type, having
thereon an isolation region separating a first oxide define (OD)
region from a second OD region; a first ion well in the
semiconductor substrate, wherein the first ion well completely
overlaps with the first oxide define region and does not overlap
with the second oxide define region; a read transistor within the
first OD region, the read transistor comprising a drain region, a
source region, a channel region between the drain region and the
source region, a floating gate formed of a single polycrystalline
silicon layer overlying the channel region, and a gate dielectric
layer between the floating gate and the channel region; and a
coupling capacitor within the second OD region, the coupling
capacitor comprising a shallow ion well of a second conductivity
type opposite to the first conductivity type, a heavily-doped,
ultra-shallow dopant region in the shallow ion well, a charge
storage floating gate formed of a single polycrystalline silicon
layer overlying the heavily-doped, ultra-shallow dopant region, and
agate dielectric layer between the charge storage floating gate and
heavily-doped, ultra-shallow dopant region, wherein the charge
storage floating gate of the coupling capacitor is electrically
coupled to the floating gate of the read transistor, and wherein
the shallow ion well has a junction depth that is substantially
equal to or shallower than a trench depth of the isolation
region.
2. The single-poly NVM cell according to claim 1 wherein the first
ion well has the second conductivity type.
3. The single-poly NVM cell according to claim 1 wherein the first
ion well has the first conductivity type.
4. The single-poly NVM cell according to claim 1 wherein the
shallow ion well has the second conductivity type, the
heavily-doped, ultra-shallow dopant region has the first
conductivity type, and the contact region has the first
conductivity type.
5. The single-poly NVM cell according to claim 2 wherein the
shallow ion well, the heavily-doped, ultra-shallow dopant region,
and the contact region have the second conductivity type.
6. The single-poly NVM cell according to claim 1 wherein a contact
region is disposed in the heavily-doped, ultra-shallow dopant
region.
7. The single-poly NVM cell according to claim 1 wherein a junction
between the shallow ion well and the heavily-doped, ultra-shallow
dopant region has a junction depth that is shallower than the
trench depth of the isolation region.
8. The single-poly NVM cell according to claim 1 wherein the trench
depth ranges between 0.1 micrometers and 1.0 micrometers.
9. The single-poly NVM cell according to claim 1 wherein the
shallow ion well is formed directly within the semiconductor
substrate, and is not formed within an ion well.
10. The single-poly NVM cell according to claim 1 wherein the first
ion well is electrically coupled to a well voltage.
11. The single-poly NVM cell according to claim 6 wherein the
contact region, the heavily-doped, ultra-shallow dopant region, and
the shallow ion well are commonly connected to a control gate
voltage.
12. The single-poly NVM cell according to claim 1 wherein the
heavily-doped, ultra-shallow dopant region and the shallow ion well
serve as a charge pumping element.
13. The single-poly NVM cell according to claim 6 further
comprising an extra dopant region encompassing the contact
region.
14. The single-poly NVM cell according to claim 13 wherein the
extra dopant region partially overlaps with the shallow ion well
and the heavily-doped, ultra-shallow dopant region.
15. The single-poly NVM cell according to claim 1 further
comprising a lightly-doped dopant region of the first conductivity
type, wherein the heavily-doped, ultra-shallow dopant region is
formed within the lightly-doped dopant region of the first
conductivity type.
16. The single-poly NVM cell according to claim 15 wherein a
junction between the shallow ion well of the second conductivity
type and the lightly-doped dopant region of the first conductivity
type has a junction depth that is shallower than a trench depth of
the isolation region.
17. The single-poly NVM cell according to claim 1 further
comprising a second ion well of the second conductivity type within
the second OD region.
18. The single-poly NVM cell according to claim 17 wherein the
second ion well of the second conductivity type is spaced apart
from the first ion well and partially overlaps with the second OD
region.
19. The single-poly NVM cell according to claim 18 further
comprising a third ion well of the first conductivity type within
the second OD region between the first ion well and the second ion
well.
20. The single-poly NVM cell according to claim 19 wherein the
second ion well of the second conductivity type partially overlaps
with the second OD region.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application claims priority from U.S. provisional
application Ser. No. 61/875,700 filed Sep. 10, 2013, U.S.
provisional application Ser. No. 61/876,775 filed Sep. 12, 2013,
U.S. provisional application Ser. No. 61/882,024 filed Sep. 25,
2013, U.S. provisional application Ser. No. 61/887,470 filed Oct.
7, 2013, and U.S. provisional application Ser. No. 61/892,425 filed
Oct. 17, 2013, which are incorporated herein by reference in their
entirety.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates generally to non-volatile
memory (NVM) devices. More particularly, the present invention
relates to a single polycrystalline silicon (single-poly) NVM
cell.
[0004] 2. Description of the Prior Art
[0005] Nonvolatile memory (NVM) devices are well known in the art.
A NVM device does not lose its data when the system or device is
turned off. As the demand for small size portable electrical
devices such as cellular phones increases, there is a great need of
the embedded memory for logic circuits and system on a chip.
High-performance embedded memory is a key component in VLSI or ULSI
because of its high-speed and wide bus-width capability, which
eliminates inter-chip communication. A NVM device, which is fully
compatible with CMOS logic processes and has low power consumption,
improved writing efficiency, low cost and high packing density is
highly desirable.
[0006] A NVM device typically comprises a MOS transistor having a
source, a drain, a floating gate, and a control gate. Electrons may
be transferred from the floating gate to the substrate by tunneling
through a thin silicon dioxide layer. Tunneling is the process by
which an NVM can be either erased or programmed. Storage of the
charge on the floating gate allows the threshold voltage to be
electrically altered between a low and a high value to represent
logic 0 and 1, respectively. In floating gate memory devices,
charge or data is stored in the floating gate and is retained when
the power is removed.
[0007] To embed memory cells into a standard logic process without
changing the single-poly process typically used in the fabrication
of the logic circuitry, the single-poly memory scheme has been
developed. The prior art single-poly memory cell typically includes
N.sup.+ source and N.sup.+ drain regions formed in a P-type
substrate and a polycrystalline silicon gate overlying a channel
region extending between the source and drain regions. An N-type
diffusion region formed in the P-type substrate serves as the
control gate and is capacitively coupled to a floating gate via a
thin gate oxide layer. The single-poly memory cell may be
programmed by electron-tunneling from the floating gate to the
substrate.
[0008] Although compatible with standard CMOS fabrication,
conventional single-poly NVM suffers from high-voltage operation,
slow programming, and incapability of electrical erase.
[0009] U.S. Patent Pub. No. 2009/0201742 A1 discloses a single-poly
NVM cell that can be programmed and erased with low operation
voltages. The single-poly NVM cell includes a programming charge
coupling MOS capacitor formed in a first P well and a storage MOS
transistor formed in a second P well. The first and second P wells
are formed in a deep N well in a P-type substrate. The programming
charge coupling MOS capacitor comprises N.sup.+ source and N.sup.+
drain regions, and a program-coupling floating gate that is
electrically connected to a charge-storage floating gate of the
storage MOS transistor to form a floating gate node. The N.sup.+
source and N.sup.+ drain regions and the first P well of the
programming charge coupling MOS capacitor are commonly connected to
a well biasing voltage. However, to establish a large coupling
ratio, the physical size of the MOS capacitor is approximately 10
times greater than that of the storage MOS transistor.
[0010] As the size of memory cells shrinks, the capacitance area
between the floating gate and the control gate shrinks as well. As
a result, the drive current and/or coupling ratio are usually
insufficient to effectively perform operations such as programming,
erasing and reading. Therefore, there is a need in this industry to
provide a single-poly NVM cell with high coupling ratio suited for
deep sub-micron dimensions, preferably 65 nm technology nodes and
beyond, which does not exhibit the above-mentioned problems.
SUMMARY OF THE INVENTION
[0011] It is one object of this invention to provide a single-poly,
one-transistor one-capacitor (1T1C) NVM cell with high coupling
ratio, which is compatible with current CMOS logic processes with
minor change by adding one process layer, and which has a
shrinkable and scalable structure for deep sub-micron dimensions,
preferably 65 nm technology nodes and beyond.
[0012] It is another object of this invention to provide a
single-poly NVM cell with improved coupling ratio when compared to
the NVM cells of the prior art, which is suited for applications
including but not limited to one-time programmable (OTP) memory,
multi-time programmable (MTP), electrically erasable programmable
read only memory (EEPROM), or flash memory.
[0013] According to one embodiment of the invention, a single-poly
non-volatile memory (NVM) cell includes a semiconductor substrate
of a first conductivity type, having thereon an isolation region
separating a first oxide define region from a second oxide define
region, a first ion well in the semiconductor substrate, a read
transistor within the first OD region, and a coupling capacitor
within the second OD region. The first ion well completely overlaps
with the first oxide define region and does not overlap with the
second oxide define region. The read transistor includes a drain
region, a source region, a channel region between the drain region
and the source region, a floating gate formed of a single
polycrystalline silicon layer overlying the channel region, and a
gate dielectric layer between the floating gate and the channel
region.
[0014] The coupling capacitor includes a shallow ion well of a
second conductivity type opposite to the first conductivity type, a
heavily-doped, ultra-shallow dopant region in the shallow ion well,
a contact region in the heavily-doped, ultra-shallow dopant region,
a charge storage floating gate formed of a single polycrystalline
silicon layer overlying the heavily-doped, ultra-shallow dopant
region, and a gate dielectric layer between the charge storage
floating gate and heavily-doped, ultra-shallow dopant region.
[0015] The charge storage floating gate of the coupling capacitor
is electrically coupled to the floating gate of the read
transistor. The heavily-doped, ultra-shallow dopant region and the
shallow ion well serve as a charge pumping element.
[0016] According to one embodiment of the invention, the first ion
well has the second conductivity type.
[0017] According to another embodiment of the invention, the first
ion well has the first conductivity type.
[0018] According to another embodiment of the invention, the
shallow ion well has the second conductivity type, the
heavily-doped, ultra-shallow dopant region has the first
conductivity type, and the contact region has the first
conductivity type.
[0019] According to another embodiment of the invention, the
shallow ion well, the heavily-doped, ultra-shallow dopant region,
and the contact region all have the second conductivity type.
[0020] According to another embodiment of the invention, the
shallow ion well has a junction depth that is substantially equal
to or shallower than a trench depth of the isolation region.
[0021] According to another embodiment of the invention, a junction
between the shallow ion well and the heavily-doped, ultra-shallow
dopant region has a junction depth that is substantially equal to
or shallower than the trench depth of the isolation region.
[0022] According to another embodiment of the invention, the trench
depth ranges between 0.1 micrometers and 1.0 micrometers.
[0023] According to another embodiment of the invention, the
shallow ion well is formed directly within the semiconductor
substrate, and is not formed within an ion well.
[0024] According to another embodiment of the invention, the
single-poly NVM cell further comprises an extra dopant region
encompassing the contact region. The extra dopant region partially
overlaps with the shallow ion well and the heavily-doped,
ultra-shallow dopant region.
[0025] According to another embodiment of the invention, the
single-poly NVM cell further comprises a lightly-doped dopant
region of the first conductivity type, wherein the heavily-doped,
ultra-shallow dopant region is formed within the lightly-doped
dopant region of the first conductivity type.
[0026] According to another embodiment of the invention, a junction
between the shallow ion well of the second conductivity type and
the lightly-doped dopant region of the first conductivity type has
a junction depth that is shallower than a trench depth of the
isolation region.
[0027] According to another embodiment of the invention, the
single-poly NVM cell further comprises a second ion well of the
second conductivity type within the second OD region. The second
ion well of the second conductivity type is spaced apart from the
first ion well and partially overlaps with the second OD
region.
[0028] According to another embodiment of the invention, the
single-poly NVM cell further comprises a third ion well of the
first conductivity type within the second OD region between the
first ion well and the second ion well. The second ion well of the
second conductivity type partially overlaps with the second OD
region.
[0029] These and other objectives of the present invention will no
doubt become obvious to those of ordinary skill in the art after
reading the following detailed description of the preferred
embodiment that is illustrated in the various figures and
drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0030] The accompanying drawings are included to provide a further
understanding of the embodiments, and are incorporated in and
constitute apart of this specification. The drawings illustrate
some of the embodiments and, together with the description, serve
to explain their principles. In the drawings:
[0031] FIG. 1A is a schematic, cross-sectional view of a
single-poly NVM cell in accordance with one embodiment of the
invention, wherein the read transistor is PMOS;
[0032] FIG. 1B is a schematic, cross-sectional view of a
single-poly NVM cell in accordance with one embodiment of the
invention, wherein the read transistor is NMOS;
[0033] FIG. 2A is a partial, schematic, cross-sectional view of a
single-poly NVM cell in accordance with another embodiment of the
invention, wherein the read transistor is PMOS, and the coupling
capacitor comprises an extra N.sup.- region to enclose the P.sup.+
contact region;
[0034] FIG. 2B is a partial, schematic, cross-sectional view of a
single-poly NVM cell in accordance with another embodiment of the
invention, wherein the read transistor is NMOS;
[0035] FIG. 3A is a partial, schematic, cross-sectional view of a
single-poly NVM cell in accordance with another embodiment of the
invention, wherein the read transistor is PMOS, and the coupling
capacitor comprises a multi-well scheme (shallow P.sup.+/shallow
P.sup.-/shallow N.sup.-/P-Sub);
[0036] FIG. 3B is a partial, schematic, cross-sectional view of a
single-poly NVM cell in accordance with another embodiment of the
invention, wherein the read transistor is NMOS;
[0037] FIG. 4A is a partial, schematic, cross-sectional view of a
single-poly NVM cell in accordance with yet another embodiment of
the invention, wherein the read transistor is NMOS, and the
coupling capacitor comprises a multi-well scheme (shallow
P.sup.+/shallow P.sup.-/shallow N.sup.-/P-Sub) with an extra
P.sup.- region encompassing the P.sup.+ contact region;
[0038] FIG. 4B is a partial, schematic, cross-sectional view of a
single-poly NVM cell in accordance with another embodiment of the
invention, wherein the read transistor is NMOS;
[0039] FIG. 5A is a partial, schematic, cross-sectional view of a
single-poly NVM cell in accordance with yet another embodiment of
the invention, wherein the read transistor is NMOS, and the
coupling capacitor comprises a multi-well scheme (shallow
P.sup.+/shallow P.sup.-/shallow N.sup.-/P-Sub) with an extra
P.sup.- region encompassing the P.sup.+ contact region, wherein an
additional N well (NW) is provided within the second OD region;
[0040] FIG. 5B is a partial, schematic, cross-sectional view of a
single-poly NVM cell in accordance with another embodiment of the
invention, wherein the read transistor is NMOS;
[0041] FIG. 6A is a partial, schematic, cross-sectional view of a
single-poly NVM cell in accordance with yet another embodiment of
the invention, wherein the read transistor is NMOS, and the
coupling capacitor comprises a multi-well scheme (shallow
P.sup.+/shallow P.sup.-/shallow N.sup.-/P-Sub) with an extra
P.sup.- region encompassing the P.sup.+ contact region, wherein an
additional N well (NW) and an additional P well (PW) are provided
within the second OD region;
[0042] FIG. 6B is a partial, schematic, cross-sectional view of a
single-poly NVM cell in accordance with another embodiment of the
invention, wherein the read transistor is NMOS;
[0043] FIG. 7 is a schematic, cross-sectional diagram of a
conventional cell structure; and
[0044] FIG. 8 shows an exemplary layout that illustrates the
advantage of reduced spacing S between two adjacent coupling
wells.
[0045] It should be noted that all the figures are diagrammatic.
Relative dimensions and proportions of parts of the drawings have
been shown exaggerated or reduced in size, for the sake of clarity
and convenience in the drawings. The same reference signs are
generally used to refer to corresponding or similar features in
modified and different embodiments.
DETAILED DESCRIPTION
[0046] In the following detailed description of the invention,
reference is made to the accompanying drawings, which form a part
hereof, and in which is shown, by way of illustration, specific
embodiments in which the invention may be practiced. These
embodiments are described in sufficient detail to enable those
skilled in the art to practice the invention. Other embodiments may
be utilized and structural, logical, and electrical changes may be
made without departing from the scope of the present invention.
[0047] The terms "wafer" and "substrate" used herein include any
structure having an exposed surface onto which at least a layer is
deposited according to the present invention, for example, to form
the integrated circuit (IC) structure. The term "substrate" is
understood to include semiconductor wafers. The term "substrate" is
also used to refer to semiconductor structures during processing,
and may include other layers that have been fabricated thereupon.
Both wafer and substrate include doped and undoped semiconductors,
epitaxial semiconductor layers supported by a base semiconductor or
insulator, as well as other semiconductor structures well known to
one skilled in the art.
[0048] The term "horizontal" as used herein is defined as a plane
parallel to the conventional major plane or surface of the
semiconductor substrate, regardless of its orientation. The term
"vertical" refers to a direction perpendicular to the horizontal as
just defined. Terms, such as "on", "above", "below", "bottom",
"top", "side" (as in "sidewall"), "higher", "lower", "over", and
"under", are defined with respect to the horizontal plane.
[0049] The following detailed description is, therefore, not to be
taken in a limiting sense, and the scope of the present invention
is defined only by the appended claims, along with the full scope
of equivalents to which such claims are entitled.
[0050] FIG. 1A is a schematic, cross-sectional view of a
single-poly NVM cell in accordance with one embodiment of the
invention. The single-poly NVM cell is suited for the applications
including but not limited to one-time programmable (OTP) memory,
multi-time programmable (MTP), electrically erasable programmable
read only memory (EEPROM), or flash memory, and may be embedded in
a system-on chip (SoC) for example. Further, the proposed
single-poly NVM may be an integrated on-chip memory that supports
the logic core to accomplish intended functions.
[0051] As shown in FIG. 1A, the single-poly NVM cell 1a comprises a
semiconductor substrate 10 having a first conductivity type. For
example, the semiconductor substrate 10 may be a P-type silicon
substrate (P-Sub) according to the embodiment. An ion well 12 of a
second conductivity type is formed in a major surface 10a of the
semiconductor substrate 10. For example, the ion well 12 of the
second conductivity type may be an N well (NW) according to the
embodiment. The ion well 12 of the second conductivity type may be
electrically coupled to V.sub.NW through an N.sup.+ contact region
120 formed within the ion well 12 of the second conductivity
type.
[0052] Shallow trench isolation (STI) regions 110a and 110b are
formed in the major surface 10a of the semiconductor substrate 10.
The STI region 110b separates two oxide-define (OD) regions or
active areas: the first OD region 102 and the second OD region 104.
The STI regions 110a and 110b extend into the semiconductor
substrate 10 to a trench depth d.sub.1 that is shallower than the
junction depth of the ion well 12. For example, the trench depth d1
may range between 0.1 micrometers and 1.0 micrometers.
[0053] A read transistor 20, as indicated by the dashed circle on
the left-hand side, is formed within the first OD region 102.
According to the embodiment, the read transistor 20 is a PMOS
transistor and may comprise a P.sup.+ drain region 202, a P.sup.+
source region 204, a channel region 210 between the P.sup.+ drain
region 202 and the P.sup.+ source region 204, a floating gate 206
formed of a single polycrystalline silicon layer overlying the
channel region 210, and a gate dielectric layer 208 between the
floating gate 206 and the channel region 210. The P' drain region
202 is separated from the N.sup.+ contact region 120 by the STI
region 110a. According to the embodiment, the gate dielectric layer
208 is made of the same material and has the same thickness as that
used in the logic circuitry on the same integrated circuit chip.
The P.sup.+ drain region 202 may be electrically coupled to a drain
voltage (V.sub.D) and the P.sup.+ source region 204 may be
electrically coupled to a source voltage (V.sub.S).
[0054] A coupling capacitor 30, as indicated by the dashed circle
on the right-hand side, is formed within the second OD region 104.
According to the embodiment, the coupling capacitor 30 may comprise
a shallow ion well 320 of the second conductivity type, a
heavily-doped, ultra-shallow dopant region 310 of the first
conductivity type in the shallow ion well 320 of the second
conductivity type, a contact region 304 of the first conductivity
type in the heavily-doped, ultra-shallow dopant region 310, a
charge storage floating gate 306 formed of a single polycrystalline
silicon layer overlying the heavily-doped, ultra-shallow dopant
region 310 of the first conductivity type, and a gate dielectric
layer 308 between the charge storage floating gate 306 and
heavily-doped, ultra-shallow dopant region 310.
[0055] According to the embodiment, the shallow ion well 320 of the
second conductivity type may be a shallow N well, the
heavily-doped, ultra-shallow dopant region 310 of the first
conductivity type may be a P.sup.+ ultra-shallow dopant region, and
the contact region 304 of the first conductivity type may be a
P.sup.+ contact region. It is noteworthy that the shallow ion well
320 of the second conductivity type is formed directly within the
semiconductor substrate 10, and is not formed within an ion well of
the second conductivity type such as an N well. A PN junction 311
between the shallow ion well 320 of the second conductivity type
and the heavily-doped, ultra-shallow dopant region 310 of the first
conductivity type has a junction depth d.sub.2 that is shallower
than the trench depth d.sub.1 of the STI regions 110a and 110b.
[0056] It is to be understood that according to another embodiment,
the heavily-doped, ultra-shallow dopant region 310 and the contact
region 304 may both have the second conductivity type as that of
the shallow ion well 320. For example, the shallow ion well 320 may
be a shallow N well, the heavily-doped, ultra-shallow dopant region
310 may be an N.sup.+ ultra-shallow dopant region, and the contact
region 304 may be an N.sup.+ contact region.
[0057] According to the embodiment, the charge storage floating
gate 306 of the coupling capacitor 30 is electrically coupled to
the floating gate 206 of the read transistor 20. The P.sup.+
contact region 304, the heavily-doped, ultra-shallow dopant region
310 of the first conductivity type (shallow P.sup.+), and the
shallow ion well 320 of the second conductivity type (shallow N
well or shallow N.sup.-) may be commonly connected to a control
gate voltage (V.sub.CG). The shallow ion well 320 of the second
conductivity type and the heavily-doped, ultra-shallow dopant
region 310 of the first conductivity type (shallow P.sup.+) may be
electrically coupled to V.sub.CG through the P.sup.+ contact region
304 formed within the ultra-shallow dopant region 310 of the first
conductivity type (shallow P.sup.+). The gate dielectric layers 208
and 308 are made of the same material and have the same thickness
as that used in the logic circuitry on the same integrated circuit
chip. An additional layer or photomask may be added to the current
single-poly logic process in order to form the shallow ion well 320
of the second conductivity type and the heavily-doped,
ultra-shallow dopant region 310 of the first conductivity type
(shallow P.sup.+).
[0058] It is to be understood that although not shown in the
figures, a pair of sidewall spacers may be formed on the opposite
sidewalls of each of the floating gates 206 and 306, and a lightly
doped drain (LDD) regions may be formed under the sidewall
spacers.
[0059] The P.sup.+ drain region 202, the P.sup.+ source region 204,
the P.sup.+ contact region 304 have substantially the same NP
junction depth. The shallow ion well 320 has a junction depth
d.sub.3. According to the embodiment, the junction depth d.sub.3 is
deeper than the junction depth d.sub.2 and is substantially equal
to or shallower than the trench depth d.sub.1 of the STI regions
110a and 110b. According to the embodiment, the multi-well scheme
(shallow P.sup.+ 310/shallow N.sup.- 320/P-Sub 10) directly under
the charge storage floating gate 306 may serve as a charge pumping
element. The heavily-doped, ultra-shallow dopant region 310 of the
first conductivity type (shallow P.sup.+) enhances the coupling
ratio of the single-poly NVM cell 1a.
[0060] To form such multi-well scheme (shallow P.sup.+ 310/shallow
N.sup.- 320/P-Sub 10), a patterned implant mask layer (not shown)
may be formed on the semiconductor substrate 10 to reveal the
second OD region 104. A first ion implantation process may be
carried out to implant N type dopants into the second OD region 104
to form the shallow N.sup.- 320. A second ion implantation process
is then carried out to implant P type dopants into the second OD
region 104 to form the shallow P.sup.+ 310. Thereafter, a thermal
oxidation process is performed to form the gate dielectric layer
308. An etch-back process may be performed to remove an upper
portion of the gate dielectric layer 308. By thinning down the
thickness of the gate dielectric layer 308, the coupling ratio of
the memory cell is increased.
[0061] According to another embodiment, to form such multi-well
scheme (shallow P.sup.+ 310/shallow N.sup.- 320/P-Sub 10), a
patterned implant mask layer (not shown) may be formed on the
semiconductor substrate 10 to reveal the second OD region 104. A
first ion implantation process may be carried out to implant N type
dopants into the second OD region 104 to form the shallow N.sup.-
320. A second ion implantation process is then carried out to
implant P type dopants into the second OD region 104 to form a
shallow P.sup.- (not shown). Thereafter, a thermal oxidation
process is performed to form the gate dielectric layer 308. After
the formation of the gate dielectric layer 308, a third ion
implantation process is carried out to implant P type dopants into
the second OD region 104 to form a shallow P.sup.+ 310. The heavily
doped shallow P.sup.+ 310 helps increase the coupling ratio.
[0062] According to still another embodiment, the shallow P.sup.+
310 and shallow N.sup.- 320 may be formed after the formation of
the gate dielectric layer 308. For example, a thermal oxidation
process is first performed to form the gate dielectric layer 308. A
first ion implantation process may be carried out to implant N type
dopants into the second OD region 104 to form the shallow N.sup.-
320. A second ion implantation process is then carried out to
implant P type dopants into the second OD region 104 to form the
shallow P.sup.+ 310. It is to be understood that in some cases, the
shallow P.sup.+ 310 may be formed before the shallow N.sup.-
320.
[0063] It should be recognized that although the present invention
has been illustrated schematically with the use of certain
conductivity types, the opposite conductive types can also be
implemented.
[0064] FIG. 1B is a partial, schematic, cross-sectional view of a
single-poly NVM cell having an NMOS read transistor. As shown in
FIG. 1B, according to another embodiment, the read transistor 20 of
the single-poly NVM cell 1b may be an NMOS transistor formed in the
ion well 12 of P type (PW) that may be electrically connected to a
P well voltage (V.sub.PW) through a P.sup.+ contact region 120.
Likewise, the single-poly NVM cell 1b further includes a coupling
capacitor 30. The coupling capacitor 30 is formed within the second
OD region 104. The coupling capacitor 30 comprises a shallow ion
well 320 of the second conductivity type, a heavily-doped,
ultra-shallow dopant region 310 in the shallow ion well 320 of the
second conductivity type, a contact region 304 in the
heavily-doped, ultra-shallow dopant region 310, a charge storage
floating gate 306 formed of a single polycrystalline silicon layer
overlying the heavily-doped, ultra-shallow dopant region 310, and a
gate dielectric layer 308 between the charge storage floating gate
306 and heavily-doped, ultra-shallow dopant region 310.
[0065] According to the embodiment, the shallow ion well 320 of the
second conductivity type may be a shallow N well, the
heavily-doped, ultra-shallow dopant region 310 may be a P.sup.+ or
N.sup.+ ultra-shallow dopant region, and the contact region 304 may
be a P.sup.+ or N.sup.+ contact region. It is noteworthy that the
shallow ion well 320 of the second conductivity type is formed
directly within the semiconductor substrate 10, and is not formed
within any ion well. A PN junction 311 between the shallow ion well
320 of the second conductivity type and the heavily-doped,
ultra-shallow dopant region 310 has a junction depth d.sub.2 that
is shallower than the trench depth d.sub.1 of the STI regions 110a
and 110b.
[0066] According to the embodiment, the charge storage floating
gate 306 of the coupling capacitor 30 is electrically coupled to
the floating gate 206 of the read transistor 20. The P.sup.+
contact region 304, the heavily-doped, ultra-shallow dopant region
310, and the shallow ion well 320 of the second conductivity type
(shallow N well or shallow Ni may be commonly connected to a
control gate voltage (V.sub.CG). The shallow ion well 320 of the
second conductivity type and the heavily-doped, ultra-shallow
dopant region 310 may be electrically coupled to V.sub.CG through
the contact region 304 formed within the ultra-shallow dopant
region 310. The gate dielectric layers 208 and 308 are made of the
same material and have the same thickness as that used in the logic
circuitry on the same integrated circuit chip.
[0067] Table 1 below shows the exemplary operating conditions for
the single-poly NVM cell 1b in FIG. 1B.
TABLE-US-00001 TABLE 1 V.sub.CG V.sub.D V.sub.S V.sub.PW Program
(Channel Hot Electron 8 V 7 V 0 V 0 V Injection) Erase (FN
tunneling) -5 V 8 V 8 V 0 V Erase (Hot Hole Injection) -3 V 7 V 0 V
0 V Erase (Hot Hole Injection) 0~2 V 7 V 0 V 0 V
[0068] In program (write) operation, for example, the shallow ion
well 320 (shallow N.sup.-) and the heavily-doped, ultra-shallow
dopant region 310 (shallow P.sup.+) are electrically coupled to
V.sub.CG=8V through the contact region 304. The drain region 202 of
the read transistor 20 is electrically coupled to drain voltage
V.sub.D=7V. The source region 204 of the read transistor 20 is
electrically coupled to source voltage V.sub.S=0V. The P well 12 is
electrically coupled to P well voltage V.sub.PW=0V through the
P.sup.+ contact region 120. Under such condition, the memory cell
1b is programmed by Channel Hot Electron Injection.
[0069] In erase operation, for example, the shallow ion well 320
(shallow N.sup.-) and the heavily-doped, ultra-shallow dopant
region 310 (shallow P.sup.+) are electrically coupled to
V.sub.CG=-5V through the contact region 304. The drain region 202
of the read transistor 20 is electrically coupled to drain voltage
V.sub.D=8V. The source region 204 of the read transistor 20 is
electrically coupled to source voltage V.sub.S=8V. The P well 12 is
electrically coupled to P well voltage V.sub.PW=0V through the
P.sup.+ contact region 120. Under such condition, the memory cell
1b is erased by FN tunneling.
[0070] In erase operation, for example, the shallow ion well 320
(shallow N.sup.-) and the heavily-doped, ultra-shallow dopant
region 310 (shallow P.sup.+) are electrically coupled to
V.sub.CG=-3V through the contact region 304. The drain region 202
of the read transistor 20 is electrically coupled to drain voltage
V.sub.D=7V. The source region 204 of the read transistor 20 is
electrically coupled to source voltage V.sub.S=0V. The P well 12 is
electrically coupled to P well voltage V.sub.PW=0V through the
P.sup.+ contact region 120. Under such condition, the memory cell
1b is erased by Hot Hole Injection.
[0071] In erase operation, for example, the shallow ion well 320
(shallow N.sup.-) and the heavily-doped, ultra-shallow dopant
region 310 (shallow P.sup.+) are electrically coupled to
V.sub.CG=0-2V through the contact region 304. The drain region 202
of the read transistor 20 is electrically coupled to drain voltage
V.sub.D=7V. The source region 204 of the read transistor 20 is
electrically coupled to source voltage V.sub.G=0V. The P well 12 is
electrically coupled to P well voltage V.sub.PW=0V through the
P.sup.+ contact region 120. Under such condition, the memory cell
1b is erased by Hot Hole Injection.
[0072] FIG. 2A is a partial, schematic, cross-sectional view of a
single-poly NVM cell in accordance with another embodiment of the
invention. As shown in FIG. 2A, the single-poly NVM cell 2a
comprises a semiconductor substrate 10 having a first conductivity
type. For example, the semiconductor substrate 10 may be a P-type
silicon substrate (P-Sub) according to the embodiment. An ion well
12 of a second conductivity type is formed in a major surface 10a
of the semiconductor substrate 10. For example, the ion well 12 of
the second conductivity type may be an N well (NW) according to the
embodiment. The ion well 12 of the second conductivity type may be
electrically coupled to V.sub.NW through an N.sup.+ contact region
120 formed within the ion well 12 of the second conductivity
type.
[0073] Likewise, STI regions 110a and 110b are formed in the major
surface 10a of the semiconductor substrate 10. The STI region 110b
separates two OD regions: the first OD region 102 and the second OD
region 104. The STI regions 110a and 110b extend into the
semiconductor substrate 10 to a trench depth d.sub.1 that is
shallower than the junction depth of the ion well 12. For example,
the trench depth d1 may range between 0.1 micrometers and 1.0
micrometers.
[0074] A read transistor 20 is formed within the first OD region
102. According to the embodiment, the read transistor 20 is a PMOS
transistor and may comprise a P.sup.+ drain region 202, a P.sup.+
source region 204, a channel region 210 between the P.sup.+ drain
region 202 and the P.sup.+ source region 204, a floating gate 206
formed of a single polycrystalline silicon layer overlying the
channel region 210, and a gate dielectric layer 208 between the
floating gate 206 and the channel region 210. The P.sup.+ drain
region 202 is separated from the N.sup.+ contact region 120 by the
STI region 110a. According to the embodiment, the gate dielectric
layer 208 is made of the same material and has the same thickness
as that used in the logic circuitry on the same integrated circuit
chip. The P.sup.+ drain region 202 may be electrically coupled to a
drain voltage (V.sub.D) and the P.sup.+ source region 204 may be
electrically coupled to a source voltage (V.sub.S).
[0075] A coupling capacitor 30 is formed within the second OD
region 104. According to the embodiment, the coupling capacitor 30
may comprise a shallow ion well 320 of the second conductivity
type, a heavily-doped, ultra-shallow dopant region 310 in the
shallow ion well 320 of the second conductivity type, a contact
region 304 in the heavily-doped, ultra-shallow dopant region 310, a
charge storage floating gate 306 formed of a single polycrystalline
silicon layer overlying the heavily-doped, ultra-shallow dopant
region 310, and a gate dielectric layer 308 between the charge
storage floating gate 306 and heavily-doped, ultra-shallow dopant
region 310.
[0076] According to the embodiment, the shallow ion well 320 of the
second conductivity type may be a shallow N well, the
heavily-doped, ultra-shallow dopant region 310 may be a P.sup.+ or
N.sup.+ ultra-shallow dopant region, and the contact region 304 may
be a P.sup.+ or N.sup.+ contact region. It is noteworthy that the
shallow ion well 320 of the second conductivity type is formed
directly within the semiconductor substrate 10, and is not formed
within an ion well such as an N well or P well. A PN junction 311
between the shallow ion well 320 of the second conductivity type
and the heavily-doped, ultra-shallow dopant region 310 has a
junction depth d.sub.2 that is shallower than the trench depth
d.sub.1 of the STI regions 110a and 110b. The junction depth
d.sub.2 is even shallower than the NP junction depth of the P.sup.+
drain region 202, the P.sup.+ source region 204, and the P.sup.+
contact region 304.
[0077] It is to be understood that according to another embodiment,
the heavily-doped, ultra-shallow dopant region 310 and the contact
region 304 may both have the second conductivity type as that of
the shallow ion well 320. For example, the shallow ion well 320 may
be a shallow N well, the heavily-doped, ultra-shallow dopant region
310 may be an N.sup.+ ultra-shallow dopant region, and the contact
region 304 may be an N.sup.+ contact region.
[0078] The single-poly NVM cell 2a further comprises an extra
N.sup.- region 330 encompassing the P.sup.+ contact region 304. The
extra N.sup.- region 330 has a junction depth d4 that is deeper
than d3. The extra N.sup.- region 330 overlaps with a right portion
of the shallow ion well 320. That is, the extra N.sup.- region 330
partially overlaps with the shallow ion well 320 and the
heavily-doped, ultra-shallow dopant region 310. The extra N.sup.-
region 330 increases breakdown voltage of the memory device.
[0079] According to the embodiment, the charge storage floating
gate 306 of the coupling capacitor 30 is electrically coupled to
the floating gate 206 of the read transistor 20. The P.sup.+
contact region 304, the heavily-doped, ultra-shallow dopant region
310 (shallow P.sup.+), and the shallow ion well 320 of the second
conductivity type (shallow N well or shallow N.sup.-) may be
commonly connected to a control gate voltage (V.sub.CG). The
shallow ion well 320 of the second conductivity type and the
heavily-doped, ultra-shallow dopant region 310 (shallow P.sup.+)
may be electrically coupled to V.sub.CG through the P.sup.+ contact
region 304 formed within the ultra-shallow dopant region 310
(shallow P.sup.+). The gate dielectric layers 208 and 308 are made
of the same material and have the same thickness as that used in
the logic circuitry on the same integrated circuit chip. An
additional layer or photomask may be added to the current
single-poly logic process in order to form the shallow ion well 320
of the second conductivity type and the heavily-doped,
ultra-shallow dopant region 310 (shallow P.sup.+).
[0080] It is to be understood that although not shown in the
figures, a pair of sidewall spacers may be formed on the opposite
sidewalls of each of the floating gates 206 and 306, and a lightly
doped drain (LDD) regions may be formed under the sidewall
spacers.
[0081] The P.sup.+ drain region 202, the P.sup.+ source region 204,
the P.sup.+ contact region 304 have substantially the same NP
junction depth. The shallow ion well 320 has a junction depth
d.sub.3. According to the embodiment, the junction depth d.sub.3 is
deeper than the junction depth d.sub.2 and is substantially equal
to or shallower than the trench depth d.sub.1 of the STI regions
110a and 110b. According to the embodiment, the multi-well scheme
(shallow P.sup.+ 310/shallow N.sup.- 320/P-Sub 10) directly under
the charge storage floating gate 306 may serve as a charge pumping
element. The heavily-doped, ultra-shallow dopant region 310
(shallow P.sup.+) enhances the coupling ratio of the single-poly
NVM cell 2a.
[0082] To form such multi-well scheme (shallow P.sup.+ 310/shallow
N.sup.- 320/extra N.sup.-/P-Sub 10), a patterned implant mask layer
(not shown) may be formed on the semiconductor substrate 10 to
reveal the second OD region 104. A first ion implantation process
may be carried out to implant N type dopants into the second OD
region 104 to form the shallow N.sup.- 320. A second ion
implantation process is then carried out to implant P type dopants
into the second OD region 104 to form the shallow P.sup.+ 310.
Thereafter, a thermal oxidation process is performed to form the
gate dielectric layer 308. An etch-back process may be performed to
remove an upper portion of the gate dielectric layer 308. By
thinning down the thickness of the gate dielectric layer 308, the
coupling ratio of the memory cell is increased. Subsequently, a
third ion implantation process is carried out to implant N type
dopants into the second OD region 104 to form the extra N.sup.-
region 330. The third ion implantation process may be carried out
after the formation of the charge storage floating gate 306 and may
be self-aligned to the edge of the charge storage floating gate
306.
[0083] According to another embodiment, to form such multi-well
scheme (shallow P.sup.+ 310/shallow N.sup.- 320/extra N.sup.-/P-Sub
10), a patterned implant mask layer (not shown) may be formed on
the semiconductor substrate 10 to reveal the second OD region 104.
A first ion implantation process may be carried out to implant N
type dopants into the second OD region 104 to form the shallow
N.sup.- 320. A second ion implantation process is then carried out
to implant P type dopants into the second OD region 104 to form a
shallow P.sup.- (not shown). Thereafter, a thermal oxidation
process is performed to form the gate dielectric layer 308. After
the formation of the gate dielectric layer 308, a third ion
implantation process is carried out to implant P type dopants into
the second OD region 104 to form a shallow P.sup.+ 310. The heavily
doped shallow P.sup.+ 310 helps increase the coupling ratio.
Subsequently, a fourth ion implantation process is carried out to
implant N type dopants into the second OD region 104 to form the
extra N.sup.- region 330. The fourth ion implantation process may
be carried out after the formation of the charge storage floating
gate 306 and may be self-aligned to the edge of the charge storage
floating gate 306.
[0084] According to still another embodiment, the shallow P.sup.+
310 and shallow N.sup.- 320 may be formed after the formation of
the gate dielectric layer 308. For example, a thermal oxidation
process is first performed to form the gate dielectric layer 308. A
first ion implantation process may be carried out to implant N type
dopants into the second OD region 104 to form the shallow N.sup.-
320. A second ion implantation process is then carried out to
implant P type dopants into the second OD region 104 to form the
shallow P.sup.+ 310. Subsequently, a third ion implantation process
is carried out to implant N type dopants into the second OD region
104 to form the extra N.sup.- region 330.
[0085] It should be recognized that although the present invention
has been illustrated schematically with the use of certain
conductivity types, the opposite conductive types can also be
implemented.
[0086] FIG. 2B is a partial, schematic, cross-sectional view of a
single-poly NVM cell having an NMOS read transistor. As shown in
FIG. 2B, according to another embodiment, the read transistor 20 of
the single-poly NVM cell 2b may be an NMOS transistor formed in the
ion well 12 of P type (PW) that may be electrically connected to a
P well voltage (V.sub.PW) through a P.sup.+ contact region 120.
Likewise, the single-poly NVM cell 2b further includes a coupling
capacitor 30. The coupling capacitor 30 is formed within the second
OD region 104. The coupling capacitor 30 comprises a shallow ion
well 320 of the second conductivity type, a heavily-doped,
ultra-shallow dopant region 310 in the shallow ion well 320 of the
second conductivity type, a contact region 304 in the
heavily-doped, ultra-shallow dopant region 310, a charge storage
floating gate 306 formed of a single polycrystalline silicon layer
overlying the heavily-doped, ultra-shallow dopant region 310, and a
gate dielectric layer 308 between the charge storage floating gate
306 and heavily-doped, ultra-shallow dopant region 310.
[0087] According to the embodiment, the shallow ion well 320 of the
second conductivity type may be a shallow N well, the
heavily-doped, ultra-shallow dopant region 310 may be a P.sup.+ or
N.sup.+ ultra-shallow dopant region, and the contact region 304 may
be a P.sup.+ or N.sup.+ contact region. It is noteworthy that the
shallow ion well 320 of the second conductivity type is formed
directly within the semiconductor substrate 10, and is not formed
within any ion well. A PN junction 311 between the shallow ion well
320 of the second conductivity type and the heavily-doped,
ultra-shallow dopant region 310 has a junction depth d.sub.2 that
is shallower than the trench depth d.sub.1 of the STI regions 110a
and 110b.
[0088] According to the embodiment, the charge storage floating
gate 306 of the coupling capacitor 30 is electrically coupled to
the floating gate 206 of the read transistor 20. The P.sup.+
contact region 304, the heavily-doped, ultra-shallow dopant region
310, and the shallow ion well 320 of the second conductivity type
(shallow N well or shallow N.sup.-) may be commonly connected to a
control gate voltage (V.sub.CG). The shallow ion well 320 of the
second conductivity type and the heavily-doped, ultra-shallow
dopant region 310 may be electrically coupled to V.sub.CG through
the contact region 304 formed within the ultra-shallow dopant
region 310. The gate dielectric layers 208 and 308 are made of the
same material and have the same thickness as that used in the logic
circuitry on the same integrated circuit chip.
[0089] FIG. 3A is a partial, schematic, cross-sectional view of a
single-poly NVM cell in accordance with yet another embodiment of
the invention. As shown in FIG. 3A, the single-poly NVM cell 3a
comprises a semiconductor substrate 10 having a first conductivity
type. For example, the semiconductor substrate 10 may be a P-type
silicon substrate (P-Sub) according to the embodiment. An ion well
12 of a second conductivity type is formed in a major surface 10a
of the semiconductor substrate 10. For example, the ion well 12 of
the second conductivity type may be an N well (NW) according to the
embodiment. The ion well 12 of the second conductivity type may be
electrically coupled to V.sub.NW through an N.sup.+ contact region
120 formed within the ion well 12 of the second conductivity
type.
[0090] Likewise, STI regions 110a and 110b are formed in the major
surface 10a of the semiconductor substrate 10. The STI region 110b
separates two oxide-define (OD) regions or active areas: the first
OD region 102 and the second OD region 104. The STI regions 110a
and 110b extend into the semiconductor substrate 10 to a trench
depth d.sub.1 that is shallower than the junction depth of the ion
well 12. For example, the trench depth d.sub.1 may range between
0.1 micrometers and 1.0 micrometers.
[0091] A read transistor 20 is formed within the first OD region
102. According to the embodiment, the read transistor 20 is a PMOS
transistor and may comprise a P.sup.+ drain region 202, a P.sup.+
source region 204, a channel region 210 between the P.sup.+ drain
region 202 and the P.sup.+ source region 204, a floating gate 206
formed of a single polycrystalline silicon layer overlying the
channel region 210, and a gate dielectric layer 208 between the
floating gate 206 and the channel region 210. The P.sup.+ drain
region 202 is separated from the N.sup.+ contact region 120 by the
STI region 110a. According to the embodiment, the gate dielectric
layer 208 is made of the same material and has the same thickness
as that used in the logic circuitry on the same integrated circuit
chip. The P.sup.+ drain region 202 may be electrically coupled to a
drain voltage (V.sub.D) and the P.sup.+ source region 204 may be
electrically coupled to a source voltage (V.sub.S).
[0092] A coupling capacitor 30 is formed within the second OD
region 104. According to the embodiment, the coupling capacitor 30
may comprise a shallow ion well 320' of the second conductivity
type, a heavily-doped, ultra-shallow dopant region 310, a contact
region 304 in the heavily-doped, ultra-shallow dopant region 310,
and a lightly-doped dopant region 312 of the first conductivity
type. The heavily-doped, ultra-shallow dopant region 310 is formed
within the lightly-doped dopant region 312 of the first
conductivity type. A charge storage floating gate 306 formed of a
single polycrystalline silicon layer overlies the heavily-doped,
ultra-shallow dopant region 310. A gate dielectric layer 308 is
provided between the charge storage floating gate 306 and
heavily-doped, ultra-shallow dopant region 310.
[0093] According to the embodiment, the shallow ion well 320' of
the second conductivity type may be a shallow N well, the
heavily-doped, ultra-shallow dopant region 310 may be a P.sup.+ or
N+ ultra-shallow dopant region, and the contact region 304 of the
first conductivity type may be a P.sup.+ or N+ contact region. It
is noteworthy that the shallow ion well 320' of the second
conductivity type is formed directly within the semiconductor
substrate 10, and is not formed within an ion well of the second
conductivity type such as an N well. A PN junction 313 between the
shallow ion well 320' of the second conductivity type and the
lightly-doped dopant region 312 of the first conductivity type has
a junction depth d5 that is shallower than the trench depth d1 of
the STI regions 110a and 110b.
[0094] It is to be understood that according to another embodiment,
the heavily-doped, ultra-shallow dopant region 310 may have the
second conductivity type as that of the shallow ion well 320'. For
example, the shallow ion well 320' may be a shallow N well, the
heavily-doped and the ultra-shallow dopant region 310 may be an N+
ultra-shallow dopant region.
[0095] According to the embodiment, the charge storage floating
gate 306 of the coupling capacitor 30 is electrically coupled to
the floating gate 206 of the read transistor 20. The P.sup.+
contact region 304, the heavily-doped, ultra-shallow dopant region
310 (shallow P.sup.+), the lightly-doped dopant region 312 of the
first conductivity type (shallow P-), and the shallow ion well 320'
of the second conductivity type (shallow N well or shallow N-) may
be commonly connected to a control gate voltage (VCG). The shallow
ion well 320' of the second conductivity type and the
heavily-doped, ultra-shallow dopant region 310 (shallow P.sup.+)
may be electrically coupled to VCG through the P+ contact region
304 formed within the ultra-shallow dopant region 310 of the first
conductivity type (shallow P.sup.+). The gate dielectric layers 208
and 308 are made of the same material and have the same thickness
as that used in the logic circuitry on the same integrated circuit
chip. An additional layer or photomask may be added to the current
single-poly logic process in order to form the shallow ion well
320' of the second conductivity type, the heavily-doped,
ultra-shallow dopant region 310 (shallow P.sup.+), and the
lightly-doped dopant region 312 of the first conductivity type.
[0096] It is to be understood that although not shown in the
figures, a pair of sidewall spacers may be formed on the opposite
sidewalls of each of the floating gates 206 and 306, and a lightly
doped drain (LDD) regions may be formed under the sidewall
spacers.
[0097] The P+ drain region 202, the P+ source region 204, the P+
contact region 304 have substantially the same NP junction depth.
The shallow ion well 320' has a junction depth d6. According to the
embodiment, the junction depth d6 is deeper than the junction depth
d5 and is deeper than the trench depth d1 of the STI regions 110a
and 110b, while shallower than the junction depth of the ion well
12. According to the embodiment, the multi-well scheme (shallow P+
310/shallow N- 320/shallow P- 312/P-Sub 10) directly under the
charge storage floating gate 306 may serve as a charge pumping
element. The heavily-doped, ultra-shallow dopant region 310
(shallow P+) enhances the coupling ratio of the single-poly NVM
cell 3a.
[0098] To form such multi-well scheme (shallow P+ 310/shallow P-
312/shallow N- 320/P-Sub 10), a patterned implant mask layer (not
shown) may be formed on the semiconductor substrate 10 to reveal
the second OD region 104. A first ion implantation process may be
carried out to implant N type dopants into the second OD region 104
to form the shallow N- 320. A second ion implantation process is
then carried out to implant P type dopants into the second OD
region 104 to form the shallow P- 312. A third ion implantation
process is then carried out to implant P type dopants into the
second OD region 104 to form the shallow P+ 310. Thereafter, a
thermal oxidation process is performed to form the gate dielectric
layer 308. An etch-back process may be performed to remove an upper
portion of the gate dielectric layer 308. By thinning down the
thickness of the gate dielectric layer 308, the coupling ratio of
the memory cell is increased.
[0099] According to another embodiment, to form such multi-well
scheme (shallow P+ 310/shallow P- 312/shallow N- 320/P-Sub 10), a
patterned implant mask layer (not shown) may be formed on the
semiconductor substrate 10 to reveal the second OD region 104. A
first ion implantation process may be carried out to implant N type
dopants into the second OD region 104 to form the shallow N- 320. A
second ion implantation process is then carried out to implant P
type dopants into the second OD region 104 to form the shallow P-
312. Thereafter, a thermal oxidation process is performed to form
the gate dielectric layer 308. After the formation of the gate
dielectric layer 308, a third ion implantation process is carried
out to implant P type dopants into the second OD region 104 to form
a shallow P+ 310. The heavily doped shallow P+ 310 helps increase
the coupling ratio.
[0100] According to still another embodiment, the shallow P+ 310,
the shallow P- 312 and shallow N- 320 may be formed after the
formation of the gate dielectric layer 308. For example, a thermal
oxidation process is first performed to form the gate dielectric
layer 308. A first ion implantation process may be carried out to
implant N type dopants into the second OD region 104 to form the
shallow N- 320. A second and third ion implantation processes are
then carried out to implant P type dopants into the second OD
region 104 to form the shallow P+ 310 and the shallow P- 312.
[0101] It should be recognized that although the present invention
has been illustrated schematically with the use of certain
conductivity types, the opposite conductive types can also be
implemented.
[0102] FIG. 3B is a partial, schematic, cross-sectional view of a
single-poly NVM cell having an NMOS read transistor. As shown in
FIG. 3B, according to another embodiment, the read transistor 20 of
the single-poly NVM cell 3b may be an NMOS transistor formed in the
ion well 12 of P type (PW) that may be electrically connected to a
P well voltage (V.sub.PW) through a P.sup.+ contact region 120.
Likewise, the single-poly NVM cell 3b further includes a coupling
capacitor 30. The coupling capacitor 30 is formed within the second
OD region 104. The coupling capacitor 30 comprises a shallow ion
well 320' of the second conductivity type, a heavily-doped,
ultra-shallow dopant region 310 in the shallow ion well 320' of the
second conductivity type, a lightly-doped dopant region 312 of the
first conductivity type, a contact region 304 in the heavily-doped,
ultra-shallow dopant region 310, a charge storage floating gate 306
formed of a single polycrystalline silicon layer overlying the
heavily-doped, ultra-shallow dopant region 310, and a gate
dielectric layer 308 between the charge storage floating gate 306
and heavily-doped, ultra-shallow dopant region 310.
[0103] According to the embodiment, the shallow ion well 320' of
the second conductivity type may be a shallow N well, the
heavily-doped, ultra-shallow dopant region 310 may be a P.sup.+ or
N.sup.+ ultra-shallow dopant region, the lightly-doped dopant
region 312 of the first conductivity type is a P.sup.- dopant
region, and the contact region 304 may be a P.sup.+ or N.sup.+
contact region. It is noteworthy that the shallow ion well 320' of
the second conductivity type is formed directly within the
semiconductor substrate 10, and is not formed within any ion well.
A PN junction 313 between the shallow ion well 320' of the second
conductivity type and the lightly-doped dopant region 312 of the
first conductivity type has a junction depth d.sub.5 that is
shallower than the trench depth d.sub.1 of the STI regions 110a and
110b.
[0104] According to the embodiment, the charge storage floating
gate 306 of the coupling capacitor 30 is electrically coupled to
the floating gate 206 of the read transistor 20. The P.sup.+
contact region 304, the heavily-doped, ultra-shallow dopant region
310, the lightly-doped dopant region 312 of the first conductivity
type, and the shallow ion well 320' of the second conductivity type
(shallow N well or shallow N.sup.-) may be commonly connected to a
control gate voltage (V.sub.CG). The shallow ion well 320' of the
second conductivity type and the heavily-doped, ultra-shallow
dopant region 310 may be electrically coupled to V.sub.CG through
the contact region 304 formed within the ultra-shallow dopant
region 310. The gate dielectric layers 208 and 308 are made of the
same material and have the same thickness as that used in the logic
circuitry on the same integrated circuit chip.
[0105] FIG. 4A is a partial, schematic, cross-sectional view of a
single-poly NVM cell in accordance with yet another embodiment of
the invention. As shown in FIG. 4A, the single-poly NVM cell 4a
comprises a semiconductor substrate 10 having a first conductivity
type. For example, the semiconductor substrate 10 may be a P-type
silicon substrate (P-Sub) according to the embodiment. An ion well
12 of a second conductivity type is formed in a major surface 10a
of the semiconductor substrate 10. For example, the ion well 12 of
the second conductivity type may be an N well (NW) according to the
embodiment. The ion well 12 of the second conductivity type may be
electrically coupled to V.sub.NW through an N.sup.+ contact region
120 formed within the ion well 12 of the second conductivity
type.
[0106] Likewise, STI regions 110a and 110b are formed in the major
surface 10a of the semiconductor substrate 10. The STI region 110b
separates two oxide-define (OD) regions or active areas: the first
OD region 102 and the second OD region 104. The STI regions 110a
and 110b extend into the semiconductor substrate 10 to a trench
depth d.sub.1 that is shallower than the junction depth of the ion
well 12. For example, the trench depth d.sub.1 may range between
0.1 micrometers and 1.0 micrometers.
[0107] A read transistor 20 is formed within the first OD region
102. According to the embodiment, the read transistor 20 is a PMOS
transistor and may comprise a P.sup.+ drain region 202, a P.sup.+
source region 204, a channel region 210 between the P.sup.+ drain
region 202 and the P.sup.+ source region 204, a floating gate 206
formed of a single polycrystalline silicon layer overlying the
channel region 210, and a gate dielectric layer 208 between the
floating gate 206 and the channel region 210. The P.sup.+ drain
region 202 is separated from the N.sup.+ contact region 120 by the
STI region 110a. According to the embodiment, the gate dielectric
layer 208 is made of the same material and has the same thickness
as that used in the logic circuitry on the same integrated circuit
chip. The P.sup.+ drain region 202 may be electrically coupled to a
drain voltage (V.sub.D) and the P.sup.+ source region 204 may be
electrically coupled to a source voltage (V.sub.S).
[0108] A coupling capacitor 30 is formed within the second OD
region 104. According to the embodiment, the coupling capacitor 30
may comprise a shallow ion well 320' of the second conductivity
type, a heavily-doped, ultra-shallow dopant region 310, a contact
region 304 in the heavily-doped, ultra-shallow dopant region 310,
and a lightly-doped dopant region 312 of the first conductivity
type. The heavily-doped, ultra-shallow dopant region 310 is formed
within the lightly-doped dopant region 312 of the first
conductivity type. A charge storage floating gate 306 formed of a
single polycrystalline silicon layer overlies the heavily-doped,
ultra-shallow dopant region 310. A gate dielectric layer 308 is
provided between the charge storage floating gate 306 and
heavily-doped, ultra-shallow dopant region 310.
[0109] According to the embodiment, the shallow ion well 320' of
the second conductivity type may be a shallow N well, the
heavily-doped, ultra-shallow dopant region 310 may be a P.sup.+ or
N.sup.+ ultra-shallow dopant region, and the contact region 304 of
the first conductivity type may be a P.sup.+ or N.sup.+ contact
region. It is noteworthy that the shallow ion well 320' of the
second conductivity type is formed directly within the
semiconductor substrate 10, and is not formed within an ion well of
the second conductivity type such as an N well. A PN junction 313
between the shallow ion well 320' of the second conductivity type
and the lightly-doped dopant region 312 of the first conductivity
type has a junction depth d.sub.5 that is shallower than the trench
depth d.sub.1 of the STI regions 110a and 110b.
[0110] The single-poly NVM cell 4a further comprises an extra
P.sup.- region 360 encompassing the P.sup.+ contact region 304. The
extra P.sup.- region 360 has a junction depth d.sub.7 that is
deeper than d.sub.5. The extra P.sup.- region 360 overlaps with a
right portion of the lightly-doped dopant region 312 of the first
conductivity type. The extra P.sup.- region 360 increases breakdown
voltage of the memory device.
[0111] It is to be understood that according to another embodiment,
the heavily-doped, ultra-shallow dopant region 310 may have the
second conductivity type as that of the shallow ion well 320'. For
example, the shallow ion well 320' may be a shallow N well, the
heavily-doped and the ultra-shallow dopant region 310 may be an
N.sup.+ ultra-shallow dopant region.
[0112] According to the embodiment, the charge storage floating
gate 306 of the coupling capacitor 30 is electrically coupled to
the floating gate 206 of the read transistor 20. The P.sup.+
contact region 304, the heavily-doped, ultra-shallow dopant region
310 (shallow P.sup.+), the lightly-doped dopant region 312 of the
first conductivity type (shallow P.sup.-), the extra P.sup.- region
360, and the shallow ion well 320' of the second conductivity type
(shallow N well or shallow N.sup.-) may be commonly connected to a
control gate voltage (V.sub.CG). The shallow ion well 320' of the
second conductivity type and the heavily-doped, ultra-shallow
dopant region 310 (shallow P.sup.+) may be electrically coupled to
V.sub.CG through the P.sup.+ contact region 304 formed within the
ultra-shallow dopant region 310 of the first conductivity type
(shallow P.sup.+). The gate dielectric layers 208 and 308 are made
of the same material and have the same thickness as that used in
the logic circuitry on the same integrated circuit chip. An
additional layer or photomask may be added to the current
single-poly logic process in order to form the shallow ion well
320' of the second conductivity type, the heavily-doped,
ultra-shallow dopant region 310 (shallow P.sup.+), and the
lightly-doped dopant region 312 of the first conductivity type.
[0113] It is to be understood that although not shown in the
figures, a pair of sidewall spacers may be formed on the opposite
sidewalls of each of the floating gates 206 and 306, and a lightly
doped drain (LDD) regions may be formed under the sidewall
spacers.
[0114] The P.sup.+ drain region 202, the P.sup.+ source region 204,
the P.sup.+ contact region 304 have substantially the same NP
junction depth. The shallow ion well 320' has a junction depth
d.sub.6. According to the embodiment, the junction depth d.sub.6 is
deeper than the junction depth d.sub.5 and is deeper than the
trench depth d.sub.1 of the STI regions 110a and 110b, while
shallower than the junction depth of the ion well 12. According to
the embodiment, the multi-well scheme (shallow P.sup.+ 310/shallow
N.sup.- 320/shallow P.sup.- 312/P-Sub 10) directly under the charge
storage floating gate 306 may serve as a charge pumping element.
The heavily-doped, ultra-shallow dopant region 310 (shallow
P.sup.+) enhances the coupling ratio of the single-poly NVM cell
4a.
[0115] To form such multi-well scheme (shallow P.sup.+ 310/shallow
P.sup.- 312/shallow N.sup.- 320/P-Sub 10), a patterned implant mask
layer (not shown) may be formed on the semiconductor substrate 10
to reveal the second OD region 104. A first ion implantation
process may be carried out to implant N type dopants into the
second OD region 104 to form the shallow N.sup.- 320. A second ion
implantation process is then carried out to implant P type dopants
into the second OD region 104 to form the shallow P.sup.- 312. A
third ion implantation process is then carried out to implant P
type dopants into the second OD region 104 to form the shallow
P.sup.+ 310. Thereafter, a thermal oxidation process is performed
to form the gate dielectric layer 308. An etch-back process may be
performed to remove an upper portion of the gate dielectric layer
308. By thinning down the thickness of the gate dielectric layer
308, the coupling ratio of the memory cell is increased.
[0116] According to another embodiment, to form such multi-well
scheme (shallow P.sup.+ 310/shallow P.sup.- 312/shallow N.sup.-
320/P-Sub 10), a patterned implant mask layer (not shown) may be
formed on the semiconductor substrate 10 to reveal the second OD
region 104. A first ion implantation process may be carried out to
implant N type dopants into the second OD region 104 to form the
shallow N.sup.- 320. A second ion implantation process is then
carried out to implant P type dopants into the second OD region 104
to form the shallow P.sup.- 312. Thereafter, a thermal oxidation
process is performed to form the gate dielectric layer 308. After
the formation of the gate dielectric layer 308, a third ion
implantation process is carried out to implant P type dopants into
the second OD region 104 to form a shallow P.sup.+ 310. The heavily
doped shallow P.sup.+ 310 helps increase the coupling ratio.
[0117] According to still another embodiment, the shallow P.sup.+
310, the shallow P.sup.- 312 and shallow N.sup.- 320 may be formed
after the formation of the gate dielectric layer 308. For example,
a thermal oxidation process is first performed to form the gate
dielectric layer 308. A first ion implantation process may be
carried out to implant N type dopants into the second OD region 104
to form the shallow N.sup.- 320. A second and third ion
implantation processes are then carried out to implant P type
dopants into the second OD region 104 to form the shallow P.sup.+
310 and the shallow P.sup.- 312.
[0118] It should be recognized that although the present invention
has been illustrated schematically with the use of certain
conductivity types, the opposite conductive types can also be
implemented.
[0119] FIG. 4B is a partial, schematic, cross-sectional view of a
single-poly NVM cell having an NMOS read transistor. As shown in
FIG. 4B, according to another embodiment, the read transistor 20 of
the single-poly NVM cell 4b may be an NMOS transistor formed in the
ion well 12 of P type (PW) that may be electrically connected to a
P well voltage (V.sub.PW) through a P.sup.+ contact region 120.
Likewise, the single-poly NVM cell 4b further includes a coupling
capacitor 30. The coupling capacitor 30 is formed within the second
OD region 104. The coupling capacitor 30 comprises a shallow ion
well 320' of the second conductivity type, a heavily-doped,
ultra-shallow dopant region 310 in the shallow ion well 320' of the
second conductivity type, a lightly-doped dopant region 312 of the
first conductivity type, a contact region 304 in the heavily-doped,
ultra-shallow dopant region 310, an extra P.sup.- region 360
encompassing the contact region 304, a charge storage floating gate
306 formed of a single polycrystalline silicon layer overlying the
heavily-doped, ultra-shallow dopant region 310, and a gate
dielectric layer 308 between the charge storage floating gate 306
and heavily-doped, ultra-shallow dopant region 310.
[0120] According to the embodiment, the shallow ion well 320' of
the second conductivity type may be a shallow N well, the
heavily-doped, ultra-shallow dopant region 310 may be a P.sup.+ or
N.sup.+ ultra-shallow dopant region, the lightly-doped dopant
region 312 of the first conductivity type is a P.sup.- dopant
region, and the contact region 304 may be a P.sup.+ or N.sup.+
contact region. It is noteworthy that the shallow ion well 320' of
the second conductivity type is formed directly within the
semiconductor substrate 10, and is not formed within any ion well.
A PN junction 313 between the shallow ion well 320' of the second
conductivity type and the lightly-doped dopant region 312 of the
first conductivity type has a junction depth d.sub.5 that is
shallower than the trench depth d.sub.1 of the STI regions 110a and
110b.
[0121] According to the embodiment, the charge storage floating
gate 306 of the coupling capacitor 30 is electrically coupled to
the floating gate 206 of the read transistor 20. The P.sup.+
contact region 304, the heavily-doped, ultra-shallow dopant region
310, the lightly-doped dopant region 312 of the first conductivity
type, and the shallow ion well 320' of the second conductivity type
(shallow N well or shallow N.sup.-) may be commonly connected to a
control gate voltage (V.sub.CG). The shallow ion well 320' of the
second conductivity type and the heavily-doped, ultra-shallow
dopant region 310 may be electrically coupled to V.sub.CG through
the contact region 304 formed within the ultra-shallow dopant
region 310. The gate dielectric layers 208 and 308 are made of the
same material and have the same thickness as that used in the logic
circuitry on the same integrated circuit chip.
[0122] FIG. 5A is a partial, schematic, cross-sectional view of a
single-poly NVM cell in accordance with yet another embodiment of
the invention. As shown in FIG. 5A, the single-poly NVM cell 5a
comprises a semiconductor substrate 10 having a first conductivity
type. For example, the semiconductor substrate 10 may be a P-type
silicon substrate (P-Sub) according to the embodiment. An ion well
12 of a second conductivity type is formed in a major surface 10a
of the semiconductor substrate 10. For example, the ion well 12 of
the second conductivity type may be an N well (NW) according to the
embodiment. The ion well 12 of the second conductivity type may be
electrically coupled to V.sub.NW through an N.sup.+ contact region
120 formed within the ion well 12 of the second conductivity
type.
[0123] Likewise, STI regions 110a and 110b are formed in the major
surface 10a of the semiconductor substrate 10. The STI region 110b
separates two oxide-define (OD) regions or active areas: the first
OD region 102 and the second OD region 104. The STI regions 110a
and 110b extend into the semiconductor substrate 10 to a trench
depth d.sub.1 that is shallower than the junction depth of the ion
well 12. For example, the trench depth d.sub.1 may range between
0.1 micrometers and 1.0 micrometers.
[0124] A read transistor 20 is formed within the first OD region
102. According to the embodiment, the read transistor 20 is a PMOS
transistor and may comprise a P.sup.+ drain region 202, a P.sup.+
source region 204, a channel region 210 between the P.sup.+ drain
region 202 and the P.sup.+ source region 204, a floating gate 206
formed of a single polycrystalline silicon layer overlying the
channel region 210, and a gate dielectric layer 208 between the
floating gate 206 and the channel region 210. The P.sup.+ drain
region 202 is separated from the N.sup.+ contact region 120 by the
STI region 110a. According to the embodiment, the gate dielectric
layer 208 is made of the same material and has the same thickness
as that used in the logic circuitry on the same integrated circuit
chip. The P.sup.+ drain region 202 may be electrically coupled to a
drain voltage (V.sub.D) and the P.sup.+ source region 204 may be
electrically coupled to a source voltage (V.sub.S).
[0125] A coupling capacitor 30 is formed within the second OD
region 104. According to the embodiment, the coupling capacitor 30
may comprise a shallow ion well 320' of the second conductivity
type, a heavily-doped, ultra-shallow dopant region 310, a contact
region 304 in the heavily-doped, ultra-shallow dopant region 310,
and a lightly-doped dopant region 312 of the first conductivity
type. The heavily-doped, ultra-shallow dopant region 310 is formed
within the lightly-doped dopant region 312 of the first
conductivity type. A charge storage floating gate 306 formed of a
single polycrystalline silicon layer overlies the heavily-doped,
ultra-shallow dopant region 310. A gate dielectric layer 308 is
provided between the charge storage floating gate 306 and
heavily-doped, ultra-shallow dopant region 310.
[0126] According to the embodiment, the shallow ion well 320' of
the second conductivity type may be a shallow N well, the
heavily-doped, ultra-shallow dopant region 310 may be an N.sup.+
ultra-shallow dopant region, and the contact region 304 of the
first conductivity type may be an N.sup.+ contact region. A PN
junction 313 between the shallow ion well 320' of the second
conductivity type and the lightly-doped dopant region 312 of the
first conductivity type has a junction depth d.sub.5 that is
shallower than the trench depth d.sub.1 of the STI regions 110a and
110b.
[0127] The single-poly NVM cell 4a further comprises an extra
P.sup.- region 360 encompassing the P.sup.+ contact region 304. The
extra P.sup.- region 360 has a junction depth d.sub.7 that is
deeper than d.sub.5. The extra P.sup.- region 360 overlaps with a
right portion of the lightly-doped dopant region 312 of the first
conductivity type. The extra P.sup.- region 360 increases breakdown
voltage of the memory device.
[0128] An additional ion well 14 of the second conductivity type
such as an N well (NW) according to the embodiment is provided
within the second OD region 104. The ion well 14 of the second
conductivity type, which is spaced apart from the ion well 12,
partially overlaps with the second OD region 104. The ion well 14
of the second conductivity type partially overlaps with the well
structure consisting of the heavily-doped, ultra-shallow dopant
region 310 (shallow N.sup.+), the lightly-doped dopant region 312
of the first conductivity type (shallow P.sup.-), and the shallow
ion well 320' of the second conductivity type (shallow N.sup.-).
According to the embodiment, the ion wells 12 and 14 may be formed
by using the same photo mask and the same ion implantation process,
and therefore may have substantially the same doping concentration
and junction depth. The P.sup.+ contact region 304 and the extra
P.sup.- region 360 are formed within the ion well 14 of the second
conductivity type. The charge storage floating gate 306 partially
overlaps with the ion well 14 of the second conductivity type.
[0129] It is to be understood that according to another embodiment,
the heavily-doped, ultra-shallow dopant region 310 may have the
first conductivity type. For example, the shallow ion well 320' may
be a shallow N well, the heavily-doped and the ultra-shallow dopant
region 310 may be an P.sup.+ ultra-shallow dopant region.
[0130] According to the embodiment, the charge storage floating
gate 306 of the coupling capacitor 30 is electrically coupled to
the floating gate 206 of the read transistor 20. The P.sup.+
contact region 304, the heavily-doped, ultra-shallow dopant region
310 (shallow N.sup.+), the lightly-doped dopant region 312 of the
first conductivity type (shallow P.sup.-), the extra P.sup.- region
360, and the shallow ion well 320' of the second conductivity type
(shallow N.sup.-) may be commonly connected to a control gate
voltage (V.sub.CG). The shallow ion well 320' of the second
conductivity type and the heavily-doped, ultra-shallow dopant
region 310 (shallow N.sup.+) may be electrically coupled to
V.sub.CG through the N.sup.+ contact region 304 formed within the
ultra-shallow dopant region 310 of the first conductivity type
(shallow N.sup.+). The gate dielectric layers 208 and 308 are made
of the same material and have the same thickness as that used in
the logic circuitry on the same integrated circuit chip. An
additional layer or photomask may be added to the current
single-poly logic process in order to form the shallow ion well
320' of the second conductivity type, the heavily-doped,
ultra-shallow dopant region 310 (shallow N.sup.+), and the
lightly-doped dopant region 312 of the first conductivity type.
[0131] It is to be understood that although not shown in the
figures, a pair of sidewall spacers may be formed on the opposite
sidewalls of each of the floating gates 206 and 306, and a lightly
doped drain (LDD) regions may be formed under the sidewall
spacers.
[0132] The P.sup.+ drain region 202, the P.sup.+ source region 204,
the P.sup.+ contact region 304 have substantially the same NP
junction depth. The shallow ion well 320' has a junction depth
d.sub.6. According to the embodiment, the junction depth d.sub.6 is
deeper than the junction depth d.sub.5 and is deeper than the
trench depth d.sub.1 of the STI regions 110a and 110b, while
shallower than the junction depth of the ion well 12. According to
the embodiment, the multi-well scheme (shallow N.sup.+ 310/shallow
P.sup.- 312/shallow N.sup.- 320/P-Sub 10) directly under the charge
storage floating gate 306 may serve as a charge pumping element.
The heavily-doped, ultra-shallow dopant region 310 (shallow
N.sup.+) enhances the coupling ratio of the single-poly NVM cell
5a.
[0133] To form such multi-well scheme (shallow N.sup.+ 310/shallow
P.sup.- 312/shallow N.sup.- 320/P-Sub 10), a patterned implant mask
layer (not shown) may be formed on the semiconductor substrate 10
to reveal the second OD region 104. A first ion implantation
process may be carried out to implant N type dopants into the
second OD region 104 to form the shallow N.sup.- 320. A second ion
implantation process is then carried out to implant P type dopants
into the second OD region 104 to form the shallow P.sup.- 312. A
third ion implantation process is then carried out to implant N
type dopants into the second OD region 104 to form the shallow
N.sup.+ 310. Thereafter, a thermal oxidation process is performed
to form the gate dielectric layer 308. An etch-back process may be
performed to remove an upper portion of the gate dielectric layer
308. By thinning down the thickness of the gate dielectric layer
308, the coupling ratio of the memory cell is increased.
[0134] According to another embodiment, to form such multi-well
scheme (shallow N.sup.+ 310/shallow P.sup.- 312/shallow N.sup.-
320/P-Sub 10), a patterned implant mask layer (not shown) may be
formed on the semiconductor substrate 10 to reveal the second OD
region 104. A first ion implantation process may be carried out to
implant N type dopants into the second OD region 104 to form the
shallow N.sup.- 320. A second ion implantation process is then
carried out to implant P type dopants into the second OD region 104
to form the shallow P.sup.- 312. Thereafter, a thermal oxidation
process is performed to form the gate dielectric layer 308. After
the formation of the gate dielectric layer 308, a third ion
implantation process is carried out to implant N type dopants into
the second OD region 104 to form a shallow N.sup.+ 310. The heavily
doped shallow N.sup.+ 310 helps increase the coupling ratio.
[0135] According to still another embodiment, the shallow N.sup.+
310, the shallow P.sup.- 312 and shallow N.sup.- 320 may be formed
after the formation of the gate dielectric layer 308. For example,
a thermal oxidation process is first performed to form the gate
dielectric layer 308. A first ion implantation process may be
carried out to implant N type dopants into the second OD region 104
to form the shallow N.sup.- 320. A second and third ion
implantation processes are then carried out to implant dopants into
the second OD region 104 to form the shallow N.sup.+ 310 and the
shallow P.sup.- 312 respectively.
[0136] It should be recognized that although the present invention
has been illustrated schematically with the use of certain
conductivity types, the opposite conductive types can also be
implemented.
[0137] FIG. 5B is a partial, schematic, cross-sectional view of a
single-poly NVM cell having an NMOS read transistor. As shown in
FIG. 5B, according to another embodiment, the read transistor 20 of
the single-poly NVM cell 5b may be an NMOS transistor formed in the
ion well 12 of P type (PW) that may be electrically connected to a
P well voltage (V.sub.PW) through a P.sup.+ contact region 120.
Likewise, the single-poly NVM cell 5b further includes a coupling
capacitor 30. The coupling capacitor 30 is formed within the second
OD region 104. The coupling capacitor 30 comprises a shallow ion
well 320' of the second conductivity type, a heavily-doped,
ultra-shallow dopant region 310 in the shallow ion well 320' of the
second conductivity type, a lightly-doped dopant region 312 of the
first conductivity type, a contact region 304 in the heavily-doped,
ultra-shallow dopant region 310, an extra P.sup.- region 360
encompassing the contact region 304, a charge storage floating gate
306 formed of a single polycrystalline silicon layer overlying the
heavily-doped, ultra-shallow dopant region 310, and a gate
dielectric layer 308 between the charge storage floating gate 306
and heavily-doped, ultra-shallow dopant region 310.
[0138] An additional ion well 14 of the second conductivity type
such as an N well (NW) according to the embodiment is provided
within the second OD region 104. The ion well 14 of the second
conductivity type, which is spaced apart from the ion well 12 of P
type, partially overlaps with the second OD region 104. The ion
well 14 of the second conductivity type partially overlaps with the
well structure consisting of the heavily-doped, ultra-shallow
dopant region 310 (shallow N.sup.+), the lightly-doped dopant
region 312 of the first conductivity type (shallow P.sup.-), and
the shallow ion well 320' of the second conductivity type (shallow
N.sup.-).
[0139] According to the embodiment, the shallow ion well 320' of
the second conductivity type may be a shallow N well, the
heavily-doped, ultra-shallow dopant region 310 may be an N.sup.+
ultra-shallow dopant region, the lightly-doped dopant region 312 of
the first conductivity type is a P.sup.- dopant region, and the
contact region 304 may be an N.sup.+ contact region. A PN junction
313 between the shallow ion well 320' of the second conductivity
type and the lightly-doped dopant region 312 of the first
conductivity type has a junction depth d5 that is shallower than
the trench depth d1 of the STI regions 110a and 110b.
[0140] According to the embodiment, the charge storage floating
gate 306 of the coupling capacitor 30 is electrically coupled to
the floating gate 206 of the read transistor 20. The P.sup.+
contact region 304, the heavily-doped, ultra-shallow dopant region
310, the lightly-doped dopant region 312 of the first conductivity
type, and the shallow ion well 320' of the second conductivity type
(shallow N.sup.-) may be commonly connected to a control gate
voltage (V.sub.CG). The shallow ion well 320' of the second
conductivity type and the heavily-doped, ultra-shallow dopant
region 310 may be electrically coupled to V.sub.CG through the
contact region 304 formed within the ultra-shallow dopant region
310. The gate dielectric layers 208 and 308 are made of the same
material and have the same thickness as that used in the logic
circuitry on the same integrated circuit chip.
[0141] FIG. 6A is a partial, schematic, cross-sectional view of a
single-poly NVM cell in accordance with yet another embodiment of
the invention. As shown in FIG. 6A, the single-poly NVM cell 6a
comprises a semiconductor substrate 10 having a first conductivity
type. For example, the semiconductor substrate 10 may be a P-type
silicon substrate (P-Sub) according to the embodiment. An ion well
12 of a second conductivity type is formed in a major surface 10a
of the semiconductor substrate 10. For example, the ion well 12 of
the second conductivity type may be an N well (NW) according to the
embodiment. The ion well 12 of the second conductivity type may be
electrically coupled to V.sub.NW through an N.sup.+ contact region
120 formed within the ion well 12 of the second conductivity
type.
[0142] Likewise, STI regions 110a and 110b are formed in the major
surface 10a of the semiconductor substrate 10. The STI region 110b
separates two oxide-define (OD) regions or active areas: the first
OD region 102 and the second OD region 104. The STI regions 110a
and 110b extend into the semiconductor substrate 10 to a trench
depth d.sub.1 that is shallower than the junction depth of the ion
well 12. For example, the trench depth d.sub.1 may range between
0.1 micrometers and 1.0 micrometers. The ion well 12 of the second
conductivity type completely overlaps with the first OD region
102.
[0143] A read transistor 20 is formed within the first OD region
102. According to the embodiment, the read transistor 20 is a PMOS
transistor and may comprise a P.sup.+ drain region 202, a P.sup.+
source region 204, a channel region 210 between the P.sup.+ drain
region 202 and the P.sup.+ source region 204, a floating gate 206
formed of a single polycrystalline silicon layer overlying the
channel region 210, and a gate dielectric layer 208 between the
floating gate 206 and the channel region 210. The P.sup.+ drain
region 202 is separated from the N.sup.+ contact region 120 by the
STI region 110a. According to the embodiment, the gate dielectric
layer 208 is made of the same material and has the same thickness
as that used in the logic circuitry on the same integrated circuit
chip. The P.sup.+ drain region 202 may be electrically coupled to a
drain voltage (V.sub.D) and the P.sup.+ source region 204 may be
electrically coupled to a source voltage (V.sub.S).
[0144] A coupling capacitor 30 is formed within the second OD
region 104. According to the embodiment, the coupling capacitor 30
may comprise a shallow ion well 320' of the second conductivity
type, a heavily-doped, ultra-shallow dopant region 310, a contact
region 304 in the heavily-doped, ultra-shallow dopant region 310,
and a lightly-doped dopant region 312 of the first conductivity
type. The heavily-doped, ultra-shallow dopant region 310 is formed
within the lightly-doped dopant region 312 of the first
conductivity type. A charge storage floating gate 306 formed of a
single polycrystalline silicon layer overlies the heavily-doped,
ultra-shallow dopant region 310. A gate dielectric layer 308 is
provided between the charge storage floating gate 306 and
heavily-doped, ultra-shallow dopant region 310.
[0145] According to the embodiment, the shallow ion well 320' of
the second conductivity type may be a shallow N well, the
heavily-doped, ultra-shallow dopant region 310 may be an N.sup.+
ultra-shallow dopant region, and the contact region 304 of the
first conductivity type may be an N.sup.+ contact region. A PN
junction 313 between the shallow ion well 320' of the second
conductivity type and the lightly-doped dopant region 312 of the
first conductivity type has a junction depth d.sub.5 that is
shallower than the trench depth d.sub.1 of the STI regions 110a and
110b.
[0146] The single-poly NVM cell 4a further comprises an extra
P.sup.- region 360 encompassing the P.sup.+ contact region 304. The
extra P.sup.- region 360 has a junction depth d.sub.7 that is
deeper than d.sub.5. The extra P.sup.- region 360 overlaps with a
right portion of the lightly-doped dopant region 312 of the first
conductivity type. The extra P.sup.- region 360 increases breakdown
voltage of the memory device.
[0147] An additional ion well 14 of the second conductivity type
such as an N well (NW) according to the embodiment is provided
within the second OD region 104. The ion well 14 of the second
conductivity type, which is spaced apart from the ion well 12,
partially overlaps with the second OD region 104. The ion well 14
of the second conductivity type partially overlaps with the well
structure consisting of the heavily-doped, ultra-shallow dopant
region 310 (shallow N.sup.+), the lightly-doped dopant region 312
of the first conductivity type (shallow P.sup.-), and the shallow
ion well 320' of the second conductivity type (shallow Ni.
According to the embodiment, the ion wells 12 and 14 may be formed
by using the same photo mask and the same ion implantation process,
and therefore may have substantially the same doping concentration
and junction depth. The P.sup.+ contact region 304 and the extra
P.sup.- region 360 are formed within the ion well 14 of the second
conductivity type. The charge storage floating gate 306 partially
overlaps with the ion well 14 of the second conductivity type.
[0148] An additional ion well 16 of the first conductivity type
such as a P well (PW) according to the embodiment is provided
within the second OD region 104. The ion well 16 of the first
conductivity type partially overlaps with the second OD region 104.
The ion well 16 of the first conductivity type partially overlaps
with the well structure consisting of the heavily-doped,
ultra-shallow dopant region 310 (shallow N.sup.+), the
lightly-doped dopant region 312 of the first conductivity type
(shallow P.sup.-), and the shallow ion well 320' of the second
conductivity type (shallow N.sup.-) on the left side of the charge
storage floating gate 306. The STI region 110b is disposed within
the ion well 16 of the first conductivity type. The ion well 16 of
the first conductivity type is interposed between the ion well 12
and the ion well 14.
[0149] It is to be understood that according to another embodiment,
the heavily-doped, ultra-shallow dopant region 310 may have the
first conductivity type. For example, the shallow ion well 320' may
be a shallow N well, the heavily-doped and the ultra-shallow dopant
region 310 may be a P.sup.+ ultra-shallow dopant region.
[0150] According to the embodiment, the charge storage floating
gate 306 of the coupling capacitor 30 is electrically coupled to
the floating gate 206 of the read transistor 20. The P.sup.+
contact region 304, the heavily-doped, ultra-shallow dopant region
310 (shallow N.sup.+), the lightly-doped dopant region 312 of the
first conductivity type (shallow P.sup.-), the extra P.sup.- region
360, and the shallow ion well 320' of the second conductivity type
(shallow N.sup.-) may be commonly connected to a control gate
voltage (V.sub.CG). The shallow ion well 320' of the second
conductivity type and the heavily-doped, ultra-shallow dopant
region 310 (shallow N.sup.+) may be electrically coupled to
V.sub.CG through the N.sup.+ contact region 304 formed within the
ultra-shallow dopant region 310 of the first conductivity type
(shallow N.sup.+). The gate dielectric layers 208 and 308 are made
of the same material and have the same thickness as that used in
the logic circuitry on the same integrated circuit chip. An
additional layer or photomask may be added to the current
single-poly logic process in order to form the shallow ion well
320' of the second conductivity type, the heavily-doped,
ultra-shallow dopant region 310 (shallow N.sup.+), and the
lightly-doped dopant region 312 of the first conductivity type.
[0151] It is to be understood that although not shown in the
figures, a pair of sidewall spacers may be formed on the opposite
sidewalls of each of the floating gates 206 and 306, and a lightly
doped drain (LDD) regions may be formed under the sidewall
spacers.
[0152] The P.sup.+ drain region 202, the P.sup.+ source region 204,
the P.sup.+ contact region 304 have substantially the same NP
junction depth. The shallow ion well 320' has a junction depth
d.sub.6. According to the embodiment, the junction depth d.sub.6 is
deeper than the junction depth d.sub.5 and is deeper than the
trench depth d.sub.1 of the STI regions 110a and 110b, while
shallower than the junction depth of the ion well 12. According to
the embodiment, the multi-well scheme (shallow N.sup.+ 310/shallow
P.sup.- 312/shallow N.sup.- 320/P-Sub 10) directly under the charge
storage floating gate 306 may serve as a charge pumping element.
The heavily-doped, ultra-shallow dopant region 310 (shallow
N.sup.+) enhances the coupling ratio of the single-poly NVM cell
5a.
[0153] To form such multi-well scheme (shallow N.sup.+ 310/shallow
P.sup.- 312/shallow N.sup.- 320/P-Sub 10), a patterned implant mask
layer (not shown) may be formed on the semiconductor substrate 10
to reveal the second OD region 104. A first ion implantation
process may be carried out to implant N type dopants into the
second OD region 104 to form the shallow N.sup.- 320. A second ion
implantation process is then carried out to implant P type dopants
into the second OD region 104 to form the shallow P.sup.- 312. A
third ion implantation process is then carried out to implant N
type dopants into the second OD region 104 to form the shallow
N.sup.+ 310. Thereafter, a thermal oxidation process is performed
to form the gate dielectric layer 308. An etch-back process may be
performed to remove an upper portion of the gate dielectric layer
308. By thinning down the thickness of the gate dielectric layer
308, the coupling ratio of the memory cell is increased.
[0154] According to another embodiment, to form such multi-well
scheme (shallow N.sup.+ 310/shallow P.sup.- 312/shallow N.sup.-
320/P-Sub 10), a patterned implant mask layer (not shown) may be
formed on the semiconductor substrate 10 to reveal the second OD
region 104. A first ion implantation process may be carried out to
implant N type dopants into the second OD region 104 to form the
shallow N.sup.- 320. A second ion implantation process is then
carried out to implant P type dopants into the second OD region 104
to form the shallow P.sup.- 312. Thereafter, a thermal oxidation
process is performed to form the gate dielectric layer 308. After
the formation of the gate dielectric layer 308, a third ion
implantation process is carried out to implant N type dopants into
the second OD region 104 to form a shallow N.sup.+ 310. The heavily
doped shallow N.sup.+ 310 helps increase the coupling ratio.
[0155] According to still another embodiment, the shallow N.sup.+
310, the shallow P.sup.- 312 and shallow N.sup.- 320 may be formed
after the formation of the gate dielectric layer 308. For example,
a thermal oxidation process is first performed to form the gate
dielectric layer 308. A first ion implantation process may be
carried out to implant N type dopants into the second OD region 104
to form the shallow N.sup.- 320. A second and third ion
implantation processes are then carried out to implant dopants into
the second OD region 104 to form the shallow N.sup.+ 310 and the
shallow P.sup.- 312 respectively.
[0156] It should be recognized that although the present invention
has been illustrated schematically with the use of certain
conductivity types, the opposite conductive types can also be
implemented.
[0157] FIG. 6B is a partial, schematic, cross-sectional view of a
single-poly NVM cell having an NMOS read transistor. As shown in
FIG. 6B, according to another embodiment, the read transistor 20 of
the single-poly NVM cell 6b may be an NMOS transistor formed in the
ion well 12 of P type (PW) that may be electrically connected to a
P well voltage (V.sub.PW) through a P.sup.+ contact region 120.
Likewise, the single-poly NVM cell 6b further includes a coupling
capacitor 30. The coupling capacitor 30 is formed within the second
OD region 104. The coupling capacitor 30 comprises a shallow ion
well 320' of the second conductivity type, a heavily-doped,
ultra-shallow dopant region 310 in the shallow ion well 320' of the
second conductivity type, a lightly-doped dopant region 312 of the
first conductivity type, a contact region 304 in the heavily-doped,
ultra-shallow dopant region 310, an extra P.sup.- region 360
encompassing the contact region 304, a charge storage floating gate
306 formed of a single polycrystalline silicon layer overlying the
heavily-doped, ultra-shallow dopant region 310, and a gate
dielectric layer 308 between the charge storage floating gate 306
and heavily-doped, ultra-shallow dopant region 310.
[0158] An additional ion well 14 of the second conductivity type
such as an N well (NW) according to the embodiment is provided
within the second OD region 104. The ion well 14 of the second
conductivity type, which is spaced apart from the ion well 12 of P
type, partially overlaps with the second OD region 104. The ion
well 14 of the second conductivity type partially overlaps with the
well structure consisting of the heavily-doped, ultra-shallow
dopant region 310 (shallow N.sup.+), the lightly-doped dopant
region 312 of the first conductivity type (shallow P.sup.-), and
the shallow ion well 320' of the second conductivity type (shallow
N.sup.-).
[0159] An additional ion well 16 of the first conductivity type
such as a P well (PW) according to the embodiment is provided
within the second OD region 104 between the ion well 12 and the ion
well 14. The ion well 16 of the first conductivity type partially
overlaps with the second OD region 104. The ion well 16 of the
first conductivity type partially overlaps with the well structure
consisting of the heavily-doped, ultra-shallow dopant region 310
(shallow N.sup.+), the lightly-doped dopant region 312 of the first
conductivity type (shallow P.sup.-), and the shallow ion well 320'
of the second conductivity type (shallow N.sup.-) on the left side
of the charge storage floating gate 306.
[0160] According to the embodiment, the shallow ion well 320' of
the second conductivity type may be a shallow N well, the
heavily-doped, ultra-shallow dopant region 310 may be an N.sup.+
ultra-shallow dopant region, the lightly-doped dopant region 312 of
the first conductivity type is a P.sup.- dopant region, and the
contact region 304 may be an N.sup.+ contact region. A PN junction
313 between the shallow ion well 320' of the second conductivity
type and the lightly-doped dopant region 312 of the first
conductivity type has a junction depth d5 that is shallower than
the trench depth d1 of the STI regions 110a and 110b.
[0161] According to the embodiment, the charge storage floating
gate 306 of the coupling capacitor 30 is electrically coupled to
the floating gate 206 of the read transistor 20. The P.sup.+
contact region 304, the heavily-doped, ultra-shallow dopant region
310, the lightly-doped dopant region 312 of the first conductivity
type, and the shallow ion well 320' of the second conductivity type
(shallow N.sup.-) may be commonly connected to a control gate
voltage (V.sub.CG). The shallow ion well 320' of the second
conductivity type and the heavily-doped, ultra-shallow dopant
region 310 may be electrically coupled to V.sub.CG through the
contact region 304 formed within the ultra-shallow dopant region
310. The gate dielectric layers 208 and 308 are made of the same
material and have the same thickness as that used in the logic
circuitry on the same integrated circuit chip.
[0162] FIG. 7 is a schematic, cross-sectional diagram of a
conventional cell structure. As shown in FIG. 7, the N well NW1
that is directly under the floating gate FG1 is spaced apart from
the N well NW2 that is directly under the floating gate FG2. The
spacing between NW1 and NW2 is denoted as S. The prior art has a
larger S because of the NW-NW spacing design rule. For example, S
should be 1.4 .mu.m for 0.18 .mu.m processes. For 0.18 .mu.m
processes, the N well junction depth may be about 10,000 angstroms,
the STI depth may be about 2,300 angstroms, and the diffusion depth
may be about 1,000 angstroms. Without the shallow N+/P+ in NW2, the
control gate-to-floating gate coupling becomes worse. It is
advantageous to use the present invention because the spacing S
between two adjacent coupling wells can be reduced. For example,
FIG. 8 shows an exemplary layout that illustrates the reduced
spacing S between two adjacent coupling wells. In FIG. 8, each
coupling area (coupling well) is electrically coupled to four
floating gates (FG). Contact areas for the bit lines and coupling
areas are also illustrated.
[0163] Those skilled in the art will readily observe that numerous
modifications and alterations of the device and method may be made
while retaining the teachings of the invention. Accordingly, the
above disclosure should be construed as limited only by the metes
and bounds of the appended claims.
* * * * *