U.S. patent application number 14/451983 was filed with the patent office on 2015-02-19 for image sensor and method of operating the same.
The applicant listed for this patent is SAMSUNG ELECTRONICS CO., LTD.. Invention is credited to Seok-yong HONG, Sun Jung KIM, Tae Chan KIM, Kwang Hyun LEE.
Application Number | 20150049230 14/451983 |
Document ID | / |
Family ID | 50474612 |
Filed Date | 2015-02-19 |
United States Patent
Application |
20150049230 |
Kind Code |
A1 |
LEE; Kwang Hyun ; et
al. |
February 19, 2015 |
IMAGE SENSOR AND METHOD OF OPERATING THE SAME
Abstract
A method of operating an image sensor includes generating a
plurality of sub pixel signals using a sub pixel group. The sub
pixel group includes a plurality of sub pixels and corresponds to a
single pixel. The method further includes generating a pixel signal
having a plurality of bits based on a result of comparing the sub
pixel signals with a reference voltage. Each of the sub pixels is a
1-transistor (1T) pixel that detects at least one photogenerated
charge and includes only one transistor.
Inventors: |
LEE; Kwang Hyun;
(Seongnam-si, KR) ; KIM; Sun Jung; (Yongin-si,
KR) ; KIM; Tae Chan; (Yongin-si, KR) ; HONG;
Seok-yong; (Seoul, KR) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
SAMSUNG ELECTRONICS CO., LTD. |
Suwon-si |
|
KR |
|
|
Family ID: |
50474612 |
Appl. No.: |
14/451983 |
Filed: |
August 5, 2014 |
Current U.S.
Class: |
348/308 |
Current CPC
Class: |
H04N 5/363 20130101;
H01L 27/1461 20130101; H04N 5/378 20130101; H01L 27/14643 20130101;
H04N 5/3745 20130101; H01L 27/14612 20130101; H04N 5/374 20130101;
H01L 27/14614 20130101; H04N 5/3742 20130101 |
Class at
Publication: |
348/308 |
International
Class: |
H04N 5/374 20060101
H04N005/374 |
Foreign Application Data
Date |
Code |
Application Number |
Aug 14, 2013 |
KR |
10-2013-0096857 |
Claims
1. A method of operating an image sensor, the method comprising:
generating a plurality of sub pixel signals using a sub pixel
group, the sub pixel group including a plurality of sub pixels and
corresponding to a single pixel; and generating a pixel signal
having a plurality of bits based on a result of comparing the sub
pixel signals with a reference voltage, wherein each of the sub
pixels is a 1-transistor (1T) pixel that detects at least one
photogenerated charge and includes only one transistor.
2. The method of claim 1, wherein the sub pixels are arranged in a
matrix of "n" rows and "m" columns in the sub pixel group, and the
generating the pixel signal comprises: comparing the sub pixel
signals with the reference voltage to generate comparison signals
for the respective columns; generating a count result by counting
each of the comparison signals; and adding count results generated
for the respective columns to generate the pixel signal.
3. The method of claim 2, wherein the generating the pixel signal
further comprises: transmitting sub pixel signals output to each of
the columns to an input node of a comparator using a capacitor; and
resetting the input node of the comparator to a power supply
voltage.
4. The method of claim 3, wherein the generating the pixel signal
further comprises: sequentially increasing a voltage of the input
node of the comparator by a hole voltage.
5. The method of claim 4, wherein the generating the pixel signal
further comprises: resetting an output node of the comparator to a
ground voltage.
6. The method of claim 1, wherein a threshold voltage of the single
transistor is changed according to the at least one photogenerated
charge.
7. An image sensor comprising: a pixel array comprising a plurality
of sub pixel groups, each of the sub pixel groups including a
plurality of sub pixels and corresponding to a single pixel; a
readout block configured to generate a pixel signal having a
plurality of bits based on a result of comparing a plurality of sub
pixel signals generated by each of the sub pixel groups with a
reference voltage; and a control unit configured to control the
pixel array and the readout block, wherein each of the sub pixels
is a 1-transistor (1T) pixel that detects at least one
photogenerated charge and includes only one transistor.
8. The image sensor of claim 7, wherein the sub pixels are arranged
in a matrix of "n" rows and "m" columns in each of the sub pixel
groups, and the readout block comprises: a comparator configured to
compare sub pixel signals of each of the columns with the reference
voltage to generate a comparison signal for each column; a counter
configured to generate a count result by counting the comparison
signal; and an adder configured to generate the pixel signal by
adding count results generated for the respective columns.
9. The image sensor of claim 8, wherein the counter is an
asynchronous counter that receives the comparison signal as a clock
signal.
10. The image sensor of claim 9, wherein the readout block further
comprises: a capacitor configured to transmit the sub pixel signals
to an input node of the comparator; and a first reset switch
configured to reset the input node of the comparator to a power
supply voltage.
11. The image sensor of claim 10, wherein the readout block further
comprises: a hole injection unit configured to sequentially
increase a voltage of the input node of the comparator by a hole
voltage.
12. The image sensor of claim 11, wherein the hole injection unit
comprises a plurality of hole injection transistors which are
connected in series between the power supply voltage and the input
node of the comparator.
13. The image sensor of claim 12, wherein the hole injection
transistors are P-channel metal oxide semiconductor (PMOS)
transistors.
14. The image sensor of claim 11, wherein the readout block further
comprises a second switch configured to reset an output node of the
comparator to a ground voltage.
15. The image sensor of claim 7, wherein a threshold voltage of the
single transistor is changed according to the at least one
photogenerated charge.
16. A method of operating an image sensor, comprising: receiving,
at a readout circuit, a plurality of sub pixel signals from a
plurality of one transistor pixels; generating, by the readout
circuit, a pixel signal based on the received sub pixel signals and
a reference voltage.
17. The method of claim 16, wherein the generating comprises:
comparing each of the sub pixel signals to the reference voltage;
and generating the pixel signal based on results of the
comparing.
18. The method of claim 16, wherein the generating comprises:
producing count values, each count value associated with a
respective once of the sub pixel signals based on a duration that a
voltage corresponding to the respective sub pixel signal meets a
relationship with the reference voltage; and determining the pixel
signal based on the generated count values.
19. The method of claim 18, wherein the generating comprising:
changing the voltage corresponding to the respective sub pixel
signal over time.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application claims priority under 35 U.S.C.
.sctn.119(a) from Korean Patent Application No. 10-2013-0096857
filed on Aug. 14, 2013, the disclosure of which is hereby
incorporated by reference in its entirety.
BACKGROUND
[0002] Some embodiments of the inventive concepts relate to an
image sensor and/or a method of operating the same, and more
particularly, to an image sensor for sensing a signal of a
1-transistor (T) pixel having a digital output and/or a method of
operating the same.
[0003] An image sensor is a device that converts an optical image
into an electrical signal. The image sensor includes a plurality of
pixels. When each of the pixels includes a transfer transistor, a
reset transistor, a selection transistor, and a source follower
transistor, each pixel may be called a 4T pixel.
[0004] With the development of technology, the size of pixels has
been decreased. For instance, instead of 4T pixels, 1T pixels,
i.e., pixels with a single-transistor architecture have been
developed.
SUMMARY
[0005] At least one embodiment relates to a method of operating an
image sensor.
[0006] In one embodiment, the method includes generating a
plurality of sub pixel signals using a sub pixel group. The sub
pixel group includes a plurality of sub pixels and corresponds to a
single pixel. The method further includes generating a pixel signal
having a plurality of bits based on a result of comparing the sub
pixel signals with a reference voltage. Each of the sub pixels is
1-transistor (1T) pixel that detects at least one photogenerated
charge and includes only one transistor.
[0007] The sub pixels may be arranged in a matrix of "n" rows and
"m" columns in the sub pixel group. The generating the pixel signal
may include comparing the sub pixel signals with the reference
voltage to generate comparison signals for the respective columns,
generating a count result by counting each of the comparison
signal, and adding count results generated for the respective
columns to generate the pixel signal.
[0008] The generating the pixel signal may further include
transmitting sub pixel signals output to each of the columns to an
input node of a comparator using a capacitor and resetting the
input node of the comparator to a power supply voltage.
[0009] The generating the pixel signal may further include
sequentially increasing a voltage of the input node of the
comparator by a hole voltage.
[0010] The generating the pixel signal may further include
resetting an output node of the comparator to a ground voltage.
[0011] A threshold voltage of the single transistor may be changed
according to the at least one photogenerated charge.
[0012] In another embodiment, the method of operating an image
sensor includes receiving, at a readout circuit, a plurality of sub
pixel signals from a plurality of one transistor pixels, and
generating, by the readout circuit, a pixel signal based on the
received sub pixels signals and a reference voltage.
[0013] In one embodiment, the generating includes comparing each of
the sub pixel signals to the reference voltage, and generating the
pixel signal based on results of the comparing.
[0014] In another embodiment, the generating includes producing
count values. Each count value is associated with a respective once
of the sub pixel signals and is based on a duration that a voltage
corresponding to the respective sub pixel signal meets a
relationship with the reference voltage. The pixel signal is
determined based on the generated count values.
[0015] In one embodiment, the generating includes changing the
voltage corresponding to the respective sub pixel signal over
time.
[0016] At least one embodiment relates to an image sensor.
[0017] In one embodiment, the image sensor includes a pixel array
including a plurality of sub pixel groups, each of the sub pixel
groups including a plurality of sub pixels and corresponds to a
single pixel; a readout block configured to generate a pixel signal
having a plurality of bits based on a result of comparing a
plurality of sub pixel signals generated by each of the sub pixel
groups with a reference voltage; and a control unit configured to
control the pixel array and the readout block. Each of the sub
pixels is a 1-transistor (1T) pixel that detects at least one
photogenerated charge.
[0018] The sub pixels may be arranged in a matrix of "n" rows and
"m" columns in each of the sub pixel groups. The readout block may
include a comparator configured to compare sub pixel signals of
each of the columns with the reference voltage to generate a
comparison signal for each column, a counter configured to generate
a count result by counting the comparison signal, and an adder
configured to generate the pixel signal by adding count results
generated for the respective columns.
[0019] The counter may be an asynchronous counter that receives the
comparison signal as a clock signal.
[0020] The readout block may further include a capacitor configured
to transmit the sub pixel signals to an input node of the
comparator and a first reset switch configured to reset the input
node of the comparator to a power supply voltage.
[0021] The readout block may further include a hole injection unit
configured to sequentially increase a voltage of the input node of
the comparator by a hole voltage.
[0022] The hole injection unit may include a plurality of hole
injection transistors which are connected in series between the
power supply voltage and the input node of the comparator.
[0023] The hole injection transistors may be P-channel metal oxide
semiconductor (PMOS) transistors.
[0024] The readout block may further include a second switch
configured to reset an output node of the comparator to a ground
voltage.
[0025] A threshold voltage of the single transistor may be changed
according to the at least one photogenerated charge.
BRIEF DESCRIPTION OF THE DRAWINGS
[0026] The above and other features and advantages of the inventive
concepts will become more apparent by describing in detail example
embodiments thereof with reference to the attached drawings in
which:
[0027] FIG. 1 is a block diagram of an image sensor according to
some embodiments of the inventive concepts;
[0028] FIG. 2 is a block diagram of an image processing system
including the image sensor illustrated in FIG. 1;
[0029] FIG. 3 is a detailed block diagram of a sub pixel in a pixel
array illustrated in FIG. 2;
[0030] FIG. 4 is a diagram of a layout for forming the sub pixel
illustrated in FIG. 3;
[0031] FIG. 5 is a diagram of a cross section of a semiconductor
substrate taken in direction A in the layout illustrated in FIG. 4
according to some embodiments of the inventive concepts;
[0032] FIG. 6 is a diagram of a cross section of a semiconductor
substrate taken in direction A in the layout illustrated in FIG. 4
according to another embodiment of the inventive concepts;
[0033] FIG. 7 is a diagram of a cross section of a semiconductor
substrate taken in direction A in the layout illustrated in FIG. 4
according to a further embodiment of the inventive concepts;
[0034] FIG. 8 is a block diagram of a connection between the pixel
array and a readout block illustrated in FIG. 2 according to some
embodiments of the inventive concepts;
[0035] FIG. 9 is a block diagram of a connection between the pixel
array and the readout block illustrated in FIG. 2 according to
another embodiment of the inventive concepts;
[0036] FIG. 10 is a detailed block diagram of an example of a
readout circuit illustrated in FIGS. 8 and 9;
[0037] FIG. 11 is a timing chart for explaining a comparison signal
of a comparator illustrated in FIG. 10;
[0038] FIG. 12 is a detailed block diagram of a counter illustrated
in FIG. 10;
[0039] FIG. 13 is a timing chart for explaining a count result of
the counter illustrated in FIG. 10;
[0040] FIG. 14 is a detailed block diagram of another example of
the readout circuit illustrated in FIGS. 8 and 9;
[0041] FIG. 15 is a detailed block diagram of a hole injection unit
illustrated in FIG. 14;
[0042] FIGS. 16A and 16B are timing charts for explaining a
comparison signal of a comparator illustrated in FIG. 14;
[0043] FIG. 17 is a detailed block diagram of a counter illustrated
in FIG. 14;
[0044] FIG. 18 is a timing chart for explaining a count result of
the counter illustrated in FIG. 14;
[0045] FIG. 19 is a flowchart of a method of operating the image
sensor illustrated in FIG. 1 according to some embodiments of the
inventive concepts;
[0046] FIG. 20A is a detailed flowchart of an operation of
generating a pixel signal in the method illustrated in FIG. 19;
[0047] FIG. 20B illustrates a flow chart of the method of
generating a pixel signal with the timing relationships shown, and
with reference to FIG. 14.
[0048] FIG. 21 is a block diagram of an electronic system including
an image sensor illustrated in FIG. 1 according to some embodiments
of the inventive concepts; and
[0049] FIG. 22 is a block diagram of an electronic system including
an image sensor illustrated in FIG. 1 according to other
embodiments of the inventive concepts.
DETAILED DESCRIPTION OF THE EMBODIMENTS
[0050] The inventive concepts now will be described more fully
hereinafter with reference to the accompanying drawings, in which
embodiments of the invention are shown. This invention may,
however, be embodied in many different forms and should not be
construed as limited to the embodiments set forth herein. Rather,
these embodiments are provided so that this disclosure will be
thorough and complete, and will fully convey the scope of the
invention to those skilled in the art. In the drawings, the size
and relative sizes of layers and regions may be exaggerated for
clarity. Like numbers refer to like elements throughout.
[0051] It will be understood that when an element is referred to as
being "connected" or "coupled" to another element, it can be
directly connected or coupled to the other element or intervening
elements may be present. In contrast, when an element is referred
to as being "directly connected" or "directly coupled" to another
element, there are no intervening elements present. As used herein,
the term "and/or" includes any and all combinations of one or more
of the associated listed items and may be abbreviated as "/".
[0052] It will be understood that, although the terms first,
second, etc. may be used herein to describe various elements, these
elements should not be limited by these terms. These terms are only
used to distinguish one element from another. For example, a first
signal could be termed a second signal, and, similarly, a second
signal could be termed a first signal without departing from the
teachings of the disclosure.
[0053] The terminology used herein is for the purpose of describing
particular embodiments only and is not intended to be limiting of
the invention. As used herein, the singular forms "a", "an" and
"the" are intended to include the plural forms as well, unless the
context clearly indicates otherwise. It will be further understood
that the terms "comprises" and/or "comprising," or "includes"
and/or "including" when used in this specification, specify the
presence of stated features, regions, integers, steps, operations,
elements, and/or components, but do not preclude the presence or
addition of one or more other features, regions, integers, steps,
operations, elements, components, and/or groups thereof.
[0054] Unless otherwise defined, all terms (including technical and
scientific terms) used herein have the same meaning as commonly
understood by one of ordinary skill in the art to which this
invention belongs. It will be further understood that terms, such
as those defined in commonly used dictionaries, should be
interpreted as having a meaning that is consistent with their
meaning in the context of the relevant art and/or the present
disclosure, and will not be interpreted in an idealized or overly
formal sense unless expressly so defined herein.
[0055] FIG. 1 is a block diagram of an image sensor 100 according
to some embodiments of the inventive concepts. FIG. 2 is a block
diagram of an image processing system 10 including the image sensor
100 illustrated in FIG. 1.
[0056] Referring to FIGS. 1 and 2, the image processing system 10
may include the image sensor 100, a digital signal processor (DSP)
200, a display unit 300, and a lens 500. The image sensor 100 may
include a pixel array 110, a control unit 150, and a readout block
190.
[0057] The pixel array 110 may include a plurality of sub pixels
(130 in FIG. 3) that detect at least one photogenerated charge and
generate a sub pixel signal in a digital form. The pixel array 110
may also include a plurality of sub pixel groups (e.g., first
through fourth sub pixel groups in FIG. 8) that include a plurality
of sub pixels 130 corresponding to a single pixel.
[0058] Each sub pixel 130 includes a single transistor (SX in FIG.
3) and a photoelectric conversion element such as a photo diode or
a pinned photo diode. Each pixel includes a single transistor,
thereby increasing the degree of integration of the image sensor
100. For instance, the image sensor 100 may include pixels having a
size of 0.1.times.0.1 .mu.m or less. The pixel array 110 senses
light using a plurality of photoelectric conversion elements and
converts the light into an electrical signal, thereby generating
sub pixel signals. The operation of the sub pixels 130 will be
described in detail with reference to FIG. 3 later.
[0059] The control unit 150 may generate a plurality of control
signals for controlling the operations of the pixel array 110 and
the readout block 190 and apply the control signals to the pixel
array 110 and the readout block 190. The control unit 150 may
include a row driver 160, a column driver 165, a timing generator
170, and a control register block 180.
[0060] The row driver 160 drives the pixel array 110 in row units.
In detail, the same control signals, i.e., a gate signals (e.g.,
one of VG1 through VGn in FIG. 10) and a source signal (e.g., one
of VS1 through VSn in FIG. 10) are applied to all pixels in one
row. The row driver 160 may decode a control signal output from the
timing generator 170 and then apply the control signal to each of
the rows in the pixel array 110.
[0061] The pixel array 110 outputs a sub pixel signal from a row
selected by the gate signals (VG1 through VGn in FIG. 10) and the
source signals (VS1 through VSn in FIG. 10), which are provided
from the row driver 160, to the readout block 190.
[0062] The column driver 165 may generate a plurality of control
signals and control the operation of the readout block 190
according to the control of the timing generator 170. The control
signals will be described in detail with reference to FIGS. 8
through 18 later.
[0063] The timing generator 170 may apply a control signal or a
clock signal to the row driver 160 and the column driver 165 to
control the operations or the timing of the row driver 160 and the
column driver 165. The timing generator 170 may generate the
control signal or the clock signal, which will be applied to the
row driver 160 and the column driver 165, using a control signal
CS, and a clock signal CLK, which are received from an external
device (e.g., a host). At this time, the control register block 180
may be controlled by a camera control unit 210 to store or buffer
the control signal CS and the clock signal CLK.
[0064] The readout block 190 generates a pixel signal PS, having a
plurality of bits based on a result of comparing a plurality of sub
pixel signals generated by each of the plurality of sub pixel
groups (e.g., the first through fourth pixel groups in FIG. 8) with
a reference voltage (e.g., Vref in FIG. 11), and outputs the pixel
signal PS to the DSP 200. The DSP 200 may process the pixel signal
PS, which has been sensed and output by the image sensor 100, to
generate image data and may output the image data to the display
unit 300.
[0065] The DSP 200 may include the camera control unit 210, an
image signal processor (ISP) 220, and a personal computer interface
(PC I/F) 230. The camera control unit 210 controls the control
register block 180. At this time, the camera control unit 210 may
control the control register block 180 using an inter-integrated
circuit (I2C), but the scope of the inventive concepts is not
restricted thereto.
[0066] The ISP 220 processes the pixel signal PS output from the
readout block 190 into image data for people to view, and outputs
the image data to the display unit 300 through the PC I/F 230. The
ISP 220 may be implemented in a chip separated from the image
sensor 100. In other embodiments, the ISP 220 and the image sensor
100 may be integrated into a single chip.
[0067] The display unit 300 may be any device that can output an
image. For instance, the display unit 300 may be implemented as a
computer, a mobile phone, a smart phone, or an image output
terminal.
[0068] FIG. 3 is a detailed block diagram of a sub pixel 130 in the
pixel array 110 illustrated in FIG. 2. Referring to FIGS. 1 through
3, the sub pixel 130 may include a single transistor SX and a photo
diode PD. Although it is assumed that the photo diode PD is used as
a photoelectric conversion element for clarity of the description,
the scope of the inventive concepts is not restricted thereto.
[0069] The photo diode PD may have a first end connected to a
ground and a second end connected to or electrically separated from
the body of the single transistor SX. The photo diode PD may hold
photogenerated charges, generated proportional to the intensity of
incident light that has passed through the lens 500.
[0070] The single transistor SX has a source and a gate which are
connected to the row driver 160 to receive a source signal VS (one
of VS1 through VSn in FIGS. 10 and 14) and a gate signal VG (one of
VG1 through VGn in FIGS. 10 and 14). The sub pixel 130 may have
three operation modes, i.e., an integration mode, a reset mode, and
a readout mode according to the source signal VS and the gate
signal VG.
[0071] In the integration mode, among photogenerated charges (i.e.,
electrons and holes) generated by incident light, one type of
photogenerated charge (i.e., electrons or holes) is accumulated in
the photo diode PD. In order to induce photogenerated charge
amplification using an avalanche effect in the integration mode,
the source signal VS, the gate signal VG, and a substrate voltage
may be a first integration voltage, a second integration voltage,
and 0V, respectively. For instance, when the single transistor SX
is a P-channel metal oxide semiconductor (PMOS) transistor, the
first integration voltage may be 0 V and the second integration
voltage may be a power supply voltage (VDD).
[0072] In the reset mode, the photogenerated charges accumulated in
the photo diode PD are drained through a source or a drain. In the
reset mode, the source signal VS, the gate signal VG, and the
substrate voltage may be a first reset voltage, a second reset
voltage, and 0V, respectively. For instance, when the single
transistor SX is a PMOS transistor, the first reset voltage may be
the power supply voltage VDD and the second reset voltage may be 0
V.
[0073] In the readout mode, a sub pixel signal corresponding to the
photogenerated charges accumulated in the photo diode PD is output
through a column line COL (one of COL1 through COLM in FIGS. 10 and
14). The sub pixel signal includes an image signal and a reset
signal. The image signal is a signal output in the readout mode
right after the integration mode, and the reset signal is a signal
output in the readout mode right after the reset mode. For
convenience sake, in the description, the description of the
readout mode for the reset signal will be omitted.
[0074] In the readout mode, the body voltage of the signal
transistor SX may be different depending on the photogenerated
charges accumulated in the photo diode PD. The threshold voltage
(Vth) of the single transistor SX may vary with the body voltage.
When Vth of the single transistor SX changes, the same result as
that obtained when a source voltage changes can be obtained. By
using this principle, the sub pixel 130 may output a digital sub
pixel signal having at least two levels.
[0075] In the readout mode, the source signal VS, the gate signal
VG, and the substrate voltage may be a first read voltage, a second
read voltage, and 0V, respectively. For instance, when the single
transistor SX is a PMOS transistor, the first read voltage may be
the power supply voltage VDD and the second read voltage may be a
read voltage (VREAD in FIGS. 11 and 16A) lower than Vth of the
single transistor SX when there is no influence from the photo
diode PD.
[0076] When the single transistor SX enters the readout mode at the
reception of voltage, the change in Vth of the single transistor SX
according to the photogenerated charges accumulated at the photo
diode PD may be sensed and a drain voltage may be output as a pixel
signal. For instance, it is assumed that the single transistor SX
is a PMOS transistor, Vth of the single transistor SX when there is
no influence of the photo diode PD is 1 V and the read voltage
(V.sub.READ in FIGS. 11 and 16A) is 1.2 V. It is also assumed that
Vth of the single transistor SX changes to 1.4 V when one
photogenerated charge is generated by the photo diode PD. When one
photogenerated charge is generated by the photo diode PD, the
single transistor SX may be activated and a sub pixel signal may be
output at a high level (e.g., 1 V). When there is no photogenerated
charge generated by the photo diode PD, the single transistor SX
may be deactivated and the sub pixel signal may be output at a low
level (e.g., 0 V).
[0077] FIG. 4 is a diagram of a layout 130' for forming the sub
pixel 130 illustrated in FIG. 3. Referring to FIGS. 3 and 4, in the
layout 130', a source S, a gate G, and a drain D of the single
transistor SX are sequentially formed and a channel 131 connecting
the source S and the drain D is formed. In addition, a well layer
132 for electrical isolation from adjacent sub pixels (not shown)
may be included in the layout 130'. Although not shown, a shallow
trench isolation (STI) (not shown) for electrical isolation from
another sub pixel adjacent to the current sub pixel 130 in a
direction A or a direction perpendicular to the direction A may be
included in the layout 130'.
[0078] FIG. 5 is a diagram of a cross section 130A-1 of a
semiconductor substrate 140-1 taken in the direction A in the
layout 130' illustrated in FIG. 4 according to some embodiments of
the inventive concepts. Referring to FIGS. 4 and 5, the cross
section 130A-1 may include the source S, gate G and drain D of the
single transistor SX, the channel 131, the well layer 132, a photo
diode 133 (PD in FIG. 3), a gate insulating layer 134, a first
epitaxial layer 135, and a second epitaxial layer 136. The
semiconductor substrate 140-1 may be formed based on a silicon (Si)
substrate.
[0079] The source S, gate G and drain D of the single transistor SX
may function as the terminals of the single transistor SX. The
source S and the drain D may be formed as a high-concentration
doped region using ion implantation. When the single transistor SX
is a PMOS transistor, the source S and the drain D may be a P
region doped with P+ type impurities. Contrarily, when the single
transistor is an N-channel metal oxide semiconductor (NMOS)
transistor, the source S and the drain D may be an N region doped
with N+ type impurities. The gate G may be formed using poly
silicon.
[0080] The channel 131 may be formed to smooth the flow of carriers
between the source S and the drain D of the single transistor SX.
The carriers are holes when the single transistor SX is a PMOS
transistor and the carriers are electrons when the single
transistor SX is an NMOS transistor. The channel 131 is not
essential but may be selectively formed. The channel 131 may be
formed using Si, germanium (Ge), or SiGe.
[0081] The well layer 132 may be doped with N- type impurities when
the single transistor SX is a PMOS transistor and may be doped with
P- type impurities when the single transistor SX is an NMOS
transistor.
[0082] The photo diode 133 may be formed in the well layer 132. The
photo diode 133 may be doped with N type impurities when the single
transistor SX is a PMOS transistor and may be doped with P type
impurities when the single transistor SX is an NMOS transistor.
[0083] The gate insulating layer 134 may be formed for insulation
between the gate G and the channel 131. The gate insulating layer
134 may be formed using SiO.sub.2, SiON, SiN, Al.sub.2O.sub.3,
Si.sub.3N.sub.4, Ge.sub.xO.sub.yN.sub.z, Ge.sub.xSi.sub.yO.sub.z,
or a high dielectric constant material. The high dielectric
constant material may be formed using atomic layer deposition of
HfO.sub.2, ZrO.sub.2, Al.sub.2O.sub.3, Ta.sub.2O.sub.5, hafnium
silicate, zirconium silicate, or a combination thereof.
[0084] The first epitaxial layer 135 and the second epitaxial layer
136 may be formed using an epitaxial growth method. When the single
transistor SX is a PMOS transistor, the first and second epitaxial
layers 135 and 136 may be doped with P- type and P+ type
impurities, respectively. Contrarily, when the single transistor SX
is an NMOS transistor, the first and second epitaxial layers 135
and 136 may be doped with N- type and N+ type impurities,
respectively.
[0085] Although not shown in FIG. 5, conducting wires for the
operation of the pixel array 110, i.e., conducting wires for
connection with the row driver 160 and the readout block 190 may be
formed on the source S, the gate G, and the drain D to use back
side illumination (BSI) that increases the light guiding efficiency
of the photo diode 133.
[0086] FIG. 6 is a diagram of a cross section 130A-2 of a
semiconductor substrate 140-2 taken in the direction A in the
layout 130' illustrated in FIG. 4 according to another embodiment
of the inventive concepts. Referring to FIGS. 4 through 6, the gate
G may be embedded in the semiconductor substrate 140-2 using an
etching process in the cross section 130A-2. In other words, the
semiconductor substrate 140-2 may have a recess gate structure.
[0087] Accordingly, the channel 131 is also embedded in the
semiconductor substrate 140-2, so that the photo diode 133 is
formed within the semiconductor substrate 140-2. Therefore, the
distance from the photo diode 133 to the source S or the drain D
increases. When the distance between the photo diode 133 and the
source S or the drain D increases, the influence of the photo diode
133 to the channel 131 can be increased.
[0088] In particular, in an ultrasmall pixel structure in which the
length of the gate G is 50 nm or less, the distance from the photo
diode 133 to the source S or the drain D is very close, obstructing
the smooth operation of the single transistor SX. In other words,
when the length of the gate G is 50 nm or less, the distance
between the photo diode 133 and the source S or the drain D is so
close that the influence of the photo diode 133 to the channel 131
can be decreased. As a result, a pixel signal insensitive to the
photogenerated charges accumulated in the photo diode 133 may be
generated. Therefore, when the image sensor 100 is implemented
using microscopic pixels, the pixel array 110 may be formed in the
recess gate structure.
[0089] Apart from the above-described differences, the
semiconductor substrate 140-2 illustrated in FIG. 6 is
substantially the same as the semiconductor substrate 140-1
illustrated in FIG. 5.
[0090] FIG. 7 is a diagram of a cross section 130A-3 of a
semiconductor substrate 140-3 taken in the direction A in the
layout 130' illustrated in FIG. 4 according to a further embodiment
of the inventive concepts. Referring to FIGS. 4 through 7, the gate
G in the cross section 130A-3 may be formed in the recess gate
structure, as in the cross section 130A-2 illustrated in FIG.
6.
[0091] The photo diode 133 may be formed closer to the drain D than
to the source S around the gate G. In other words, the photo diode
133 may be formed in an asymmetric structure with respect to the
gate G. In other embodiments, the photo diode 133 may be formed
closer to the source S than to the drain D.
[0092] When the photo diode 133 is formed as shown in FIG. 7, the
entire size of the photo diode 133 may be decreased. When the
entire size of the photo diode 133 decreases, the distance between
photogenerated charges accumulated in the photo diode 133 and the
channel 131 also decreases, and therefore, the influence of the
photo diode 133 to the channel 131 increases according to Coulomb's
law.
[0093] In particular, the recess gate structure in which the photo
diode 133 is formed asymmetrically with respect to the gate G as
shown in FIG. 7 in an ultrasmall pixel structure having the gate G
32 nm or less in length may have higher photoelectric conversion
gain (mV/e-) and higher resistance change (%/e-) than the simple
recess gate structure illustrated in FIG. 6. For instance, in an
ultrasmall pixel structure, in which the length of the gate G is 22
nm, a single photogenerated charge may generate a conversion
voltage of about 60 mV and a resistance change of about 18%.
[0094] FIG. 8 is a block diagram of a connection between the pixel
array 110 and the readout block 190 illustrated in FIG. 2 according
to some embodiments of the inventive concepts. Referring to FIGS. 2
and 8, the pixel array 110 may include a plurality of sub pixel
groups, i.e., first through fourth sub pixel groups 115 arranged in
a matrix. Although it is illustrated in FIG. 8 that the pixel array
110 includes four sub pixel groups 115 for convenience sake in the
description, the scope of the inventive concepts is not restricted
thereto.
[0095] Each of the sub pixel groups 115 corresponds to a single
pixel. For example, each of the sub pixel groups 115 may correspond
to one of red (R), green (Ga, Gb) and blue (B) pixels arranged in a
Bayer pattern. The sub pixel groups 115 may be controlled by a
control signal output from the row driver 160 to output sub pixel
signals.
[0096] The readout block 190 may include a readout circuit unit 191
and a memory unit 195. The readout circuit unit 191 includes a
plurality of readout circuits 192 connected to the sub pixel groups
115, respectively. Each of the readout circuits 192 receives sub
pixel signals from a sub pixel group 115 connected to each readout
circuit 192 among the sub pixel groups 115 and generates and output
a pixel signal having a plurality of bits to the memory unit 195.
The structure and operations of the readout circuits 192 will be
described in detail with reference to FIGS. 10 through 18
later.
[0097] The memory unit 195 includes a plurality of memories 196
respectively connected to the readout circuits 192. Each of the
memories 196 may receive a pixel signal from a corresponding one of
the readout circuits 192 and store the pixel signal. The memories
196 may sequentially output pixel signals stored therein to the DSP
200 according to a column selection signal (not shown) output from
the column driver 165.
[0098] FIG. 9 is a block diagram of a connection between the pixel
array 110 and the readout block 190 illustrated in FIG. 2 according
to another embodiment of the inventive concepts. Referring to FIGS.
2, 8, and 9, a readout block 190' may also include a switching unit
197 between the pixel array 110 and a readout circuit unit
191'.
[0099] The switching unit 197 may include a first switch SW1 and a
second switch SW2 provided to respectively correspond to columns
for the sub pixel groups 115 arranged in a matrix. For instance,
the first switch SW1 is formed to correspond to the first and
second sub pixel groups 115 in the same column among the first
through fourth sub pixel groups 115. The first and second switches
SW1 and SW2 may be controlled by a switching control signal (not
shown) output from the column driver 165 to simultaneously connect
sub pixel groups 115 in the same row among the first through fourth
sub pixel groups 115 to the readout circuit unit 191'.
[0100] For instance, when the switching control signal is at a high
level, the first and second switches SW1 and SW2 may connect the
first and third sub pixel groups 115 to the readout circuit unit
191'. When the switching control signal is at a low level, the
first and second switches SW1 and SW2 may connect the second and
fourth sub pixel groups 115 to the readout circuit unit 191'.
[0101] Accordingly, the readout circuit unit 191' includes fewer
readout circuits 192' than the readout circuit unit 191 illustrated
in FIG. 8 and a memory unit 195' includes fewer memories 196' than
the memory unit 195 illustrated in FIG. 8. In other words, the
readout block 190' illustrated in FIG. 9 includes only single
readout circuit 192' and single memory 196' per one color of sub
pixel groups, thereby increasing the degree of integrition and
reducing power consumption in the image sensor 100.
[0102] FIG. 10 is a detailed block diagram of an example 192-1 of
the readout circuits 192 and 192' illustrated in FIGS. 8 and 9.
Referring to FIGS. 8 through 10, the first sub pixel group 115
illustrated in FIG. 10 corresponds to the first sub pixel group 115
illustrated in FIGS. 8 and 9. The first sub pixel group 115
includes a plurality of sub pixels 130 in a matrix of "n" rows and
"m" columns.
[0103] The source and the gate of a single transistor SX in each of
the sub pixels 130 may respectively receive one of the source
signals VS1 through VSn and one of the gate signals VG1 though VGn.
The drain of the single transistor SX may be connected to one of
first through m-th column lines COL1 through COLm. First through
m-th transistors X1 through Xm are connected between the power
supply voltage VDD and the respective first through m-th column
lines COL1 through COLm. The first through m-th transistors X1
through Xm function as resistors and contribute to increasing the
degree of integrition of the image sensor 100.
[0104] The readout circuit 192-1 may include a plurality of
capacitors C1 through Cm, a plurality of first reset switches RSW1,
a plurality of comparators 193-1, a plurality of counters 194-1,
and an adder 198-1.
[0105] The capacitors C1 through Cm are connected between the
respective first through m-th column lines COL1 through COLm and
respective first through m-th nodes N1 through Nm. The first
through m-th nodes N1 through Nm correspond to input nodes of the
respective comparators 193-1. The capacitors C1 through Cm transmit
sub pixel signals output from the first through m-th column lines
COL1 through COLm to the first through m-th nodes N1 through Nm. In
other words, each of the capacitors C1 through Cm sets a voltage
level of a corresponding one of the first through m-th nodes N1
through Nm to a voltage level obtained by subtracting a difference
between a voltage level of a corresponding one of the first through
m-th column lines COL1 through COLm and the power supply voltage
VDD from the power supply voltage VDD.
[0106] The first reset switches RSW1 may reset the first through
m-th nodes N1 through Nm, respectively, to the power supply voltage
VDD according to a first reset signal Si output from the column
driver 165. Since the first reset switches RSW1 reset the first
through m-th nodes N1 through Nm to the power supply voltage VDD,
comparison signals COMP1 through COMPm respectively output from the
comparators 193-1 can have a pulse shape.
[0107] Each of the comparators 193-1 may compare a reference
voltage Vref output from the column driver 165 with one of
comparator input voltages INN1 through INNm (i.e., voltages of the
respective first through m-th nodes N1 through Nm), and may
generate one of the comparison signals COMP1 through COMPm
according to the comparison result. The counters 194-1 may
respectively count the comparison signals COMP1 through COMPm in
response to a counter enable signal EN_C output from the column
driver 165 and may respectively generate count results. Each of the
count results is a digital signal having a plurality of bits.
[0108] The adder 198-1 may add the count results of the counters
194-1 and generate a pixel signal. In other words, the pixel signal
is a result of adding all digital values corresponding to sub pixel
signals of the sub pixels 130 included in the first sub pixel group
115.
[0109] Although only the first sub pixel group 115 and the readout
circuit 192-1 connected to the first sub pixel group 115 have been
described, the structures and operations of all sub pixel groups
and readout circuits are the same as one another.
[0110] FIG. 11 is a timing chart for explaining the comparison
signal COMP1 of a comparator 193-1 illustrated in FIG. 10. It is
presumed that the single transistor SX of each of the sub pixels
130 included in the first sub pixel group 115 is a PMOS
transistor.
[0111] Referring to FIGS. 8 through 11, in a reset period
.sub.tRESET, the source signals VS1 through VSn input to the
respective rows of the first sub pixel group 115 have a level of
the power supply voltage VDD and the gate signals VG1 through VGn
input to the respective rows have a level of 0 V. In the reset
period t.sub.RESET, photogenerated charges accumulated in the photo
diode PD of each sub pixel 130 included in the first sub pixel
group 115 are eliminated.
[0112] In an integration period t.sub.INT, the source signals VS1
through VSn input to the respective rows of the first sub pixel
group 115 have the level of 0 V and the gate signals VG1 through
VGn input to the respective rows have the level of the power supply
voltage VDD. In the integration period t.sub.INT, photogenerated
charges corresponding to light incident through the lens 500 are
accumulated in the photo diode PD of each sub pixel 130 included in
the first sub pixel group 115.
[0113] In a readout period t.sub.READ, the source signals VS1
through VSn input to the respective rows of the first sub pixel
group 115 sequentially have the level of the power supply voltage
VDD and the gate signals VG1 through VGn input to the respective
rows sequentially have the level of the read voltage
V.sub.READ.
[0114] When one of the source signals VS1 through VSn input to the
respective rows of the first sub pixel group 115 has the level of
the power supply voltage VDD and one of the gate signals VG1
through VGn input to the respective rows has the level of the read
voltage V.sub.READ, it is defined as a row readout period (one of
t.sub.READ1 through t.sub.READn) for a current row. Accordingly, in
each of the row readout periods t.sub.READ1 through t.sub.READn,
sub pixel signals of the respective sub pixels 130 in a current row
are sequentially output through the column lines COL1 through COLm,
respectively.
[0115] For convenience sake in the description, only the capacitor
C1, the first reset switch RSW1, the comparator 193-1, and the
counter 194-1, which are connected to the first column line COL1
among the column lines COL1 through COLm, will be described; but
the structure and operations of the elements connected to the other
column lines COL2 through COLm are the same as those of the
elements C1, RSW1, 193-1, and 194-1 connected to the first column
line COL1.
[0116] In the first row readout period t.sub.READ1, the first reset
signal S1 may be at a low level for a a desired (or, alternatively
a predetermined) period of time and then transit to a high level.
In the same manner, in each of the second through n-th row readout
periods t.sub.READ2 through t.sub.READn, the first reset signal S1
may be at the low level for the a desired (or, alternatively a
predetermined) period of time and then transit to the high level.
It is assumed that the a desired (or, alternatively a
predetermined) period of time is 1/2 of the first row readout
period t.sub.READ1 for convenience sake in the description, but the
scope of the inventive concepts is not restricted thereto.
[0117] In the first row readout period t.sub.READ1, the first
comparator input voltage INN1 has a level corresponding to a sub
pixel signal input through the capacitor C1. It is assumed that the
initial value of the first comparator input voltage INN1 in the
first row readout period t.sub.READ1 has a lower level than the
reference voltage Vref. When the first reset signal Si transits to
the high level after the a desired (or, alternatively a
predetermined) period of time elapses, the first reset switch RSW1
is short-circuited and the first node N1 has the level of the power
supply voltage VDD. Accordingly, the first comparator input voltage
INN1 is changed from a level lower than the reference voltage Vref
to the level of the power supply voltage VDD in the first row
readout period t.sub.READ1. Therefore, the first comparison signal
COMP1 corresponding to a result of comparing the first comparator
input voltage INN1 with the reference voltage Vref has a pulse
shape changing from a high level to a low level in the first row
readout period t.sub.READ1.
[0118] In the second row readout period t.sub.READ2, the first
comparator input voltage INN1 has a level corresponding to a sub
pixel signal input through the capacitor C1. It is assumed that the
initial value of the first comparator input voltage INN1 in the
second row readout period t.sub.READ2 has a higher level than the
reference voltage Vref. When the first reset signal S1 transits to
the high level after the a desired (or, alternatively a
predetermined) period of time elapses, the first reset switch RSW1
is short-circuited and the first node N1 has the level of the power
supply voltage VDD. Accordingly, the first comparator input voltage
INN1 is changed to the level of the power supply voltage VDD in the
second row readout period t.sub.READ2. Therefore, the first
comparison signal COMP1 corresponding to a result of comparing the
first comparator input voltage INN1 with the reference voltage Vref
remains at the low level in the second row readout period
t.sub.READ2.
[0119] In other words, in the row readout periods t.sub.READ1
through t.sub.READn, the first comparison signal COMP1 has a pulse
shape when a sub pixel signal has a lower level than the reference
voltage Vref and remains at the low level when the sub pixel signal
has a higher level than the reference voltage Vref.
[0120] FIG. 12 is a detailed block diagram of the counter 194-1
illustrated in FIG. 10. Referring to FIGS. 10 through 12, the
counter 194-1 may include an AND gate 20 and a plurality of D
flip-flops 22, 24, 26, and 28. For convenience sake in the
description, the counter 194-1 connected to the first column line
COL1 will be described as an example.
[0121] The AND gate 20 receives the first comparison signal COMP1
and the counter enable signal EN_C and performs an AND operation.
Accordingly, only when the counter enable signal EN_C is at a high
level, is the first comparison signal COMP1 input to the first
flip-flop 22 as a clock signal. In each of the D flip-flops 22, 24,
26, and 28, a data input terminal D and an inverting output
terminal QB are connected with each other, and an output terminal Q
outputs a bit in a count result. In other words, the first through
fourth flip-flops 22, 24, 26, and 28 output first through fourth
bits bit<0> through bit<3>, respectively. The output
terminal Q of each of the first through third flip-flops 22, 24,
and 26 is connected to a clock terminal CLK of a following
flip-flop 24, 26, or 28.
[0122] The D flip-flops 22, 24, 26, and 28 change the level of an
output value at a falling edge of a signal input to the clock
terminal CLK. In other words, the counter 194-1 may be implemented
as an asynchronous counter that receives the first comparison
signal COMP1 as a clock signal.
[0123] The number of flip-flops included in the counter 194-1 is
determined depending on the number of sub pixels 130 in a column of
the first sub pixel group 115 and the number of levels that each
sub pixel 130 can have. For instance, when the number of sub pixels
130 in a column of the first sub pixel group 115, connected with
the counter 194-1, is 8 and the number of levels that each sub
pixel 130 can have is 2, 8*2=16 data values are generated. Since
four binary bits (i.e., 2.sup.4=16) are needed to represent 16 data
values, at least four flip-flops are required.
[0124] FIG. 13 is a timing chart for explaining a count result of
the counter 194-1 illustrated in FIG. 10. Referring to FIGS. 10
through 13, it is assumed that the number of sub pixels 130 in a
column of the first sub pixel group 115 connected with the counter
194-1 is 8 and the number of levels that each of the sub pixels 130
can have is 2. In other words, there are first through eighth row
readout periods t.sub.READ1 through t.sub.READ8.
[0125] The counter enable signal EN_C is at a high level from
before the first row readout period t.sub.READ1 till after the n-th
row readout period t.sub.READn. Since each sub pixel 130 can have
two levels, it is defined that the level of each sub pixel 130 is 1
when the level of a sub pixel signal corresponding to
photogenerated charges accumulated at the photo diode PD of the sub
pixel 130 is lower than the reference voltage Vref and the level of
the sub pixel 130 is 0 when the level of the sub pixel signal is
higher than the reference voltage Vref.
[0126] FIG. 13 shows a case where the sub pixels 130 sequentially
have levels of 1, 1, 0, 1, 0, 0, 1, and 1 in a column direction.
Accordingly, the first comparison signal COMP1 has a pulse shape in
the first, second, fourth, seventh and eighth row readout periods
t.sub.READ1, t.sub.READ2, t.sub.READ4, t.sub.READ7, and
t.sub.READ8.
[0127] The level of the first bit <0> of the first flip-flop
22 is changed at falling edges of the first comparison signal
COMP1. The level of the second bit <1> of the second
flip-flop 24 is changed at falling edges of the first bit
<0>. The level of the third bit <2> of the third
flip-flop 26 is changed at falling edges of the second bit
<1>. The level of the fourth bit <3> of the fourth
flip-flop 28 is changed at falling edges of the third bit
<2>.
[0128] Accordingly, a binary count result output after the eighth
row readout period t.sub.READ8 includes the first bit <0>
(i.e., a place of 1) at a high level, the second bit <1>
(i.e., a place of 2.sup.1) at a low level, the third bit <2>
(i.e., a place of 2.sup.2) at a high level, and the fourth bit
<3> (i.e., a place of 2.sup.3) at a low level. When the count
result is converted into a decimal number, it becomes 5. This is
the same as the number of pulse shapes included in the first
comparison signal COMP1, that is, the number of the sub pixels 130
having a level of 1.
[0129] FIG. 14 is a detailed block diagram of another example 192-2
of the readout circuits 192 and 192' illustrated in FIGS. 8 and 9.
FIG. 15 is a detailed block diagram of a hole injection unit 199
illustrated in FIG. 14. Referring to FIGS. 8 through 10 and FIGS.
14 and 15, the readout circuit 192-2 may further include a
plurality of hole injection units 199 and a plurality of second
reset switches RSW2.
[0130] The hole injection units 199 are connected to the first
through m-th nodes N1 through Nm, respectively. The hole injection
units 199 may sequentially increase the comparator input voltages
INN1 through INNm, respectively, by a hole voltage (.DELTA.V.sub.h
in FIG. 16B).
[0131] FIG. 15 shows a hole injection unit 199 connected to the
first node N1 among the hole injection units 199. The hole
injection unit 199 includes a plurality of hole injection
transistors HX1 through HX3 connected in series between the power
supply voltage VDD and the first node N1.
[0132] The hole injection transistors HX1 through HX3 may be
sequentially turned on in response to third through fifth signals
S3 through S5, respectively. The hole injection transistors HX1
through HX3 may transmit positive holes determined by the timing of
the third through fifth signals S3 through S5 to the first node
N1.
[0133] The second reset switches RSW2 may reset an output node of
each comparator 193-2 to a ground voltage VSS (e.g., 0 V) according
to a second reset signal S2 output from the column driver 165.
Since the second reset switches RSW2 reset the output node of each
comparator 193-2 to the ground voltage VSS, the comparison signals
COMP1 through COMPm output from the respective comparators 193-2
have a pulse shape before the first reset signal S1 transits to the
high level in the row readout periods t.sub.READ1 through
t.sub.READn.
[0134] FIGS. 16A and 16B are timing charts for explaining the
comparison signal COMP1 of the comparator 192-2 illustrated in FIG.
14. Referring to FIGS. 8 through 11 and FIGS. 14 through 16B, the
source signals VS1 through VSn and the gate signals VG1 and VGn
input to the respective rows of the first sub pixel group 115 in
the reset period t.sub.RESET, the integration period t.sub.INT, and
the readout period t.sub.READ illustrated in FIG. 16A are
substantially the same as those illustrated in FIG. 11.
[0135] For convenience sake in the description, only the first and
second row readout periods t.sub.READ1 and t.sub.READ2 are
illustrated. It is assumed that each of the hole injection
transistors HX1 through HX3 is implemented as a PMOS transistor.
Also, it is assumed that the number of levels that each sub pixel
130 can have is 4. In other words, it is assumed that each sub
pixel 130 can have first through fourth levels and that the sub
pixel 130 has the first level when the photo diode PD detects zero
photogenerated charges, the second level when the photo diode PD
detects one photogenerated charge, the third level when the photo
diode PD detects two photogenerated charges, and the fourth level
when the photo diode PD detects three photogenerated charges.
[0136] After a a desired (or, alternatively a predetermined) period
of time since the start of the first row readout period
t.sub.READ1, the third through fifth signals S3 through S5 may
sequentially transit to a low level. While the third through fifth
signals S3 through S5 are at the low level, the hole injection
transistors HX1 through HX3 respectively transmit holes from the
power supply voltage VDD to the first node N1. The number of holes
is determined depending on the length of a period in which the
third through fifth signals S3 through S5 is at the low level and
the length of a period in which the third through fifth signals S3
through S5 overlap one another.
[0137] A change occurring in the first comparator input voltage
INN1 due to the operation of the hole injection transistors HX1
through HX3 is defined as the hole voltage .DELTA.V.sub.h. The
initial value of the first comparator input voltage INN1 is the VDD
level when the sub pixel 130 has the first level, a VDD-.DELTA.V
level when the sub pixel 130 has the second level, a VDD-2.DELTA.V
level when the sub pixel 130 has the third level, and a
VDD-3.DELTA.V level when the sub pixel 130 has the fourth level. At
this time, .DELTA.V is defined as a unit voltage.
[0138] In the first row readout period t.sub.READ1, the initial
value of the first comparator input voltage INN1 is the
VDD-3.DELTA.V level and the reference voltage Vref is higher than
the first comparator input voltage INN1, and therefore, the first
comparison signal COMP1 is at the high level. Thereafter, when the
second reset signal S2 transits the high level, the second reset
switch RSW2 is short-circuited so that the output node of the
comparator 193-2 is reset to the ground voltage VSS (e.g., 0 V).
Therefore, the first comparison signal COMP1 has a pulse shape.
[0139] When a period in which the third through fifth signals S3
through S5 sequentially transit to the low level and remain at the
low level ends, that is, at a time point t2, the first comparator
input voltage INN1 is increased by the hole voltage .DELTA.V.sub.h.
Since the first comparator input voltage INN1 has the
VDD-3.DELTA.V+.DELTA.V.sub.h level and the reference voltage Vref
is higher than the first comparator input voltage INN1, the first
comparison signal COMP1 transits to the high level. Thereafter,
when the second reset signal S2 transits the high level, the second
reset switch RSW2 is short-circuited so that the output node of the
comparator 193-2 is reset to the ground voltage VSS (e.g., 0 V).
Therefore, the first comparison signal COMP1 has a pulse shape.
[0140] When another period in which the third through fifth signals
S3 through S5 sequentially transit to the low level and remain at
the low level ends, that is, at a time point t3, the first
comparator input voltage INN1 is increased by the hole voltage
.DELTA.V.sub.h. Since the first comparator input voltage INN1 has
the VDD-3.DELTA.V+2.DELTA.V.sub.h level and the reference voltage
Vref is still higher than the first comparator input voltage INN1,
the first comparison signal COMP1 transits to the high level.
Thereafter, when the second reset signal S2 transits the high
level, the second reset switch RSW2 is short-circuited so that the
output node of the comparator 193-2 is reset to the ground voltage
VSS (e.g., 0 V). Therefore, the first comparison signal COMP1 has a
pulse shape.
[0141] Thereafter, when the first reset signal 51 transits from the
low level to the high level after the a desired (or, alternatively
a predetermined) period of time, the first comparator input voltage
INN1 has the VDD level. At this time,
VDD-3.DELTA.V+2.DELTA.V.sub.h<Vref needs to be satisfied to
distinguish the third level from the fourth level, and therefore,
the hole voltage .DELTA.V.sub.h needs to meet the condition of
.DELTA.V.sub.h<(3.DELTA.V+Vref-VDD)/2. Accordingly, the sub
pixel 130 has the fourth level in the first row readout period
t.sub.READ1, and therefore, the initial value of the first
comparator input voltage INN1 is the VDD-3.DELTA.V level and the
first comparison signal COMP1 has three pulse shapes.
[0142] In the second row readout period t.sub.READ2, the first
reset signal S1, the second reset signal S2, and the third through
fifth signals S3 through S5 may be applied in the same manner as in
the first row readout period t.sub.READ1. Accordingly, the sub
pixel 130 has the second level in the second row readout period
t.sub.READ2, and therefore, the initial value of the first
comparator input voltage INN1 is the VDD-.DELTA.V level and the
first comparison signal COMP1 has one pulse shape.
[0143] Consequently, when the sub pixel 130 has the first through
fourth levels, the first comparison signal COMP1 has zero through
three pulse shapes.
[0144] FIG. 17 is a detailed block diagram of a counter 194-2
illustrated in FIG. 14. Referring to FIGS. 10 through 12 and FIGS.
14 through 17, the counter 194-2 may include an AND gate 30 and a
plurality of D flip-flops 32, 34, 36, 38, and 40. For convenience
sake in the description, the counter 194-2 connected to the first
column line COL1 will be described as an example. It is also
assumed that the number of sub pixels 130 in a column of the first
sub pixel group 115 connected with the counter 194-2 is 8 and the
number of levels that each sub pixel 130 can have is 4.
[0145] The structures and operations of the AND gate 30 and the D
flip-flops 32, 34, 36, 38, and 40 are substantially the same as
those of the AND gate 20 and the D flip-flops 22, 24, 26, and 28
illustrated in FIG. 12. However, unlike the embodiment illustrated
in FIG. 12, the embodiment illustrated in FIG. 17 additionally
includes the fifth flip-flop 40, so that the counter 194-2 may
generate a count result having first through fifth bits <0>
through <4>.
[0146] When the number of sub pixels 130 in a column of the first
sub pixel group 115 connected with the counter 194-2 is 8 and the
number of levels that each sub pixel 130 can have is 4, 8*4=32 data
values are generated. Since five binary bits (i.e., 2.sup.5=32) are
needed to represent 32 data values, at least five flip-flops are
required.
[0147] FIG. 18 is a timing chart for explaining a count result of
the counter 194-2 illustrated in FIG. 14. Referring to FIGS. 10
through 12 and FIGS. 14 through 18, the counter enable signal EN_C
is at a high level from before the first row readout period
t.sub.READ1 till after the n-th row readout period t.sub.READn.
Since each sub pixel 130 can have four levels, it is defined that
the first through fourth levels of each sub pixel 130 are defined
as 0, 1, 2, and 3, respectively.
[0148] FIG. 18 shows a case where the sub pixels 130 sequentially
have levels of 3, 1, 0, 2, 0, 0, 3, and 1 in a column direction.
Accordingly, the first comparison signal COMP1 has 3, 1, 2, 3 and 1
pulse shapes in the first, second, fourth, seventh and eighth row
readout periods t.sub.READ1, t.sub.READ2, t.sub.READ4, t.sub.READ7,
and t.sub.READ8, respectively.
[0149] The level of the first bit <0> of the first flip-flop
32 is changed at falling edges of the first comparison signal
COMP1. The level of the second bit <1> of the second
flip-flop 34 is changed at falling edges of the first bit
<0>. The level of the third bit <2> of the third
flip-flop 36 is changed at falling edges of the second bit
<1>. The level of the fourth bit <3> of the fourth
flip-flop 38 is changed at falling edges of the third bit
<2>. The level of the fifth bit <4> of the fifth
flip-flop 40 is changed at falling edges of the fourth bit
<3>.
[0150] Accordingly, a binary count result output after the eighth
row readout period t.sub.READ8 includes the first bit <0>
(i.e., a place of 1) at a low level, the second bit <1>
(i.e., a place of 2.sup.1) at a high level, the third bit <2>
(i.e., a place of 2.sup.2) at a low level, the fourth bit <3>
(i.e., a place of 2.sup.3) at a high level, and the fifth bit
<4> (i.e., a place of 2.sup.4) at a low level. When the count
result is converted into a decimal number, it becomes 10, which is
the same as the number of pulse shapes included in the first
comparison signal COMP1, that is, the sum of all levels appearing
when the sub pixels 130 have the levels of 0 through 3.
[0151] As described above, when the image sensor 100 according to
some embodiments of the inventive concepts is used, sub pixel
signals of 1T pixels having a plurality of levels can be precisely
read in a digital pixel signal corresponding to the plurality of
levels.
[0152] FIG. 19 is a flowchart of a method of operating the image
sensor 100 illustrated in FIG. 1 according to some embodiments of
the inventive concepts. FIG. 20A is a detailed flowchart of an
operation of generating a pixel signal in the method illustrated in
FIG. 19.
[0153] Referring to FIGS. 1 through 20, a sub pixel group (e.g.,
the first sub pixel group) 115 including some sub pixels 130
corresponding to a single pixel among a plurality of the sub pixels
130 may generate a plurality of sub pixel signals in operation S10.
The readout block 190 may generate the pixel signal PS having a
plurality of bits based on a result of comparing the sub pixel
signals with the reference voltage Vref in operation S20. Operation
S20 may include operations S21 through S27 shown in FIG. 20A.
[0154] The capacitors C1 through Cm may transmit a plurality of sub
pixel signals from the first through m-th column lines COL1 through
COLm to the input nodes, i.e., the first through m-th nodes N1
through Nm of the respective comparators 193-1 or 193-2 in
operation S21. When the readout block 190 detects sub pixel signals
having at least four levels (e.g., the case illustrated in FIG.
14), the hole injection unit 199 may sequentially increase the
voltage INN1 of the input node N1 of the comparator 193-2 by the
hole voltage .DELTA.V.sub.h in operation S22.
[0155] The first reset switch RSW1 may reset the input node N1 of
the comparator 193-1 or 193-2 to the power supply voltage VDD in
operation S23. The comparator 193-1 or 193-2 may compare the sub
pixel signals with the reference voltage Vref and generate the
comparison signal COMP1 in operation S24.
[0156] When the readout block 190 detects sub pixel signals having
at least four levels (e.g., the case illustrated in FIG. 14), the
second reset switches RSW2 may reset the output nodes of the
respective comparators 193-2 to the ground voltage VSS (e.g., 0 V)
so that the comparison signal COMP1 has a pulse shape before the
first reset signal S1 transits to the high level in the row readout
periods t.sub.READ1 through t.sub.READn in operation S25.
[0157] The counter 194-1 or 194-2 may count the comparison signal
COMP1 and generate a count result in operation S26. The adder 198-1
or 198-2 may add count results generated with respect to the column
lines COL1 through COLm, respectively, to generate the pixel signal
PS in operation S27.
[0158] FIG. 20A explains the operations performed, but as will be
appreciated from the previous portions of this disclosure does not
convey the timing relationship of the operations. Instead, FIG. 20B
illustrates a flow chart of the method of generating a pixel signal
with the timing relationship shown and with reference to FIG.
14.
[0159] As will be understood from FIG. 16B, after a read portion of
a readout time period t.sub.READ#, the first reset signal S1
transition to the high level, switches RSW2 close, and the input
nodes N1-Nm of the comparators COMP1 to COMPm are reset to VDD.
Accordingly, this is the state of the input nodes N1-Nm when the
first reset signal S1 transitions to low level at the beginning of
a readout time period t.sub.READ#.
[0160] As shown, in step S30, the sub pixel signals output from the
first through m-th column lines COL1 to COLm are respectively
transmitted by the capacitors C1 to Cm to the input nodes NN1 to
NNm of comparators COMP1 to COMPm. Each comparator C1 to Cm
determines whether the voltage at the respective input node NN1 to
NNm exceeds a reference voltage Vref in step S35.
[0161] Steps S35-S70 will be described for a single comparator
COMP1, but it will be understood that this description applies to
each of the comparators COMP1 to COMPm. If the determination in
step S35 is negative, the comparator COMP1 generates a high level
output, which increments the counter 194 in step S45. The output of
the comparator COMP1 is then reset to a low level in step S50 for a
period of time by reset switch RSW2 connecting the output of the
comparator COMP1 to ground VSS in response to the second reset
signal S2. The hole injection unit 199 associated with the
comparator COMP1 then injects holes into the input node INN1 in
step S55. This injection increases the voltage at the input node
INN1 as shown in FIG. 16B according to third through fifth signal
S3 through S5. The method returns to S35, and the comparator COMP1
again compares the voltage at input node INN1 to the reference
voltage Vref. Accordingly, the count value produced by the counter
194 is based on a duration that the voltage at the input node INN1,
which corresponds to the respective sub pixel signal, is less than
the reference voltage V.sub.ref. If the determination in step S35
is positive, then no further incrementing of the counter 194 takes
place.
[0162] And, once the first reset signal S1 transitions to the high
level after the read portion of the readout time period
t.sub.READ#, step S60, the input nodes INN1 to INNm are reset to
VDD in step S65. As will be appreciated the read portion of the
readout time period t.sub.READ# is set such that the comparisons
and counter increments complete prior to this reset operation. The
adder 198 counts the counter values received from the counters 198
as described previously, and outputs the accumulated count values
as the pixel signal in step S70.
[0163] FIG. 21 is a block diagram of an electronic system including
an image sensor illustrated in FIG. 1 according to some embodiments
of the inventive concept. Referring to FIGS. 1 and 21, the
electronic system 2100 may be implemented by a data processing
apparatus, such as a mobile phone, a personal digital assistant
(PDA), a portable media player (PMP), an IP TV, or a smart phone
that can use or support the MIPI interface. The electronic system
2100 includes the image sensor 100, an application processor 2110
and a display 2150.
[0164] A camera serial interface (CSI) host 2112 included in the
application processor 2110 performs serial communication with a CSI
device 2141 included in the image sensor 100 through CSI. For
example, an optical de-serializer (DES) may be implemented in the
CSI host 2112, and an optical serializer (SER) may be implemented
in the CSI device 2141.
[0165] A display serial interface (DSI) host 2111 included in the
application processor 2110 performs serial communication with a DSI
device 2151 included in the display 2150 through DSI. For example,
an optical serializer may be implemented in the DSI host 2111, and
an optical de-serializer may be implemented in the DSI device
2151.
[0166] The electronic system 2100 may also include a radio
frequency (RF) chip 2160, which communicates with the application
processor 2110. A physical layer (PHY) 2113 of the electronic
system 2100 and a PHY 2161 of the RF chip 2160 communicate data
with each other according to a MIPI DigRF standard. The electronic
system 2100 may further include at least one element among a GPS
2120, a storage device 2170, a microphone 2180, a DRAM 2185 and a
speaker 2190. The electronic system 2100 may communicate using
Wimax (World Interoperability for Microwave Access) 2191, WLAN
(Wireless LAN) 2193 or UWB (Ultra Wideband) 2195 etc.
[0167] FIG. 22 is a block diagram of an electronic system including
an image sensor illustrated in FIG. 1 according to other
embodiments of the inventive concepts. Referring to FIGS. 1 and 22,
the electronic system 2200 includes the image sensor 100, a
processor 2210, a memory 2220, a display unit 2230 and an interface
2240.
[0168] The processor 2210 may control the operation of the image
sensor 100. For example, the processor 2210 may process pixel
signals output from the image sensor 100 and generate image
data.
[0169] The memory 2220 may store a program for controlling the
image sensor 100 and the image data generated by the processor
2210. The processor 2210 may execute the program stored in the
memory 2220. For example, the memory 2220 may be implemented by a
volatile or non-volatile memory.
[0170] The display unit 2230 may display the image data output from
the processor 2210 or the memory 2220. For example, the display
unit 2230 may be a liquid crystal display (LCD), a light emitting
diode (LED) display, an organic LED (OLED) display, an active
matrix organic light emitting diodes (AMOLED) display or a flexible
display.
[0171] The interface 2240 may be implemented as an interface for
inputting and outputting the image data. For example, the interface
2240 may be implemented by a wireless interface.
[0172] The present general inventive concepts can also be embodied
as computer-readable codes on a computer-readable medium. The
computer-readable recording medium is any data storage device that
can store data as a program, which can be thereafter read by a
computer system. Examples of the computer-readable recording medium
include read-only memory (ROM), random-access memory (RAM),
CD-ROMs, magnetic tapes, floppy disks, and optical data storage
devices.
[0173] The computer-readable recording medium can also be
distributed over network coupled computer systems so that the
computer-readable code is stored and executed in a distributed
fashion. Also, functional programs, codes, and code segments to
accomplish the present general inventive concepts can be easily
construed by programmers.
[0174] As described above, according to some embodiments of the
inventive concepts, an image sensor can precisely read sub pixel
signals of 1T pixels having a plurality of levels in a digital
pixel signal.
[0175] While the inventive concepts have been particularly shown
and described with reference to example embodiments thereof, it
will be understood by those of ordinary skill in the art that
various changes in forms and details may be made therein without
departing from the spirit and scope of the inventive concepts as
defined by the following claims.
* * * * *