U.S. patent application number 13/943721 was filed with the patent office on 2015-01-22 for semiconductor device having metal gate and manufacturing method thereof.
The applicant listed for this patent is UNITED MICROELECTRONICS CORP.. Invention is credited to Yong Tian Hou.
Application Number | 20150021681 13/943721 |
Document ID | / |
Family ID | 52342886 |
Filed Date | 2015-01-22 |
United States Patent
Application |
20150021681 |
Kind Code |
A1 |
Hou; Yong Tian |
January 22, 2015 |
SEMICONDUCTOR DEVICE HAVING METAL GATE AND MANUFACTURING METHOD
THEREOF
Abstract
A manufacturing method of a semiconductor device having metal
gate includes providing a substrate having a first semiconductor
device formed thereon, and the first semiconductor device includes
a first dummy gate. Next, the dummy gate is removed to form a first
gate trench in the first semiconductor device, and the substrate is
exposed in a bottom of the first gate trench. Subsequently, an
epitaxial channel layer is formed in the first gate trench.
Inventors: |
Hou; Yong Tian; (Singapore,
SG) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
UNITED MICROELECTRONICS CORP. |
Hsin-Chu City |
|
TW |
|
|
Family ID: |
52342886 |
Appl. No.: |
13/943721 |
Filed: |
July 16, 2013 |
Current U.S.
Class: |
257/330 ;
438/589 |
Current CPC
Class: |
H01L 29/66636 20130101;
H01L 29/517 20130101; H01L 29/66651 20130101; H01L 29/495 20130101;
H01L 29/4966 20130101; H01L 21/823828 20130101; H01L 21/823807
20130101; H01L 29/7848 20130101; H01L 29/6659 20130101; H01L
29/66545 20130101; H01L 29/42364 20130101; H01L 21/823857 20130101;
H01L 29/20 20130101; H01L 29/16 20130101 |
Class at
Publication: |
257/330 ;
438/589 |
International
Class: |
H01L 29/78 20060101
H01L029/78; H01L 21/28 20060101 H01L021/28 |
Claims
1. A manufacturing method of a semiconductor device having metal
gate comprising: providing a substrate having at least a first
semiconductor device formed thereon, the first semiconductor device
comprising a first dummy gate; removing the first dummy gate to
form a first gate trench in the first semiconductor device, and the
substrate is exposed in a bottom of the first gate trench; and
forming an epitaxial channel layer in the first gate trench.
2. The manufacturing method of the semiconductor device having
metal gate according to claim 1, further comprising an oxide layer
formed between the substrate and the first dummy gate.
3. The manufacturing method of the semiconductor device having
metal gate according to claim 2, further comprising removing the
oxide layer to expose the substrate in the bottom of the first gate
trench after removing the first dummy gate.
4. The manufacturing method of the semiconductor device having
metal gate according to claim 1, further comprising over etching
the substrate exposed in the bottom of the first gate trench.
5. The manufacturing method of the semiconductor device having
metal gate according to claim 1, wherein the first semiconductor
device is a p-typed semiconductor device and the epitaxial channel
layer comprises Si, Ge, or SiGe.
6. The manufacturing method of the semiconductor device having
metal gate according to claim 1, wherein the first semiconductor
device is an n-typed semiconductor device and the epitaxial channel
layer comprises III-V material.
7. The manufacturing method of the semiconductor device having
metal gate according to claim 1, further comprising a second
semiconductor device positioned on the substrate, the second
semiconductor device comprising a second dummy gate and an oxide
layer, and the oxide layer being positioned between the second
dummy gate and the substrate.
8. The manufacturing method of the semiconductor device having
metal gate according to claim 7, further comprising removing the
second dummy gate to form a second gate trench in the second
semiconductor device simultaneously with removing the first dummy
gate.
9. The manufacturing method of the semiconductor device having
metal gate according to claim 8, wherein the oxide layer is exposed
in a bottom of the second gate trench.
10. The manufacturing method of the semiconductor device having
metal gate according to claim 1, further comprising forming a high
dielectric constant (high-k) gate dielectric layer on the epitaxial
channel layer.
11. The manufacturing method of the semiconductor device having
metal gate according to claim 10, further comprising sequentially
forming a work function metal layer and a filling metal layer on
the high-k gate dielectric layer, and the first gate trench being
filled up with the filling metal layer.
12. A semiconductor device having metal gate, comprising: a
substrate; a metal gate positioned on the substrate; a high-k gate
dielectric layer; and an epitaxial channel layer positioned in
between the high-k gate dielectric layer and the substrate, and a
length of the epitaxial channel layer is larger than a length of
the metal gate.
13. The semiconductor device having metal gate according to claim
12, wherein the high-k gate dielectric layer comprises a U
shape.
14. The semiconductor device having metal gate according to claim
12, wherein the metal gate comprises at least a work function metal
layer and a filling metal layer.
15. The semiconductor device having metal gate according to claim
12, wherein the semiconductor device is a p-typed semiconductor
device and the epitaxial channel layer comprises Si, Ge, or
SiGe.
16. The semiconductor device having metal gate according to claim
12, wherein the semiconductor device is an n-typed semiconductor
device and the epitaxial channel layer comprises III-V
material.
17. The semiconductor device having metal gate according to claim
12, further comprising a source/drain formed in the substrate.
18. The semiconductor device having metal gate according to claim
17, wherein the source/drain comprises a doped epitaxial layer,
respectively.
19. The semiconductor device having metal gate according to claim
12, wherein a bottom of the epitaxial channel layer and the
substrate are coplanar.
20. The semiconductor device having metal gate according to claim
12, wherein a bottom of the epitaxial channel layer and the
substrate are non-coplanar.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The invention relates to a semiconductor device having metal
gate and manufacturing method thereof, and more particularly, to a
semiconductor device having metal gate and manufacturing method
integrated with epitaxy technique.
[0003] 2. Description of the Prior Art
[0004] With semiconductor processes entering the era of the deep
submicron meter, it has been more and more important to increase
the metal-oxide semiconductor (MOS) drive current. To improve
device performance, epitaxy technique is developed to enhance
carrier mobility of the channel region.
[0005] On the other hands, with the trend toward scaling down the
size of the semiconductor device, work function metals are provided
to replace the conventional polysilicon gate to be the control
electrode that competent to the high dielectric constant (herein
after abbreviated as high-K) gate dielectric layer. The metal gate
methods in the-state-of-art are categorized into the gate first
process and the gate last process. Among the two main processes,
the gate last process is able to avoid processes of high thermal
budget and to provide wider material choices for the high-K gate
dielectric layer and the metal gate, and thus the gate last process
gradually replaces the gate first process.
[0006] It is observed that processes with high thermal budget
impacts not only the metal gate process, but also the quality of
the epitaxial layers. In the view of the above, there exists a need
for integrating the epitaxy technique and metal gate process
without encountering the high thermal budget issue.
SUMMARY OF THE INVENTION
[0007] According to an aspect of the present invention, a
manufacturing method of a semiconductor device having metal gate is
provided. According to the manufacturing method, a substrate having
at least a first semiconductor device formed thereon is provided,
and the first semiconductor device includes a first dummy gate.
Next, the first dummy gate is removing to form a first gate trench
in the first semiconductor device, and the substrate is exposed in
a bottom of the first gate trench. After forming the first gate
trench, an epitaxial channel layer is formed in the first gate
trench.
[0008] According to an aspect of the present invention, a
semiconductor device having metal gate is provided. The
semiconductor device includes a substrate, a metal gate positioned
on the substrate, a high-k gate dielectric layer, and an epitaxial
channel layer positioned in between the high-k gate dielectric
layer and the substrate. A length of the epitaxial channel layer is
equal to a length of the metal gate.
[0009] According to the semiconductor device having metal gate and
the manufacturing method thereof provided by the present invention,
the metal-last process is integrated with the epitaxy technique.
Accordingly, the epitaxial channel layer is formed in the gate
trench after performing steps having high thermal budget such as
source/drain formation, and silicide process. And the metal gate is
subsequently formed in the gate trench. Since the epitaxial channel
layer and the metal gate are all formed after process requiring
high temperature, qualities of the metal gate and the epitaxial
channel layer are no longer impacted by those processes and thus
performance of the transistor device is improved.
[0010] These and other objectives of the present invention will no
doubt become obvious to those of ordinary skill in the art after
reading the following detailed description of the preferred
embodiment that is illustrated in the various figures and
drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0011] FIGS. 1-6 are drawings illustrating a manufacturing method
for a semiconductor device having metal gate provided by a first
preferred embodiment of the present invention, wherein
[0012] FIG. 2 is a schematic drawing in a step subsequent to FIG.
1,
[0013] FIG. 3 is a schematic drawing in a step subsequent to FIG.
2,
[0014] FIG. 4 is a schematic drawing in a step subsequent to FIG.
3,
[0015] FIG. 5 is a schematic drawing in a step subsequent to FIG.
4, and
[0016] FIG. 6 is a schematic drawing in a step subsequent to FIG.
5.
[0017] FIGS. 7-10 are drawings illustrating a manufacturing method
for a semiconductor device having metal gate provided by a second
preferred embodiment of the present invention, wherein
[0018] FIG. 8 is a schematic drawing in a step subsequent to FIG.
7,
[0019] FIG. 9 is a schematic drawing in a step subsequent to FIG.
8, and
[0020] FIG. 10 is a schematic drawing in a step subsequent to FIG.
9.
DETAILED DESCRIPTION
[0021] Please refer to FIGS. 1-6, which are drawings illustrating a
manufacturing method for a semiconductor device having metal gate
provided by a first preferred embodiment of the present invention.
As shown in FIG. 1, the preferred embodiment first provides a
substrate 100 such as silicon substrate, silicon-containing
substrate, or silicon-on-insulator (SOI) substrate. The substrate
100 includes a core region 102 and a peripheral region 104 defined
thereon. An isolation structure 106, such as a shallow trench
isolation (STI) is formed in the substrate 100 between the core
region 102 and the peripheral region 104 for rendering electrical
isolation. A first semiconductor device 110 is formed in the core
region 102 and a second semiconductor device 112 is formed in the
peripheral region 104. In the preferred embodiment, the first
semiconductor device 110 and the second semiconductor device 112
include the same conductivity type. However, those skilled in the
art would easily realize that the first semiconductor device 110
and the second semiconductor device 112 can include conductivity
types that are complementary to each other. Additionally,
semiconductor devices having conductivity types complementary to
the first semiconductor device 110 can be formed in the core region
102, but not detailed.
[0022] Please still refer to FIG. 1. The first semiconductor device
110 and the second semiconductor device 112 respectively includes
an oxide layer 114, a dummy gate 116 such as a polysilicon layer
formed on the oxide layer 114, and a patterned hard mask (not
shown) formed on the dummy gate 116 for defining placement of the
dummy gate 116. As shown in FIG. 1, the oxide layer 114 is formed
between the dummy gate 116 and the substrate 100 for serving as an
interfacial layer (IL). The intentionally grown interfacial layer
is used in order to arrange a good interface between the surface of
the substrate 100 and the gate insulator, particularly the high-k
gate insulator, formed later. The oxide layer 114 is formed on the
substrate 100 by high-temperature process such as in-situ silicon
growth (ISSG), rapid thermal oxidation (RTO), etc. The first
semiconductor device 110 and the second semiconductor device 112
further respectively include first lightly doped drains
(hereinafter abbreviate as LDDs) 120 and second LDDs 122, a spacer
124, a first source/drain 130 and a second source/drain 132.
Salicides (not shown) are respectively formed on the first
source/drain 130 and the second source/drain 132. After forming the
first semiconductor device 110 and the second semiconductor device
112, a contact etch stop layer (hereinafter abbreviated as CESL)
140 and an inter-layer dielectric (hereinafter abbreviated as ILD)
layer 142 are sequentially formed. Since the steps and material
choices for the abovementioned elements are well-known to those
skilled in the art, those details are omitted herein in the
interest of brevity.
[0023] Furthermore, selective strain scheme (SSS) can be used in
the preferred embodiment. For example, a selective epitaxial growth
(hereinafter abbreviated as SEG) method can be used to form at
least the first source/drain 130. Accordingly, the first
source/drain 130 of the first semiconductor device 100 in the core
region 102 respectively includes a doped epitaxial layer. Because
the lattice constant of the epitaxial layer is different from that
of the silicon substrate, a strained stress is generated and a
surface of the first source/drain 130 having the doped epitaxial
layer may be higher than a surface of the substrate 100, as shown
in FIG. 1.
[0024] Please refer to FIGS. 1 and 2. After forming the CESL 140
and the ILD layer 142, a planarization process is performed to
remove a portion of the CESL 140 and a portion of the ILD layer 142
to expose the patterned hard masks or the dummy gates 116 of the
first semiconductor device 110 and the second semiconductor device
112. Subsequently, a suitable etching process is performed to
remove the patterned hard masks and the dummy gates 116 of the
first semiconductor device 110 and the second semiconductor device
112. Consequently, a first gate trench 150 is formed in the first
semiconductor device 110 and a second gate trench 152 is
simultaneously formed in the second semiconductor device 112. As
shown in FIG. 2, the oxide layers 114 are exposed in bottoms of
both the first gate trench 150 and the second gate trench 152.
[0025] Please refer to FIG. 3. More important, an etching process
is performed to remove the oxide layer 114 from the first gate
trench 150 with a suitable etchant after forming the first gate
trench 150 and the second gate trench 152. It should be understood
that a protection layer (not shown) can be formed in the second
semiconductor device 112 in order to protect the oxide layer 114
exposed in the bottom of the second gate trench 152. Consequently,
the substrate 100 is exposed in the bottom of the first gate trench
150 while the oxide layer 114 is exposed in the bottom of the
second gate trench 152 according to the preferred embodiment.
However, those skilled in the art would easily realize that the
oxide layers 114 can be simultaneously removed from both of the
first gate trench 150 and the second gate trench 152 according to a
modification to the preferred embodiment, and thus the substrate
100 is exposed in the bottoms of both the first gate trench 150 and
the second gate trench 152.
[0026] Please refer to FIG. 4. After removing the oxide layer 114
from the first gate trench 150 to expose the substrate 100, a
cleaning step is performed to remove native oxides or other
impurities from the first gate trench 150. Next, an epitaxy
process, such as a SEG method is performed to form an epitaxial
channel layer 160 in the first gate trench 150. A thickness of the
epitaxial channel layer 160 is between 2 nanometer (hereinafter
abbreviated as nm) and 50 nm. Because the epitaxial materials only
grow along the silicon surface, the epitaxial channel layer 160 is
spontaneously formed on the exposed substrate 100 and confined
within the first gate trench 150. Additionally, a bottom of the
epitaxial channel layer 160 is coplanar with the surface of the
substrate 100. It is noteworthy that the epitaxial channel layer
160 includes different materials depending on the conductivity type
required in the preferred embodiment. For example, when the first
semiconductor device 110 is a p-typed semiconductor device, the
epitaxial channel layer 160 includes silicon (Si), germanium (Ge),
or silicon germanium (SiGe). When the first semiconductor device
110 is an n-typed semiconductor device, the epitaxial channel layer
160 includes III-V material such as gallium arsenide (GaAs), indium
phosphide (InP), indium arsenide (InAs), or indium antimonide
(InSb). Additionally, the epitaxial channel layer 160 can include
doped epitaxial material or undoped epitaxial material. When the
epitaxial channel layer 160 includes the doped epitaxial material,
it further includes dopants having conductivity type complementary
to the first source/drain 130.
[0027] Please refer to FIG. 5. After forming the epitaxial channel
layer 160, a high-k gate dielectric layer 170 is formed on the
substrate 100. It is therefore conceivable that the preferred
embodiment adopts the high-k last process. The high-k gate
dielectric layer 170 can include metal oxides such as rare earth
metal oxides. The high-k gate dielectric layer 170 can include
material selected from the group consisting of hafnium oxide
(HfO.sub.2), hafnium silicon oxide (HfSiO.sub.4), hafnium silicon
oxynitride (HfSiON), aluminum oxide (Al.sub.2O.sub.3), lanthanum
oxide (La.sub.2O.sub.3), tantalum oxide (Ta.sub.2O.sub.5), yttrium
oxide (Y.sub.2O.sub.3), zirconium oxide (ZrO.sub.2), strontium
titanate oxide (SrTiO.sub.3), zirconium silicon oxide
(ZrSiO.sub.4), hafnium zirconium oxide (HfZrO.sub.4), strontium
bismuth tantalate, (SrBi.sub.2 Ta.sub.2O.sub.9, SBT), lead
zirconate titanate (PbZr.sub.xTi.sub.1-xO.sub.3, PZT), and barium
strontium titanate (Ba.sub.xSr.sub.1-xTiO.sub.3, BST).
[0028] Please still refer to FIG. 5. After forming the high-k gate
dielectric layer 170, a work function metal layer 172 and a filling
metal layer 174 are sequentially formed on the substrate 100. As
shown in FIG. 5, the first gate trench 150 and the second gate
trench 152 are filled up with the filling metal layer 174. The work
function metal layer 172 includes different metal materials
depending on the conductivity type required in accordance with the
preferred embodiment. For example, when the first semiconductor
device 110 is a p-typed semiconductor device, the work function
metal layer 172 includes p-metal and possesses a work function
between 4.8 and 5.2. When the first semiconductor device 110 is an
n-typed semiconductor device, the work function metal layer 172
includes an n-metal and possesses a work function between 3.9 and
4.3. Furthermore, it is well-known to those skilled in the art that
other layers such as the barrier layer, the etch stop layer, or,
even the strained layer can be formed in the gate trenches 150/152
before forming the work function metal layer 172.
[0029] Please refer to FIG. 6. Next, a planarization process, such
as a chemical mechanical polishing (CMP) process is performed to
remove the superfluous filling metal layer 174, work function metal
layer 172, and the high-k gate dielectric layer 170. Consequently,
a first metal gate 180 is formed in the first semiconductor device
110 and a second metal gate 182 is formed in the second
semiconductor device 112. In addition, the ILD layer 140 and the
CESL 142 can be selectively removed and sequentially reformed on
the substrate 100 for improving performance of the semiconductor
devices 110/112 in the preferred embodiment. As shown in FIG. 6,
since the preferred embodiment adopts the high-k last process, the
high-k gate dielectric layer 170 includes a U shape. More
important, the epitaxial channel layer 160 is formed between the
high-k gate dielectric layer 170 and the substrate 100, and
confined within the spacer 124. A length of the epitaxial channel
layer 160 is equal to a length of the firs metal gate 180.
[0030] According to the semiconductor having metal gate and
manufacturing method thereof provided by the first preferred
embodiment, the gate-last process and epitaxy technique are
integrated successfully. More important, the epitaxial channel
layer 160 is formed in the first gate trench 150 after the
processes having high thermal budget, such as the oxide layer 114
formation, the source/drain 130 formation, and the silicide
process. And the metal gates 180/182 are subsequently formed. Since
the epitaxial channel layer 160 and the metal gates 180/182 are all
formed after the high temperature processes, qualities of the
epitaxial channel layer 160 and the metal gates 180/182 are no
longer impacted and thus the performance of the first semiconductor
device 110 is improved.
[0031] Please refer to FIGS. 7-10, which are drawings illustrating
a manufacturing method for a semiconductor device having metal gate
provided by a second preferred embodiment of the present invention.
It should be noted that elements the same in both of the first and
second preferred embodiments can include the same material and
conductivity type, and therefore those details are omitted in the
interest of brevity. As shown in FIG. 7, the preferred embodiment
first provides a substrate 200. The substrate 200 includes a core
region 202 and a peripheral region 204 defined thereon. An
isolation structure 206, such as a shallow trench isolation is
formed in the substrate 200 between the core region 202 and the
peripheral region 204 for rendering electrical isolation. A first
semiconductor device 210 is formed in the core region 202 and a
second semiconductor device 212 is formed in the peripheral region
204. As mentioned above, the first semiconductor device 210 and the
second semiconductor device 212 include the same conductivity type.
However, those skilled in the art would easily realize that the
first semiconductor device 210 and the second semiconductor device
212 can include conductivity types that are complementary to each
other. Additionally, semiconductor devices having conductivity
types complementary to the first semiconductor device 210 can be
formed in the core region 202, but not detailed.
[0032] Please still refer to FIG. 7. The first semiconductor device
210 and the second semiconductor device 212 respectively includes
an oxide layer 214, a dummy gate (not shown), and a patterned hard
mask. As mentioned above, the oxide layer 214 is formed between the
dummy gate and the substrate 200 for serving as an interfacial
layer. The intentionally grown interfacial layer is used in order
to arrange a good interface between the surface of the substrate
200 and the gate insulator, particularly the high-k gate insulator,
formed later. As mentioned above, the oxide layer 214 is formed on
the substrate 200 by high-temperature process such as ISSG, RTO,
etc. The first semiconductor device 210 and the second
semiconductor device 212 respectively include first LDDs 220 and
second LDDs 222, a spacer 224, a first source/drain 230 and a
second source/drain 232. Salicides (not shown) are respectively
formed on the first source/drain 230 and the second source/drain
232. After forming the first semiconductor device 210 and the
second semiconductor device 212, a CESL 240 and an ILD layer 242
are sequentially formed. Since the steps and material choices for
the abovementioned elements are well-known to those skilled in the
art, those details are omitted herein in the interest of
brevity.
[0033] Furthermore, selective strain scheme (SSS) can be used in
the preferred embodiment. For example, a SEG method can be used to
form at least the first source/drain 230. Accordingly, the first
source/drain 230 of the first semiconductor device 200 in the core
region 202 respectively includes a doped epitaxial layer. Because
the lattice constant of the epitaxial layer is different from that
of the silicon substrate, a strain stress is generated and a
surface of the first source/drain 230 having the doped epitaxial
layer may be higher than a surface of the substrate 200, as shown
in FIG. 7.
[0034] Please refer to FIG. 7. After forming the CESL 240 and the
ILD layer 242, a planarization process is performed to remove a
portion of the CESL 240 and a portion of the ILD layer 242 to
expose the patterned hard masks or the dummy gates of the first
semiconductor device 210 and the second semiconductor device 212.
Subsequently, a suitable etching process is performed to remove the
patterned hard masks and the dummy gates of the first semiconductor
device 210 and the second semiconductor device 212. Consequently, a
first gate trench 250 is formed in the first semiconductor device
210 and a second gate trench 252 is simultaneously formed in the
second semiconductor device 212. As shown in FIG. 7, the oxide
layers 214 are exposed in bottoms of both the first gate trench 250
and the second gate trench 252.
[0035] Please refer to FIG. 8. Next, an etching process is
performed to remove the oxide layer 214 from the first gate trench
250 with a suitable etchant. Consequently, the substrate 200 is
exposed in the bottom of the first gate trench 250 after removing
the oxide layer 240. More important, the etching process is
performed to over etch the substrate 200 exposed in first gate
trench 250, and thus a recess 254 is formed in the bottom of the
first gate trench 250. It should be understood that a protection
layer (not shown) can be formed in the second semiconductor device
212 in order to protect the oxide layer 214 exposed in the bottom
of the second gate trench 252. Consequently, the substrate 200 is
exposed in the bottom of the first gate trench 250, particularly
exposed in a bottom of the recess 254, while the oxide layer 214 is
exposed in the bottom of the second gate trench 252 according to
the preferred embodiment. However, those skilled in the art would
easily realize that the oxide layers 214 in both of the first gate
trench 250 and the second gate trench 252 can be simultaneously
removed according to a modification to the preferred embodiment,
and thus the substrate 200 is exposed in the bottoms of both the
first gate trench 250 and the second gate trench 252 and is over
etched to form recesses respectively in the bottom of both the
first gate trench 250 and the second gate trench 252.
[0036] Please refer to FIG. 9. After removing the oxide layer 214
and forming the recess 254, a cleaning step is performed to remove
native oxides or other impurities from the recess 254. Next, an
epitaxy process, such as a SEG method is performed to form an
epitaxial channel layer 260 in the first gate trench 250. A
thickness of the epitaxial channel layer 260 is between 2 nm and 50
nm. Because the epitaxial materials only grow along the silicon
surface, the epitaxial channel layer 260 is spontaneously formed on
the exposed substrate 200 and confined within the first gate trench
250. Additionally, a bottom of the epitaxial channel layer 260 is
non-coplanar with the surface of the substrate 200. As shown in
FIG. 9, the epitaxial channel layer 260 is confined within the
spacer 224, and a bottom of the epitaxial channel layer 260 is
lower than the surface of the substrate 200. As mentioned above,
the epitaxial channel layer 260 includes different materials
depending on the conductivity type required in the preferred
embodiment. Since the materials have been disclosed in the first
preferred embodiment, those details are omitted for simplicity.
Additionally, the epitaxial channel layer 260 can include doped
epitaxial material or undoped epitaxial material. When the
epitaxial channel layer 260 includes the doped epitaxial material,
it further includes dopants having conductivity type complementary
to the first source/drain 230.
[0037] Please refer to FIG. 10. After forming the epitaxial channel
layer 260, a high-k gate dielectric layer 270 is formed on the
substrate 200. The materials used to form the high-k gate
dielectric layer 270 are the same with those detailed in the first
preferred embodiment, therefore those materials are omitted for
simplicity. It is therefore conceivable that the preferred
embodiment adopts the high-k last process. After forming the high-k
gate dielectric layer 270, a work function metal layer 272 and a
filling metal layer 274 are sequentially formed on the substrate
200. As shown in FIG. 10, the first gate trench 250 and the second
gate trench 252 are filled up with the filling metal layer 274. In
the preferred embodiment, the work function metal layer 272
includes different metal materials depending on the conductivity
type required in accordance with the preferred embodiment. For
example, when the first semiconductor device 210 is a p-typed
semiconductor device, the work function metal layer 272 includes
p-metal and possesses a work function between 4.8 and 5.2. When the
first semiconductor device 210 is an n-typed semiconductor device,
the work function metal layer 272 includes an n-metal and possesses
a work function between 3.9 and 4.3. Furthermore, it is well-known
to those skilled in the art that other layers such as the barrier
layer, the etch stop layer, or, even the strained layer can be
formed in the gate trenches 250/252 before forming the work
function metal layer 272.
[0038] Please still refer to FIG. 10. Next, a planarization
process, such as a CMP process is performed to remove the
superfluous filling metal layer 274, work function metal layer 272,
and the high-k gate dielectric layer 270. Consequently, a first
metal gate 280 is formed in the first semiconductor device 210 and
a second metal gate 282 is formed in the second semiconductor
device 212. In addition, the ILD layer 240 and the CESL 242 can be
selectively removed and sequentially reformed on the substrate 200
for improving performance of the semiconductor devices 210/212 in
the preferred embodiment. As shown in FIG. 10, since the preferred
embodiment adopts the high-k last process, the high-k gate
dielectric layer 270 includes a U shape. More important, the
epitaxial channel layer 260 is formed between the high-k gate
dielectric layer 270 and the substrate 200, and confined within the
spacer 224. A length of the epitaxial channel layer 260 is equal to
a length of the firs metal gate 280.
[0039] According to the semiconductor having metal gate and
manufacturing method thereof provided by the second preferred
embodiment, the gate-last process and epitaxy technique are
integrated successfully. More important, the epitaxial channel
layer 260 is formed in the first gate trench 250 after the
processes having high thermal budget, such as the oxide layer 214
formation, the source/drain 230 formation, and the silicide
process. And the metal gates 280/282 are subsequently formed. Since
the epitaxial channel layer 260 and the metal gates 280/282 are all
formed after the high temperature processes, qualities of the
epitaxial channel layer 260 and the metal gates 280/282 are no
longer impacted and thus the performance of the first semiconductor
device 210 is improved. Furthermore, since the bottom of the
epitaxial channel layer 260 is lower than the surface of the
substrate 200, the channel region obtains more effective strained
stress from the first source/drain 230 having the doped epitaxial
material, and thus the performance of the first semiconductor
device 210 is further improved.
[0040] According to the semiconductor device having metal gate and
the manufacturing method thereof provided by the present invention,
the metal-last process is integrated with the epitaxy technique.
Accordingly, the epitaxial channel layer with the bottom coplanar
or non-coplanar with the substrate is formed in the gate trench
after steps of high thermal budget such as source/drain formation,
and silicide process. And the metal gate is subsequently formed in
the gate trench. Since the epitaxial channel layer and the metal
gate are all formed after the processes having high thermal budget,
qualities of the metal gate and the epitaxial channel layer are no
longer impacted by those processes. For example, high resistance
and current leakage due to the high thermal issue are all avoided
and thus performance of the transistor device is improved.
Additionally, the semiconductor device and the manufacturing method
thereof provided by the present invention can be integrated with
multi-gate technique, such as the fin field transistor (FinFET)
technique.
[0041] Those skilled in the art will readily observe that numerous
modifications and alterations of the device and method may be made
while retaining the teachings of the invention. Accordingly, the
above disclosure should be construed as limited only by the metes
and bounds of the appended claims.
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