U.S. patent application number 14/511430 was filed with the patent office on 2015-01-22 for nonvolatile semiconductor memory device and method of manufacturing the same.
This patent application is currently assigned to KABUSHIKI KAISHA TOSHIBA. The applicant listed for this patent is KABUSHIKI KAISHA TOSHIBA. Invention is credited to Ryuji OHBA.
Application Number | 20150021678 14/511430 |
Document ID | / |
Family ID | 49210977 |
Filed Date | 2015-01-22 |
United States Patent
Application |
20150021678 |
Kind Code |
A1 |
OHBA; Ryuji |
January 22, 2015 |
NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING
THE SAME
Abstract
According to one embodiment, a nonvolatile semiconductor memory
device includes a first memory cell on the first fin-type active
area, and a second memory cell on the second fin-type active area.
Each of widths of charge storage layers of the first and second
memory cells becomes narrower upward from below. Each of
inter-electrode insulating layers of the first and second memory
cells has a contact portion through which both are in contact with
each other.
Inventors: |
OHBA; Ryuji; (Kawasaki-shi,
JP) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
KABUSHIKI KAISHA TOSHIBA |
Minato-ku |
|
JP |
|
|
Assignee: |
KABUSHIKI KAISHA TOSHIBA
Minato-ku
JP
|
Family ID: |
49210977 |
Appl. No.: |
14/511430 |
Filed: |
October 10, 2014 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
13603710 |
Sep 5, 2012 |
8890231 |
|
|
14511430 |
|
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Current U.S.
Class: |
257/316 |
Current CPC
Class: |
H01L 27/11519 20130101;
H01L 27/0207 20130101; H01L 29/42328 20130101; H01L 27/11521
20130101; H01L 29/40114 20190801; H01L 29/785 20130101; H01L
29/66833 20130101; H01L 27/11517 20130101; H01L 29/788
20130101 |
Class at
Publication: |
257/316 |
International
Class: |
H01L 27/115 20060101
H01L027/115; H01L 29/423 20060101 H01L029/423; H01L 29/78 20060101
H01L029/78; H01L 29/788 20060101 H01L029/788 |
Foreign Application Data
Date |
Code |
Application Number |
Mar 23, 2012 |
JP |
2012-068335 |
Mar 23, 2012 |
JP |
2012-068401 |
Claims
1. (canceled)
2. A nonvolatile semiconductor memory device comprising: a
semiconductor substrate; first and second active areas adjacent to
each other in a first direction on the semiconductor substrate; a
first memory cell on the first active area, the first memory cell
including a first gate insulating layer on the first active area, a
first charge storage layer on the first gate insulating layer and
in which a first width thereof in the first direction becomes
narrower upward from below, a first insulating layer covering an
upper portion of the first charge storage layer, and a control gate
electrode on the first insulating layer and extending in the first
direction, the first insulating layer having a first lowest edge
and a first side edge; and a second memory cell on the second
active area, the second memory cell including a second gate
insulating layer on the second active area, a second charge storage
layer on the second gate insulating layer and in which a second
width thereof in the first direction becomes narrower upward from
below, a second insulating layer covering an upper portion of the
second charge storage layer, and the control gate electrode on the
second insulating layer, the second insulating layer having a
second lowest edge and a second side edge, the second insulating
layer being isolated the first insulating layer, wherein a first
interval between the first and second side edges in the first
direction is smaller than a second interval between first and
second lowest edges in the first direction.
3. The nonvolatile semiconductor memory device according to claim
2, wherein the first insulating layer has a first highest edge, the
second insulating layer has a second highest edge, and the first
interval is smaller than a third interval between the first and
second highest edges in the first direction.
4. The nonvolatile semiconductor memory device according to claim
2, wherein the first insulating layer has a first highest edge, the
second insulating layer has a second highest edge, and a bottom
surface of the control gate electrode between the first and second
active areas is above the first and second side edges and below the
first and second highest edges.
5. The nonvolatile semiconductor memory device according to claim
2, wherein a bottom surface of the control gate electrode between
the first and second active areas is positioned around the first
and second side edges.
6. The nonvolatile semiconductor memory device according to claim
2, wherein an air gap is provided between lower portions of the
first and second charge storage layers, and is provided below the
control gate electrode.
7. The nonvolatile semiconductor memory device according to claim
2, wherein the first insulating layer has a first highest edge, the
second insulating layer has a second highest edge, and a bottom
surface of the control gate electrode between the first and second
active areas is above top edges of the first and second charge
storage layers and below the first and second highest edges.
8. The nonvolatile semiconductor memory device according to claim
2, wherein an opening is provided between the first and second side
edges.
9. The nonvolatile semiconductor memory device according to claim
2, wherein each of first and second charge storage layers has a
cross-sectional shape in the first direction having a triangle
shape or a trapezoid shape.
10. The nonvolatile semiconductor memory device according to claim
2, wherein each of the first and second charge storage layers
includes a floating gate electrode and a charge trap layer on the
floating gate electrode.
11. The nonvolatile semiconductor memory device according to claim
10, wherein each of the first and second charge storage layers
includes an intermediate insulating layer between the floating gate
electrode and the charge trap layer.
12. A nonvolatile semiconductor memory device comprising: a
semiconductor substrate; first and second active areas adjacent to
each other in a first direction on the semiconductor substrate; a
first memory cell on the first active area, the first memory cell
including a first gate insulating layer on the first active area, a
first charge storage layer on the first gate insulating layer and
in which a first width thereof in the first direction becomes
narrower upward from below, a first insulating layer covering an
upper portion of the first charge storage layer, and a control gate
electrode on the first insulating layer and extending in the first
direction; and a second memory cell on the second active area, the
second memory cell including a second gate insulating layer on the
second active area, a second charge storage layer on the second
gate insulating layer and in which a second width thereof in the
first direction becomes narrower upward from below, a second
insulating layer covering an upper portion of the second charge
storage layer, and the control gate electrode on the second
insulating layer, wherein a region between the upper portions of
the first and second charge storage layers is filled with the first
and second insulating layers.
13. The nonvolatile semiconductor memory device according to claim
12, wherein the first insulating film has a first side surface, the
second insulating film has a second side surface, and the first and
second side surfaces are in contact with each other in a plane
above bottom surfaces of the first and second charge storage
layers.
14. The nonvolatile semiconductor memory device according to claim
12, wherein the first and second insulating layers are separate
layers.
15. The nonvolatile semiconductor memory device according to claim
12, wherein an air gap is provided between lower portions of the
first and second charge storage layers, and the air gap is isolated
from the control gate electrode by the first and second insulating
layers.
16. The nonvolatile semiconductor memory device according to claim
12, wherein bottom surfaces of the first and second insulating
films are positioned above bottom surfaces of the first and second
charge storage layers.
17. The nonvolatile semiconductor memory device according to claim
12, wherein a bottom surface of the control gate electrode between
the first and second active areas is above a contact portion of the
first and second insulating layers.
18. The nonvolatile semiconductor memory device according to claim
12, wherein a bottom surface of the control gate electrode between
the first and second active areas is above top edges of the first
and second charge storage layers and below top edges of the first
and second insulating layers.
19. The nonvolatile semiconductor memory device according to claim
12, wherein each of first and second charge storage layers has a
cross-sectional shape in the first direction having a triangle
shape or a trapezoid shape.
20. The nonvolatile semiconductor memory device according to claim
12, wherein each of the first and second charge storage layers
includes a floating gate electrode and a charge trap layer on the
floating gate electrode.
21. The nonvolatile semiconductor memory device according to claim
12, wherein each of the first and second charge storage layers
includes an intermediate insulating layer between the floating gate
electrode and the charge trap layer.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is based upon and claims the benefit of
priority from Japanese Patent Applications No. 2012-068335, filed
Mar. 23, 2012; and No. 2012-068401, filed Mar. 23, 2012, the entire
contents of all of which are incorporated herein by reference.
FIELD
[0002] Embodiments described herein relate generally to a
nonvolatile semiconductor memory device and a method of
manufacturing the same.
BACKGROUND
[0003] The flat cell structure, which is advantageous for finer
structures, in a nonvolatile semiconductor storage device such as a
NAND flash memory has recently gained attention again.
[0004] The flat cell structure has the advantage that half the
pitch (half pitch) of bit lines extending in a column direction is
not restricted by an inter-electrode insulating layer or a control
gate electrode because the inter-electrode insulating layer or the
control gate electrode does not get in between floating gate
electrodes aligned in a row direction in which a control gate
electrode (word line) extends.
[0005] However, an opposing area of the floating gate electrode and
the control gate electrode is small in the flat cell structure and
it is difficult to achieve a sufficiently large coupling ratio.
Moreover, if the half pitch is narrowed by the flat cell structure,
the so-called inter-cell interference in which memory cells aligned
in the row direction interfere with each other in a read or write
operation may be caused.
[0006] In addition, it is becoming more difficult to achieve a
sufficiently large coupling ratio in the flat cell structure with
increasingly finer structures of memory cells.
BRIEF DESCRIPTION OF THE DRAWINGS
[0007] FIG. 1 is a plan view showing an array structure according
to a first embodiment;
[0008] FIG. 2 is a sectional view along a II-II line in FIG. 1;
[0009] FIG. 3 is a sectional view along a III-III line in FIG.
1;
[0010] FIGS. 4 to 8 are sectional views showing a manufacturing
method;
[0011] FIG. 9 is a sectional view showing a first modification;
[0012] FIG. 10 is diagram showing a relationship between the
thickness of an inter-electrode insulating layer and a height of a
contact portion;
[0013] FIG. 11 is a diagram showing dependence of a coupling ratio
and inter-cell interference on the thickness of the inter-electrode
insulating layer;
[0014] FIG. 12 is a sectional view showing a second
modification;
[0015] FIG. 13 is a sectional view showing a third
modification;
[0016] FIG. 14 is a sectional view showing a fourth
modification;
[0017] FIG. 15 is a sectional view showing a fifth
modification;
[0018] FIG. 16 is a sectional view showing a sixth
modification;
[0019] FIG. 17 is a sectional view showing a seventh
modification;
[0020] FIG. 18 is a sectional view showing an eighth
modification;
[0021] FIG. 19 is a sectional view showing a ninth
modification;
[0022] FIG. 20 is a sectional view showing a tenth
modification;
[0023] FIG. 21 is a sectional view showing an eleventh
modification;
[0024] FIG. 22 is a sectional view showing a twelfth
modification;
[0025] FIG. 23 is a sectional view showing a thirteenth
modification;
[0026] FIG. 24 is a sectional view showing a fourteenth
modification;
[0027] FIG. 25 is a sectional view showing a fifteenth
modification;
[0028] FIG. 26 is a plan view showing an array structure according
to a second embodiment;
[0029] FIG. 27 is a sectional view along a II-II line in FIG.
26;
[0030] FIG. 28 is a sectional view along a III-III line in FIG.
26;
[0031] FIG. 29 is a diagram showing an angle .theta. that decides
the shape of a charge storage layer;
[0032] FIG. 30 is a diagram showing the relationship between the
angle .theta. and electric lines of force;
[0033] FIG. 31 is a diagram showing an optimal range of offset of
the inter-electrode insulating layer;
[0034] FIGS. 32 to 36 are sectional views showing a manufacturing
method;
[0035] FIG. 37 is a sectional view showing a first
modification;
[0036] FIG. 38 is a sectional view showing a second
modification;
[0037] FIGS. 39 to 42 are sectional views showing a manufacturing
method;
[0038] FIG. 43 is a sectional view showing a third
modification;
[0039] FIG. 44 is a sectional view showing a fourth
modification;
[0040] FIG. 45 is a sectional view showing a fifth
modification;
[0041] FIG. 46 is a sectional view showing a sixth
modification;
[0042] FIG. 47 is a sectional view showing a seventh
modification;
[0043] FIG. 48 is a sectional view showing an eighth
modification;
[0044] FIG. 49 is a sectional view showing a ninth
modification;
[0045] FIG. 50 is a sectional view showing a tenth modification;
and
[0046] FIG. 51 is a sectional view showing an eleventh
modification.
DETAILED DESCRIPTION
[0047] In general, according to one embodiment, a nonvolatile
semiconductor memory device comprises: a semiconductor substrate;
first and second fin-type active areas arranged on the
semiconductor substrate, aligned in a first direction, and
extending in a second direction perpendicular to the first
direction; a first memory cell on the first fin-type active area;
and a second memory cell on the second fin-type active area,
wherein the first memory cell includes a first gate insulating
layer on the first fin-type active area, a first charge storage
layer arranged on the first gate insulating layer and in which a
width thereof in the first direction becomes narrower upward from
below, a first inter-electrode insulating layer covering an upper
portion of the first charge storage layer, and a control gate
electrode arranged on the first inter-electrode insulating layer
and extending in the first direction, the second memory cell
includes a second gate insulating layer on the second fin-type
active area, a second charge storage layer arranged on the second
gate insulating layer and in which the width thereof in the first
direction becomes narrower upward from below, a second
inter-electrode insulating layer covering an upper portion of the
second charge storage layer, and the control gate electrode
arranged on the second inter-electrode insulating layer, the first
and second inter-electrode insulating layers have a contact portion
through which both are in contact with each other in the first
direction, and thicknesses of the first and second inter-electrode
insulating layers in the contact portion in a third direction
perpendicular to the first and second directions are smaller than
thicknesses of the first and second inter-electrode insulating
layers in the third direction in top portions of the first and
second charge storage layers respectively.
First Embodiment
[0048] FIGS. 1 to 3 show an array structure.
[0049] FIG. 1 is a plan view of a memory cell array, FIG. 2 is a
sectional view along a II-II line in FIG. 1, and FIG. 3 is a
sectional view along a III-III line in FIG. 1.
[0050] Semiconductor substrate 11 is, for example, a silicon
substrate. The upper surface of semiconductor substrate 11 has an
irregular shape and projections form fin-type active areas AA. The
fin-type active areas AA are aligned in the row direction (first
direction) and also extend in the column direction (second
direction) perpendicular to the row direction.
[0051] The upper surface (bottom of depressions) of semiconductor
substrate 11 and the side face of the fin-type active areas AA may
be covered with insulating layer 12. Insulating layer 12 is, for
example, a layer of oxides formed by oxidizing semiconductor
substrate 11. Insulating layer 12 prevents electrons in the
fin-type active areas (channels) AA from escaping to an air gap
AG.
[0052] In the present example, the fin-type active areas AA are a
portion of semiconductor substrate 11, but are not limited to such
an example. For example, the fin-type active areas AA may be a
semiconductor layer such as an epitaxial layer on semiconductor
substrate 11.
[0053] Memory cells (Field Effect Transistor: FET) MC are arranged
on each fin-type active area AA. The memory cells MC on one
fin-type active area AA constitutes a NAND string, for example, by
being connected in series in the column direction.
[0054] Each memory cell MC includes a gate insulating layer (tunnel
insulating layer) TNL on the fin-type active area AA, a floating
gate electrode FG on the gate insulating layer TNL, an
inter-electrode insulating layer IPD on the floating gate electrode
FG, and a control gate electrode CG on the inter-electrode
insulating layer IPD.
[0055] The gate insulating layer TNL is, for example, a silicon
oxide layer and is formed by oxidizing the upper surface of the
fin-type active area AA.
[0056] The floating gate electrode FG is, for example, a
polysilicon layer, a metallic layer, or a lamination layer of these
layers. The width of the floating gate electrode FG in the row
direction gradually becomes narrower upward from below. In the
present example, the floating gate electrode FG is a triangle of a
base Fw and a height Fh, but the shape thereof is not limited to
the above example. For example, the floating gate electrode FG may
have a trapezoidal or semicircular shape.
[0057] However, the side face of the floating gate electrode FG in
the row direction is desirably plane or curved.
[0058] By adopting a tapering shape upward from below for the shape
of the floating gate electrode FG in this manner, inter-cell
interference can be mitigated.
[0059] The side face of the floating gate electrode FG in the row
direction may be covered with an insulating layer such as a layer
of oxides. In such a case, the insulating layer covering the side
face of the floating gate electrode FG in the row direction
prevents electrons stored in the floating gate electrode FG from
escaping to the air gap AG.
[0060] The inter-electrode insulating layer IPD covers an upper
portion of the floating gate electrode FG. A space between lower
portions of the floating gate electrode FG is the air gap AG. By
creating the air gap AG between lower portions, particularly
between lower edge portions, the effect of preventing the
inter-cell interference can further be increased.
[0061] To improve the coupling ratio of memory cells, the
inter-electrode insulating layer IPD includes a high dielectric
constant material having a higher dielectric constant than, for
example, a silicon oxide layer. The high dielectric constant
material is, for example, a metallic oxide such as Al.sub.2O.sub.3,
ZrO.sub.2, HfO.sub.2, HfSiO, HfAlO, LaAlO (LAO), and LaAlSiO (LASO)
or a laminated structure of these. The high dielectric constant
material may also be a laminated structure of a silicon oxide layer
and a silicon nitride layer like ONO.
[0062] If the floating gate electrode FG and the control gate
electrode CG contain a polysilicon layer, the inter-electrode
insulating layer IPD may also be called an inter-polysilicon
dielectric (IPD).
[0063] The control gate electrode CG includes a polysilicon layer,
a metallic silicide layer, or a laminated structure of these. The
control gate electrode CG and the inter-electrode insulating layer
IPD extend in the row direction. The control gate electrode CG
constitutes a word line.
[0064] In the above array structure, the two inter-electrode
insulating layers IPD of two memory cells adjacent in the row
direction share a contact portion through which both are in contact
with each other
[0065] The thickness (zero or almost zero in the present example)
of the two inter-electrode insulating layers IPD in the contact
portion in a vertical direction (third direction) perpendicular to
the row direction and the column direction is smaller than a
thickness T of the two inter-electrode insulating layers IPD in the
vertical direction in top portions Ftop of the two floating gate
electrodes FG of two memory cells adjacent in the row
direction.
[0066] Accordingly, the control gate electrode CG has a bottom
portion Cbottom in the contact portion of the two inter-electrode
insulating layers IPD. The bottom portion Cbottom of the control
gate electrode CG is below the top portion Ftop of the floating
gate electrode FG.
[0067] Therefore, according to the present example, the
inter-electrode insulating layer IPD and the control gate electrode
CG can partially be inserted between the two floating gate
electrodes FG. As a result, opposing portions of the floating gate
electrode FG and the control gate electrode CG increase and thus,
the coupling ratio of memory cells MC can be improved.
[0068] Moreover, according to the present example, like the flat
cell structure, an advantage that a half pitch hp is not restricted
by the inter-electrode insulating layer IPD and the control gate
electrode CG is not lost. This will be described more
concretely.
[0069] If half the distance (pitch of the active area AA) from the
center of one active area AA to the center of another adjacent
active area AA is defined as the half pitch hp, the half pitch hp
can be represented as:
hp=(tfg+tcg)/2+tipd (1)
[0070] If an imaginary line passing through the floating gate
electrode FG in a portion (upper portion) covered with the
inter-electrode insulating layer IPD and extending in the row
direction is assumed, tfg is the width in the row direction of the
floating gate electrode FG on the imaginary line, tcg is the width
in the row direction of the control gate electrode CG on the
imaginary line, and tipd is the width in the row direction of the
inter-electrode insulating layer IPD on the imaginary line.
[0071] If the thickness of the inter-electrode insulating layer IPD
in a direction perpendicular to the side face of the floating gate
electrode FG in the row direction is T, T and tipd are related
as:
tipd=T/cos .theta. (2)
[0072] While tipd is almost constant regardless of the location,
tfg and tcg change depending on the location. Moreover, tfg and tcg
have a complementary relation and tcg decreases with increasing tfg
and tcg increases with decreasing tfg.
[0073] That is, the present example is characterized in that even
if the inter-electrode insulating layer IPD and the control gate
electrode CG are partially inserted between the two floating gate
electrodes FG, the half pitch hp is not restricted by the
inter-electrode insulating layer IPD and the control gate electrode
CG.
[0074] The half pitch hp corresponds to half the pitch of a bit
line (not shown) arranged in the upper portion of the active area
AA.
[0075] Also according to the present example, the half pitch hp is
not restricted by the inter-electrode insulating layer IPD and the
control gate electrode CG and thus, a thickness tipd in the row
direction of the inter-electrode insulating layer IPD on the side
face of the floating gate electrode FG in the row direction can be
made larger than half a space Ws between active areas AA in the row
direction.
[0076] In a conventional structure in which the inter-electrode
insulating layer IPD and the control gate electrode CG getting in
between the two floating gate electrodes FG, by contrast, the
control gate electrode CG having a fixed thickness needs to be
inserted into a fixed space between the two floating gate
electrodes FG and thus, the thickness in the row direction of the
inter-electrode insulating layer IPD cannot be made larger than
half the space Ws between active areas AA in the row direction.
[0077] In the present example, an air gap is formed between the
floating gate electrodes FG, but can be replaced by an insulating
layer (for example, a silicon oxide layer) having a relative
dielectric constant smaller than that of the inter-electrode
insulating layer IPD. In addition, the charge storage layer of the
memory cells MC is the floating gate electrode FG in the present
example, but floating gate electrode FG can also be replaced by a
charge trap layer (insulating layer) having a function to trap
charges.
[0078] In the present example, the memory cells MC aligned in the
column direction do not have a diffusion layer in the fin-type
active area AA. This is because if each memory cell MC is made
finer, a channel can be formed in the fin-type active area AA due
to the so-called fringe effect without the diffusion layer.
[0079] However, each memory cell MC may have a diffusion layer in
the fin-type active area AA.
[0080] According to an array structure in the present example, an
increase in coupling ratio and prevention of inter-cell
interference can be realized in the flat cell structure at the same
time.
Manufacturing Method
[0081] The method of manufacturing a cell array structure according
to the first embodiment will be described.
[0082] First, as shown in FIG. 4, the gate insulating layer TNL and
the floating gate electrode FG are formed on semiconductor
substrate 11. The gate insulating layer TNL is, for example, a
silicon oxide layer and the floating gate electrode FG is, for
example, a polysilicon layer.
[0083] Then, a photoresist layer is formed on the floating gate
electrode FG by PEP (Photo Engraving Process). The photoresist
layer has a line & space pattern aligned with a fixed pitch in
the row direction and extending in the column direction.
[0084] Then, the floating gate electrode FG is patterned by RIE
(Reactive Ion Etching) using the photoresist layer as a mask. The
photoresist layer is removed and subsequently, the gate insulating
layer TNL and semiconductor substrate 11 are etched by dry etching
using the floating gate electrode FG as a mask.
[0085] As a result, the active area AA having a line & space
pattern aligned with a fixed pitch (2.times.half pitch hp) in the
row direction and extending in the column direction is formed. At
the same time, the floating gate electrode FG is partially etched
to form the floating gate electrode FG in a tapering shape upward
from below.
[0086] Then, the surface of semiconductor substrate 11 is covered
with insulating layer 12. Insulating layer 12 may be a natural
oxidation layer. The surface of the floating gate electrode FG may
also be covered with an insulating layer such as a natural
oxidation layer.
[0087] In place of the above process, the floating gate electrode
FG, the gate insulating layer TNL, and semiconductor substrate 11
may successively be etched by RIE using the photoresist layer as a
mask. In this case, after the etching, etching to form the floating
gate electrode FG into a tapering shape is performed.
[0088] Next, as shown in FIG. 5, insulating layer (for example, a
silicon oxide layer) 13 is formed only on an upper portion of the
floating gate electrode FG by using a film formation method with
poor coverage such as the sputter process and CVD method.
Subsequently, as shown in FIG. 6, insulating layer (for example, a
lanthanum aluminate layer) 14 is formed only on insulating layer 13
on the upper portion of the floating gate electrode FG by using a
film formation method with poor coverage such as the sputter
process and CVD method.
[0089] Then, two insulating layers 13, 14 are made to react by, for
example, heat treatment to form, as shown in FIG. 7, one insulating
layer (for example, a lanthanum aluminosilicate layer) as the
inter-electrode insulating layer IPD.
[0090] Lastly, as shown in FIG. 8, the control gate electrode CG is
formed on the inter-electrode insulating layer IPD. The control
gate electrode CG is formed by, for example, the following
process.
[0091] An electrode material is formed on the inter-electrode
insulating layer IPD and a mask layer is formed on the electrode
material. The mask layer has a line & space pattern aligned
with a fixed pitch in the column direction and extending in the row
direction.
[0092] Then, each of the electrode material and the inter-electrode
insulating layer IPD is patterned by RIE using the mask layer as a
mask. At this point, the floating gate electrode FG present in a
region that is not covered with the mask layer is also etched.
[0093] That is, the floating gate electrodes FG of memory cells
connected in series in the column direction are isolated from each
other.
[0094] The mask layer is, for example, a hard mask layer to perform
a sidewall patterning process (double patterning process). The
process is known as a technology to realize a narrow line width or
a narrow line pitch.
[0095] With the above manufacturing method, the cell array
structure according to the first embodiment is completed.
First Modification
[0096] FIG. 9 shows a cell array structure according to the first
modification.
[0097] FIG. 9 corresponds to the sectional view (FIG. 2) in the row
direction according to the first embodiment.
[0098] The cell array structure according to the present example is
different from the cell array structure according to the first
embodiment in that a thickness h in the vertical direction of a
contact portion of two inter-electrode insulating layers IPD of two
memory cells adjacent in the row direction exceeds zero.
[0099] However, like the first embodiment described above, the
thickness h in the vertical direction of the two inter-electrode
insulating layers IPD in the contact portion is desirably smaller
than a thickness T of the two inter-electrode insulating layers IPD
in the vertical direction in top portions Ftop of two floating gate
electrodes FG of two memory cells adjacent in the row
direction.
[0100] The present example is the same as the first embodiment in
other respects and thus, the description thereof is omitted.
[0101] FIG. 10 shows a relationship between the thickness T of the
inter-electrode insulating layer and the thickness h of the contact
portion.
[0102] As is evident from FIG. 10, when the thickness T of the
inter-electrode insulating layer IPD is a predetermined value X,
the two inter-electrode insulating layers IPD of two memory cells
adjacent in the row direction are in contact with each other. If
the thickness T of the inter-electrode insulating layer IPD exceeds
X, the thickness h of the contact portion of the two
inter-electrode insulating layers IPD increases in proportion to an
increase in thickness T of the inter-electrode insulating layer
IPD.
[0103] FIG. 11 shows relationships between a coupling ratio and
inter-cell interference and the thickness T of the inter-electrode
insulating layer.
[0104] In FIG. 11, shows the relationship between the coupling
ratio and the thickness T of the inter-electrode insulating layer
and shows the relationship between the inter-cell interference and
the thickness T of the inter-electrode insulating layer.
[0105] An increasing coupling ratio of memory cells is more
desirable, but if the thickness T of the inter-electrode insulating
layer IPD exceeds X, the coupling ratio decreases rapidly. This can
be considered to be caused by a decreasing opposing area of the
floating gate electrode FG and the control gate electrode CG with
an increasing thickness h of the contact portion of the two
inter-electrode insulating layers IPD. That is, the coupling ratio
increases with an increasing opposing area of both and thus, the
increasing thickness h of the contact portion invites a decrease in
coupling ratio.
[0106] Decreasing inter-cell interference (Yupin effect) is more
desirable, but if the thickness T of the inter-electrode insulating
layer IPD exceeds X, the inter-cell interference increases rapidly.
This can be considered to be caused by disappearance of an air gap
present between the two inter-electrode insulating layers IPD after
both come into contact with each other. That is, the relative
dielectric constant of the inter-electrode insulating layer IPD is
generally larger than the relative dielectric constant of an air
gap and thus, if the two inter-electrode insulating layers IPD come
into contact, inter-cell interference increases.
[0107] In a conventional structure (rocket structure), the
inter-electrode insulating layer IPD having a fixed thickness is
formed along the side face of the two adjacent floating gate
electrodes FG and thus, the two adjacent floating gate electrodes
FG electrically interfere with each other via
2.times.(inter-electrode insulating layer having a fixed
thickness).
[0108] According to the present modification, by contrast, the
thickness h in the contact portion of the two adjacent
inter-electrode insulating layers IPD is sufficiently smaller than
the thickness T of the inter-electrode insulating layer and thus
excels in preventing inter-cell interference.
[0109] It is more desirable that the thickness h in the contact
portion be smaller than half the thickness T (T/2) of the
inter-electrode insulating layer IPD. In a conventional structure,
the inter-electrode insulating layer IPD has a laminated structure
of silicon oxide and silicon nitride and the relative dielectric
constant thereof is about 4 to 5.
[0110] In the present modification, by contrast, a material
containing oxide of, for example, La, Hf, and Al is used for the
inter-electrode insulating layer IPD with a large relative
dielectric constant to increase the coupling ratio. In this case,
the relative dielectric constant of the inter-electrode insulating
layer IPD is assumed to be still larger than 9, which of the
relative dielectric constant of thin alumina.
[0111] Thus, according to the present modification, even if the
relative dielectric constant of the inter-electrode insulating
layer IPD is twice the relative dielectric constant of a
conventional structure or more, a material having such a large
relative dielectric constant can be prevented from being arranged
between the two adjacent floating gate electrodes FG by making the
thickness h in the contact portion of the two adjacent
inter-electrode insulating layers IPD smaller than half the
thickness T (T/2) of the inter-electrode insulating layer IPD.
[0112] Therefore, the present modification is effective in
preventing inter-cell interference.
[0113] If the relative dielectric constant of the inter-electrode
insulating layer IPD according to the present modification is about
N times the relative dielectric constant of 4 to 5 in a
conventional structure, setting h<T/N is a desirable condition
for realizing a large coupling ratio and prevention of inter-cell
interference at the same time.
[0114] What can be learned from the above is that in order to
achieve an increase in coupling ratio and prevention of inter-cell
interference, the thickness h of the contact portion when the two
inter-electrode insulating layers IPD of two memory cells adjacent
in the row direction are in contact with each other is desirably as
small as possible.
[0115] From the above consideration, it is clear that it is
desirable to set the thickness T of the inter-electrode insulating
layer IPD to less than X and to provide an opening between the two
inter-electrode insulating layers IPD of two memory cells adjacent
in the row direction without allowing the two inter-electrode
insulating layers IPD to come into contact.
Second Modification
[0116] FIG. 12 shows a cell array structure according to the second
modification.
[0117] FIG. 12 corresponds to the sectional view (FIG. 2) in the
row direction according to the first embodiment.
[0118] The cell array structure according to the present example is
different from the cell array structure according to the first
embodiment in that with an opening formed between two
inter-electrode insulating layers IPD of two memory cells adjacent
in the row direction, these inter-electrode insulating layers IPD
are isolated from each other.
[0119] The width in the row direction of the opening between the
two inter-electrode insulating layers IPD of two memory cells
adjacent in the row direction is Wsilt.
[0120] The width Wsilt is desirably narrower than a width Ws in the
row direction of two active areas AA adjacent in the row
direction.
[0121] According to the present example, the effect of an increase
in coupling ratio and prevention of inter-cell interference can
further be improved.
Third Modification
[0122] FIG. 13 shows a cell array structure according to the third
modification.
[0123] FIG. 13 corresponds to the sectional view (FIG. 2) in the
row direction according to the first embodiment.
[0124] The cell array structure according to the present example is
different from the cell array structure according to the first
embodiment in that a top portion of a floating gate electrode FG is
flat.
[0125] That is, the section of the floating gate electrode FG in
the row direction is trapezoidal. A bottom portion Cbottom of a
control gate electrode CG is below the top portion Ftop of the
floating gate electrode FG.
[0126] The bottom portion Cbottom of the control gate electrode CG
may be above the top portion Ftop of the floating gate electrode
FG, but as described above, the bottom portion Cbottom of the
control gate electrode CG is desirably below the top portion Ftop
of the floating gate electrode FG to improve the coupling
ratio.
[0127] Also according to the present example, an increase in
coupling ratio and prevention of inter-cell interference can be
realized at the same time.
Fourth Modification
[0128] FIG. 14 shows a cell array structure according to the fourth
modification.
[0129] FIG. 14 corresponds to the sectional view (FIG. 2) in the
row direction according to the first embodiment. The cell array
structure according to the present example is different from the
cell array structure according to the first embodiment in that a
floating gate electrode FG has a multilayer structure.
[0130] That is, the floating gate electrode FG includes a first
conductive layer FG1 on a gate insulating layer TNL and a second
conductive layer FG2 on the first conductive layer FG1.
[0131] The first conductive layer FG1 is, for example, a
polysilicon layer. The second conductive layer FG2 is, for example,
a titanium layer, tungsten layer, tantalum layer, titanium nitride
layer, tungsten nitride layer, or tantalum nitride layer. The first
and second conductive layers FG1, FG2 are not limited to the above
materials, but have mutually different materials.
[0132] Mutually different materials include a case when the first
conductive layer FG1 contains a portion or all of compositions of
the second conductive layer FG2.
[0133] The above case is, for example, a case when the second
conductive layer FG2 is a titanium layer, tungsten layer, or
tantalum layer and the first conductive layer FG1 is a titanium
silicide layer, tungsten silicide layer, or tantalum silicide
layer.
[0134] At least the upper portion of the second conductive layer
FG2 is completely covered with the inter-electrode insulating layer
IPD, but the entire second conductive layer FG2 may be covered with
the inter-electrode insulating layer IPD or a portion of the first
conductive layer FG1 may be covered with the inter-electrode
insulating layer IPD.
[0135] Also according to the present example, an increase in
coupling ratio and prevention of inter-cell interference can be
realized at the same time.
Fifth Modification
[0136] FIG. 15 shows a cell array structure according to the fifth
modification.
[0137] FIG. 15 corresponds to the sectional view (FIG. 2) in the
row direction according to the first embodiment.
[0138] The present example is a further modification of the fourth
modification. The cell array structure according to the present
example is different from the cell array structure according to the
fourth modification in that the side face of the first conductive
layer FG1 in the row direction is not inclined (tapered) and is
almost perpendicular to the upper surface of semiconductor
substrate 11.
[0139] Whether the shape of the floating gate electrode FG is like
in the fourth modification or the fifth modification depends on the
materials of the first and second conductive layers FG1, FG2 and
conditions for patterning the floating gate electrode FG.
[0140] At least the upper portion of the second conductive layer
FG2 is completely covered with the inter-electrode insulating layer
IPD, but the entire second conductive layer FG2 may be covered with
the inter-electrode insulating layer IPD or a portion of the first
conductive layer FG1 may be covered with the inter-electrode
insulating layer IPD.
[0141] Also according to the present example, an increase in
coupling ratio and prevention of inter-cell interference can be
realized at the same time.
Sixth Modification
[0142] FIG. 16 shows a cell array structure according to the sixth
modification.
[0143] FIG. 16 corresponds to the sectional view (FIG. 2) in the
row direction according to the first embodiment.
[0144] The present example is a further modification of the fourth
or fifth modification. The cell array structure according to the
present example is different from the cell array structure
according to the fourth or fifth modification in that the width of
the first conductive layer FG1 in the row direction is narrower
than the width of the bottom portion (bottom) of the second
conductive layer FG2 in the row direction.
[0145] The structure of the present example can easily be formed by
selectively performing recess etching of only the first conductive
layer FG1 after the floating gate electrode FG being patterned.
[0146] By narrowing the width of the first conductive layer FG1 in
the row direction in this manner, inter-cell interference can
further be prevented.
[0147] At least the upper portion of the second conductive layer
FG2 is completely covered with the inter-electrode insulating layer
IPD, but the entire second conductive layer FG2 may be covered with
the inter-electrode insulating layer IPD or a portion of the first
conductive layer FG1 may be covered with the inter-electrode
insulating layer IPD.
[0148] Also according to the present example, an increase in
coupling ratio and prevention of inter-cell interference can be
realized at the same time.
Seventh Modification
[0149] FIG. 17 shows a cell array structure according to the
seventh modification.
[0150] FIG. 17 corresponds to the sectional view (FIG. 2) in the
row direction according to the first embodiment.
[0151] The cell array structure according to the present example is
different from the cell array structure according to the first
embodiment in that the side face in a lower portion of the floating
gate electrode FG in the row direction is not inclined (tapered)
and is almost perpendicular to the upper surface of semiconductor
substrate 11.
[0152] Whether the shape of the floating gate electrode FG is like
in the first embodiment or the present example depends on the
materials constituting the floating gate electrode FG and
conditions for patterning the floating gate electrode FG.
[0153] Also according to the present example, an increase in
coupling ratio and prevention of inter-cell interference can be
realized at the same time.
Eighth Modification
[0154] FIG. 18 shows a cell array structure according to the eighth
modification.
[0155] FIG. 18 corresponds to the sectional view (FIG. 2) in the
row direction according to the first embodiment.
[0156] The cell array structure according to the present example is
different from the cell array structure according to the first
embodiment in that an inter-electrode insulating layer has a
multilayer structure.
[0157] That is, in the present example, the inter-electrode
insulating layer includes a first insulating layer IPD1 and a
second insulating layer IPD2 constituted of mutually different
materials. Mutually different materials include a case when one of
the first and second insulating layers IPD1, IPD2 contains a
portion or all of elements constituting the other.
[0158] A case when the first and second insulating layers IPD1,
IPD2 have the same component elements, but have different
composition ratios is also assumed to be mutually different
materials.
[0159] In the present example, the inter-electrode insulating layer
has two layers, but the present example is not limited to such an
example. That is, the inter-electrode insulating layer may have
three layers or more.
[0160] Also according to the present example, an increase in
coupling ratio and prevention of inter-cell interference can be
realized at the same time.
Ninth Modification
[0161] FIG. 19 shows a cell array structure according to the ninth
modification.
[0162] FIG. 19 corresponds to the sectional view (FIG. 2) in the
row direction according to the first embodiment.
[0163] The present example is a combination of the second
modification and the eighth modification. The cell array structure
according to the present example is characterized in that an
inter-electrode insulating layer (second insulating layer) IPD2 is
further formed as if to close an opening (width: Wslit) between two
inter-electrode insulating layers (first insulating layer) IPD1 of
two memory cells adjacent in the row direction.
[0164] Like the eighth modification, the first and second
insulating layers IPD1, IPD2 desirably include mutually different
materials. In the present example, the two first insulating layers
IPD1 adjacent in the row direction are isolated via the opening,
but both may be in contact with each other.
[0165] Also according to the present example, an increase in
coupling ratio and prevention of inter-cell interference can be
realized at the same time.
Tenth Modification
[0166] FIG. 20 shows a cell array structure according to the tenth
modification.
[0167] FIG. 20 corresponds to the sectional view (FIG. 2) in the
row direction according to the first embodiment.
[0168] The cell array structure according to the present example is
different from the cell array structure according to the first
embodiment in that a charge storage layer of a memory cell includes
a floating gate electrode FG as a conductive layer in an
electrically floating state and a charge trap layer CT as an
insulating layer arranged on the floating gate electrode FG to trap
charges.
[0169] For example, the floating gate electrode FG whose sectional
shape in the row direction is trapezoidal is arranged on a gate
insulating layer (tunnel insulating layer) TNL. Further, the charge
trap layer CT whose sectional shape in the row direction is
triangular is arranged on the floating gate electrode FG.
[0170] The floating gate electrode FG includes, as described above,
a polysilicon layer, a metallic layer, or a lamination layer of
these layers. The charge trap layer CT includes an insulating layer
of SiN, SiON, Al.sub.2O.sub.3, HfO or the like.
[0171] In the present example, an insulating layer (ultra-thin
insulating layer) I of, for example, 10 nm or less in thickness is
arranged between the floating gate electrode FG and the charge trap
layer CT. The insulating layer I may be omitted.
[0172] The charge trap layer CT is completely covered with an
inter-electrode insulating layer IPD, but a portion of the charge
trap layer CT may be covered with the inter-electrode insulating
layer IPD or a portion of the floating gate electrode FG may be
covered with the inter-electrode insulating layer IPD.
[0173] The above structure is called the so-called hybrid type.
[0174] According to the hybrid type, the charge storage layer of a
memory cell includes the floating gate electrode FG and the charge
trap layer CT. The charge trap layer CT has a function to raise a
potential barrier by trapping charges and thus has an effect of
preventing a leak current between two charge storage layers
adjacent in the row or column direction.
[0175] The present example can realize an increase in coupling
ratio and prevention of inter-cell interference at the same
time.
Eleventh Modification
[0176] FIG. 21 shows a cell array structure according to the
eleventh modification.
[0177] FIG. 21 corresponds to the sectional view (FIG. 2) in the
row direction according to the first embodiment.
[0178] The present example is a further modification of the tenth
modification. The cell array structure according to the present
example is different from the tenth modification in that an entire
charge trap layer CT and further a portion of a floating gate
electrode FG are covered with an inter-electrode insulating layer
IPD.
[0179] In other respects, the eleventh modification is the same as
the tenth modification.
[0180] With the structure as described above, the same effect as
the above hybrid type can be achieved.
Twelfth Modification
[0181] FIG. 22 shows a cell array structure according to the
twelfth modification.
[0182] FIG. 22 corresponds to the sectional view (FIG. 2) in the
row direction according to the first embodiment.
[0183] The present example is also a further modification of the
tenth modification. The cell array structure according to the
present example is different from the tenth modification in that a
portion of a charge trap layer CT is covered with an
inter-electrode insulating layer IPD.
[0184] In other respects, the twelfth modification is the same as
the tenth modification.
[0185] With the structure as described above, the same effect as
the above hybrid type can be achieved.
Thirteenth Modification
[0186] FIG. 23 shows a cell array structure according to the
thirteenth modification.
[0187] FIG. 23 corresponds to the sectional view (FIG. 2) in the
row direction according to the first embodiment.
[0188] The cell array structure according to the present example
relates, like the tenth modification described above, to the hybrid
type. The present example is characterized in that a charge trap
layer CT is formed so as to cover a portion of the surface or the
entire surface of a floating gate electrode FG.
[0189] For example, the floating gate electrode FG whose sectional
shape in the row direction is triangular is arranged on a gate
insulating layer (tunnel insulating layer) TNL. Further, an
insulating layer (ultra-thin insulating layer) I of, for example,
10 nm or less in thickness is arranged so as to cover the entire
surface of the floating gate electrode FG. The insulating layer may
be omitted.
[0190] The charge trap layer CT is arranged on the surface of an
upper portion of the floating gate electrode FG via the insulating
layer I.
[0191] The floating gate electrode FG includes, as described above,
a polysilicon layer, a metallic layer, or a lamination layer of
these layers. The charge trap layer CT includes an insulating layer
of SiN, SiON, Al.sub.2O.sub.3, HfO or the like.
[0192] The charge trap layer CT is completely covered with an
inter-electrode insulating layer IPD, but a portion of the charge
trap layer CT may be covered with the inter-electrode insulating
layer IPD or a portion of the floating gate electrode FG may be
covered with the inter-electrode insulating layer IPD.
[0193] According to the above structure, the charge storage layer
of a memory cell includes the floating gate electrode FG and the
charge trap layer CT. The charge trap layer CT has a function to
raise a potential barrier by trapping charges and thus has an
effect of preventing a leak current between two charge storage
layers adjacent in the row or column direction.
[0194] The present example can realize an increase in coupling
ratio and prevention of inter-cell interference at the same
time.
Fourteenth Modification
[0195] FIG. 24 shows a cell array structure according to the
fourteenth modification.
[0196] FIG. 24 corresponds to the sectional view (FIG. 2) in the
row direction according to the first embodiment.
[0197] The present example is a further modification of the
thirteenth modification. The cell array structure according to the
present example is different from the thirteenth modification in
that an entire charge trap layer CT and further a portion of a
floating gate electrode FG are covered with an inter-electrode
insulating layer IPD.
[0198] For example, a portion in an area between the floating gate
electrode FG and the inter-electrode insulating layer IPD where the
charge trap layer CT is not present is an air gap.
[0199] In other respects, the fourteenth modification is the same
as the thirteenth modification.
[0200] With the structure as described above, the same effect as
the above hybrid type can be achieved.
Fifteenth Modification
[0201] FIG. 25 shows a cell array structure according to the
fifteenth modification.
[0202] FIG. 25 corresponds to the sectional view (FIG. 2) in the
row direction according to the first embodiment.
[0203] The present example is also a further modification of the
thirteenth modification. The cell array structure according to the
present example is different from the thirteenth modification in
that a charge trap layer CT covers an entire floating gate
electrode FG and further the surface of an active area AA.
[0204] Even if the charge trap layer CT covers the surface of the
active area AA, a portion that actually traps charges is a portion
adjacent to the floating gate electrode FG and thus, no problem is
caused as memory cell characteristics.
[0205] In other respects, the fifteenth modification is the same as
the thirteenth modification.
[0206] With the structure as described above, the same effect as
the above hybrid type can be achieved.
[0207] In the above modifications excluding the third modification,
the top portion of the floating gate electrode FG or the charge
trap layer CT as a charge storage layer is acute, but may also be
round. In such a case, leakage of information charges due to
electric field concentration in an acute angle portion in the top
portion can be reduced. An increase in coupling ratio and
prevention of inter-cell interference can similarly be realized at
the same time.
Summary
[0208] According to the first embodiment as described above, an
increase in coupling ratio and prevention of inter-cell
interference can be realized at the same time.
[0209] The air gap AG in all examples according to the first
embodiment described above may be replaced by an insulating layer
(for example, a silicon oxide layer) whose relative dielectric
constant is smaller than that of the inter-electrode insulating
layer IPD.
[0210] In each example of the first embodiment shown in FIGS. 1 to
19, the floating gate electrode FG may be replaced by the charge
trap layer as an insulating layer that traps charges. That is, in
these examples of the first embodiment, the charge storage layer of
a memory cell may be a floating gate electrode or a charge trap
layer.
Second Embodiment
[0211] FIGS. 26 to 28 show an array structure.
[0212] FIG. 26 is a plan view of a memory cell array, FIG. 27 is a
sectional view along a II-II line in FIG. 26, and FIG. 28 is a
sectional view along a III-III line in FIG. 26.
[0213] Semiconductor substrate 11 is, for example, a silicon
substrate. The upper surface of semiconductor substrate 11 has an
irregular shape and projections form fin-type active areas AA. The
fin-type active areas AA is aligned in the row direction (first
direction) and also extend in the column direction (second
direction) perpendicular to the row direction.
[0214] The upper surface (bottom of depressions) of semiconductor
substrate 11 and the side face of the fin-type active areas AA may
be covered with insulating layer 12. Insulating layer 12 is, for
example, a layer of oxides formed by oxidizing semiconductor
substrate 11. Insulating layer 12 prevents electrons in the
fin-type active areas (channels) AA from escaping to an air gap
AG.
[0215] In the present example, the fin-type active areas AA are a
portion of semiconductor substrate 11, but are not limited to such
an example. For example, the fin-type active areas AA may be a
semiconductor layer such as an epitaxial layer on semiconductor
substrate 11.
[0216] Memory cells (Field Effect Transistor: FET) MC are arranged
on each fin-type active area AA. The memory cells MC on one
fin-type active area AA constitutes a NAND string, for example, by
being connected in series in the column direction.
[0217] Each memory cell MC includes a gate insulating layer (tunnel
insulating layer) TNL on the fin-type active area AA, a floating
gate electrode FG on the gate insulating layer TNL, an
inter-electrode insulating layer IPD on the floating gate electrode
FG, and a control gate electrode CG on the inter-electrode
insulating layer IPD.
[0218] The gate insulating layer TNL is, for example, a silicon
oxide layer and is formed by oxidizing the upper surface of the
fin-type active area AA.
[0219] The floating gate electrode FG is, for example, a
polysilicon layer, a metallic layer, or a lamination layer of these
layers. The width of the floating gate electrode FG in the row
direction gradually becomes narrower upward from below. In the
present example, the floating gate electrode FG is a triangle of a
base Fw and a height Fh, but the shape thereof is not limited to
the above example. For example, the floating gate electrode FG may
have a trapezoidal or semicircular shape.
[0220] However, the side face of the floating gate electrode FG
present in the row direction is desirably plane or curved.
[0221] In the present example, the shape of the floating gate
electrode FG as described above by an angle .theta.. The angle
.theta. is an angle formed by a tangent L-ta and a horizontal plane
(upper surface of semiconductor substrate 11) at a contact point P
of an edge IPD-edge of the inter-electrode insulating layer and the
surface of the floating gate electrode FG as shown in FIG. 29.
[0222] The edge IPD-edge of the inter-electrode insulating layer is
the lower surface of the inter-electrode insulating layer, more
specifically, the lower surface of the inter-electrode insulating
layer between fin-type active areas AA. In other words, if a memory
cell is cut in an up and down direction by a line extending in the
row direction, the edge IPD-edge refers to a portion of the lower
surface of the inter-electrode insulating layer that is not in
contact with the floating gate electrode FG. A point on the surface
of the floating gate electrode FG where a line of the lower surface
of the inter-electrode insulating layer touches is set as the
contact point P.
[0223] If, for example, the floating gate electrode FG is designed
to be an isosceles triangle, the angle .theta. is, as shown in FIG.
29A, means a low angle of the floating gate electrode FG. When a
device is actually manufactured, even if the floating gate
electrode FG is designed as an isosceles triangle, as shown in FIG.
29B, an oblique side extending from a vertex is frequently formed
as a curved shape. In such a case, the definition of the above
angle .theta. is very useful to determine the shape of the floating
gate electrode FG.
[0224] In the present example, the angle .theta. is set to the
range of 0.degree.<.theta..ltoreq.45.degree.. The reason
therefor is as follows.
[0225] If the angle .theta. is, for example, as shown in FIG. 30A,
a rocket type in the range of 45.degree.<.theta.<90.degree.,
the opposing area of the floating gate electrode FG and the control
gate electrode CG increase and so the coupling ratio of memory
cells can be improved.
[0226] Moreover, by adopting a structure in which a lower edge
portion of the floating gate electrode FG is not covered with the
inter-electrode insulating layer IPD, inter-cell interference can
be prevented. This effect is made more conspicuous by creating an
air gap between lower edge portions of the two floating gate
electrodes FG.
[0227] However, as is evident from FIG. 30A, the number of electric
lines of force extending one floating gate electrode FG to other
floating gate electrodes adjacent thereto increases with the
increasing angle .theta.. This means an increase of inter-cell
interference due to an increase of parasitic capacitance caused
between the two floating gate electrodes FG.
[0228] Therefore, it is very important to estimate the optimal
range of the angle .theta. to guide almost all electric lines of
force extending from the floating gate electrode FG to the control
gate electrode CG and to achieve improvement of the coupling ratio
and prevention of inter-cell interference at the same time.
[0229] In the present example, as a result of simulation and
verification using an actual device, as shown in FIG. 30B, the
inventors found that many electric lines of force extending from
the floating gate electrode FG can be guided to the control gate
electrode CG by setting the angle .theta. to the range of
0.degree.<.theta..ltoreq.45.degree..
[0230] If the floating gate electrode FG is a conductor, the
surface thereof is always an equipotential surface and thus, an
electric line of force always comes out from the surface of the
floating gate electrode FG in a direction perpendicular to the
surface thereof.
[0231] Therefore, if the angle .theta. is in the range of
.theta..ltoreq.45.degree., an electric line of force on the surface
of the floating gate electrode FG is less likely to move in the
horizontal direction to the side of the adjacent floating gate
electrodes FG and more likely to move in the vertical direction to
the side of the control gate electrode CG.
[0232] As a result, by setting the angle .theta. to the range of
.theta..ltoreq.45.degree., many electric lines of force extending
from the floating gate electrode FG can be guided to the control
gate electrode CG. If the floating gate electrode FG is not a
perfect electric conductor, the floating gate electrode FG still
has a similar tendency and in such a case, the angle .theta. is
desirably in the range of .theta..ltoreq.45.degree..
[0233] The floating gate electrode FG has a tapering shape in which
the width thereof becomes gradually narrower upward from below and
thus, improvement of the coupling ratio due to an increased
opposing area of the floating gate electrode FG and the control
gate electrode CG can be realized.
[0234] Thus, improvement of the coupling ratio of memory cells and
prevention of inter-cell interference can be realized at the same
time by adopting the tapering shape for the floating gate electrode
FG and setting the angle .theta. to the range of
0.degree..ltoreq..theta..ltoreq.45.degree..
[0235] The side face of the floating gate electrode FG present in
the row direction may be covered with an insulating layer such as a
layer of oxides. In such a case, the insulating layer covering the
side face of the floating gate electrode FG present in the row
direction prevents electrons stored in the floating gate electrode
FG from escaping to an air gap AG.
[0236] The inter-electrode insulating layer IPD covers an upper
portion of the floating gate electrode FG. A space between lower
portions of the floating gate electrode FG is the air gap AG. By
creating the air gap AG between lower portions, particularly
between lower edge portions, the effect of preventing inter-cell
interference can further be increased.
[0237] If only a case when the lower edge portion of the floating
gate electrode FG is not covered with the inter-electrode
insulating layer IPD is considered, as shown in FIG. 31, the range
of the contact point P can suitably be selected from a range of a
lower surface (bottom) A (excluding the lower surface A) of the
floating gate electrode FG to a surface B passing through a top Top
of the floating gate electrode FG and parallel to the horizontal
plane.
[0238] However, if the actual manufacturing process and improvement
of the coupling ratio are considered, the range of the contact
point P is further limited.
[0239] Thus, an offset of the inter-electrode insulating layer IPD
is as an index that the lower edge portion of the floating gate
electrode FG is not covered with the inter-electrode insulating
layer IPD. The offset of the inter-electrode insulating layer IPD
is, as shown in FIG. 31, is the shortest distance L-offset from the
lower surface (bottom) A of the floating gate electrode FG to the
contact point P.
[0240] If the offset L-offset of the inter-electrode insulating
layer IPD is too small, an increase of inter-cell interference is
invited and conversely, if the offset L-offset is too large, a
decrease of the coupling ratio of memory cells is invited and thus,
the optimal range satisfying both at the same time exists.
[0241] In the present example, as a result of simulation and
verification using an actual device, as shown in FIG. 31, the
inventors found that the optimal range of the contact point P
(offset of the inter-electrode insulating layer) is a surface C
positioned a width d above the lower surface (bottom) A of the
floating gate electrode FG or above, and a surface D passing
through half a height Fh (Fh/2) of the floating gate electrode FG
or below.
[0242] To ensure the coupling ratio, for example, the angle .theta.
is expected to be designed at 45.degree.. In such a case, if the
contact point P is at (Fh/2), a covered surface area of the
floating gate electrode FG by the inter-electrode insulating layer
will be (bottom area of the floating gate
electrode).times.2.sup.1/2/2=(bottom area of the floating gate
electrode).times.0.7.
[0243] The covered surface area refers to the surface of the
floating gate electrode FG in the row direction.
[0244] In contrast, the area of the control gate electrode CG
opposed to the floating gate electrode FG is given by (bottom area
of the floating gate electrode).times.1.4 if the height Fh of the
floating gate electrode FG is about 10 nm and the physical film
thickness of the inter-electrode insulating layer is about 10 nm.
This is about twice the covered surface area of the floating gate
electrode FG by the inter-electrode insulating layer.
[0245] From the above, if the contact point P is set to (Fh/2), the
average value of the opposing area between the floating gate
electrode FG and the control gate electrode CG via the
inter-electrode insulating layer is given by (bottom area of the
floating gate electrode).times.[(0.7+1.4)/2], which is
approximately equal to the bottom area of the floating gate
electrode FG.
[0246] Being equal to the bottom area of the floating gate
electrode FG means being equal to the opposing area (bottom area of
the floating gate electrode) between the floating gate electrode FG
and the control gate electrode CG in the floating gate electrode FG
(quadrangular shape) in the flat cell structure.
[0247] Therefore, according to the second embodiment, it is clear
that a larger effective area (opposing area between the floating
gate electrode FG and the control gate electrode CG) than the
effective area of the flat cell structure can be realized by
setting the contact point P lower than (Fh/2).
[0248] The width d is about 1 nm. That is, if the height Fh of the
floating gate electrode FG is assumed to be 10 nm, the optimal
range of the contact point P will be the range of 1 nm or more and
5 nm or less from the lower surface A of the floating gate
electrode FG.
[0249] The offset L-offset needs the lower limit d=1 nm because
electric lines of force moving toward the adjacent floating gate
electrodes FG are concentrated in acute angle portions on both ends
at the bottom of the floating gate electrode FG. That is, if acute
angle portions on both ends at the bottom of the floating gate
electrode FG should be covered with an inter-electrode insulating
layer having a high dielectric constant, this is contrary to the
original purpose of moving many electric lines of force toward the
control gate electrode CG.
[0250] Moreover, the height Fh of the floating gate electrode FG is
assumed to be 10 nm or less and thus, if the offset of d=1 nm,
which is 10% of the maximum value (10 nm) of the height Fh, or more
is secured, acute angle portions on both ends at the bottom of the
floating gate electrode FG can reliably be prevented from being
covered with the inter-electrode insulating layer so that almost
all electric lines of force coming out from the surface of the
floating gate electrode FG can be guided to the control gate
electrode CG.
[0251] Therefore, the coupling ratio can be secured and at the same
time, inter-cell interference can be prevented.
[0252] To improve the coupling ratio of memory cells, the
inter-electrode insulating layer IPD includes, for example, a high
dielectric constant material having a higher dielectric constant
than a silicon oxide layer. The high dielectric constant material
is, for example, a metallic oxide such as Al.sub.2O.sub.3,
ZrO.sub.2, HfO.sub.2, HfSiO, HfAlO, LaAlO (LAO), and LaAlSiO (LASO)
or a laminated structure of these. The high dielectric constant
material may also be a laminated structure of a silicon oxide layer
and a silicon nitride layer like ONO.
[0253] If the floating gate electrode FG and the control gate
electrode CG contain a polysilicon layer, the inter-electrode
insulating layer IPD may also be called an inter-polysilicon
dielectric (IPD).
[0254] The control gate electrode CG includes a polysilicon layer,
a metallic silicide layer, or a laminated structure of these. The
control gate electrode CG and the inter-electrode insulating layer
IPD extend in the row direction. The control gate electrode CG
constitutes a word line.
[0255] In the above array structure, the two inter-electrode
insulating layers IPD of two memory cells adjacent in the row
direction share a contact portion through which both are in contact
with each other.
[0256] The thickness (zero or almost zero in the present example)
of the two inter-electrode insulating layers IPD in the contact
portion in a vertical direction (third direction) perpendicular to
the row direction and the column direction is smaller than a
thickness T of the two inter-electrode insulating layers IPD in the
vertical direction in top portions Ftop of the two floating gate
electrodes FG of two memory cells adjacent in the row
direction.
[0257] Accordingly, the control gate electrode CG has a bottom
portion Cbottom in the contact portion of the two inter-electrode
insulating layers IPD. The bottom portion Cbottom of the control
gate electrode CG is above the top portion Ftop of the floating
gate electrode FG.
[0258] A half pitch hp corresponds to half the pitch of a bit line
(not shown) arranged in the upper portion of the active area
AA.
[0259] In the present example, an air gap is formed between the
floating gate electrodes FG, but can be replaced by an insulating
layer (for example, a silicon oxide layer) having a relative
dielectric constant smaller than that of the inter-electrode
insulating layer IPD. In addition, the charge storage layer of the
memory cells MC is the floating gate electrode FG in the present
example, but the floating gate electrode FG can also be replaced by
a charge trap layer (insulating layer) having a function to trap
charges.
[0260] In the present example, the memory cells MC aligned in the
column direction do not have a diffusion layer in the fin-type
active area AA. This is because if each memory cell MC is made
finer, a channel can be formed in the fin-type active area AA due
to the so-called fringe effect without the diffusion layer.
[0261] However, each memory cell MC may have a diffusion layer in
the fin-type active area AA.
[0262] According to an array structure in the present example, an
increase in coupling ratio and prevention of inter-cell
interference can be realized in the flat cell structure at the same
time.
Manufacturing Method
[0263] The method of manufacturing a cell array structure according
to the second embodiment will be described.
[0264] First, as shown in FIG. 32, the gate insulating layer TNL
and the floating gate electrode FG are formed on semiconductor
substrate 11. The gate insulating layer TNL is, for example, a
silicon oxide layer and the floating gate electrode FG is, for
example, a polysilicon layer.
[0265] Then, a photoresist layer is formed on the floating gate
electrode FG by PEP (Photo Engraving Process). The photoresist
layer has a line & space pattern aligned with a fixed pitch in
the row direction and extending in the column direction.
[0266] Then, the floating gate electrode FG is patterned by RIE
(Reactive Ion Etching) using the photoresist layer as a mask. The
photoresist layer is removed and subsequently, the gate insulating
layer TNL and semiconductor substrate 11 are etched by dry etching
using the floating gate electrode FG as a mask.
[0267] As a result, the active area AA having a line & space
pattern aligned with a fixed pitch (2.times.half pitch hp) in the
row direction and extending in the column direction is formed. At
the same time, the floating gate electrode FG is partially etched
to form the floating gate electrode FG in a tapering shape upward
from below.
[0268] Then, the surface of semiconductor substrate 11 is covered
with insulating layer 12. Insulating layer 12 may be a natural
oxidation layer. The surface of the floating gate electrode FG may
also be covered with an insulating layer such as a natural
oxidation layer.
[0269] In place of the above process, the floating gate electrode
FG, the gate insulating layer TNL, and semiconductor substrate 11
may successively be etched by RIE using the photoresist layer as a
mask. In this case, after the etching, etching to form the floating
gate electrode FG into a tapering shape is performed.
[0270] Next, as shown in FIG. 33, insulating layer (for example, a
silicon oxide layer) 13 with poor coverage is formed only on an
upper portion of the floating gate electrode FG by the sputter
process or CVD method. Subsequently, as shown in FIG. 34,
insulating layer (for example, a lanthanum aluminate layer) 14 with
poor coverage is formed only on insulating layer 13 on the upper
portion of the floating gate electrode FG by the sputter process or
CVD method.
[0271] Then, two insulating layers 13, 14 are made to react by, for
example, heat treatment to form, as shown in FIG. 35, one
insulating layer (for example, a lanthanum aluminosilicate layer)
as the inter-electrode insulating layer IPD.
[0272] Lastly, as shown in FIG. 36, the control gate electrode CG
is formed on the inter-electrode insulating layer IPD. The control
gate electrode CG is formed by, for example, the following
process.
[0273] An electrode material is formed on the inter-electrode
insulating layer IPD and a mask layer is formed on the electrode
material. The mask layer has a line & space pattern aligned
with a fixed pitch in the column direction and extending in the row
direction.
[0274] Then, each of the electrode material and the inter-electrode
insulating layer IPD is patterned by RIE using the mask layer as a
mask. At this point, the floating gate electrode FG present in a
region that is not covered with the mask layer is also etched.
[0275] That is, the floating gate electrodes FG of memory cells
connected in series in the column direction are isolated from each
other.
[0276] The mask layer is, for example, a hard mask layer to perform
a sidewall patterning process (double patterning process). The
process is known as a technology to realize a narrow line width or
a narrow line pitch.
[0277] With the above manufacturing method, the cell array
structure according to the second embodiment is completed.
First Modification
[0278] FIG. 37 shows a cell array structure according to the first
modification.
[0279] FIG. 37 corresponds to the sectional view (FIG. 27) in the
row direction according to the second embodiment.
[0280] The cell array structure according to the present example is
different from the cell array structure according to the second
embodiment in that with an opening formed between two
inter-electrode insulating layers IPD of two memory cells adjacent
in the row direction, these inter-electrode insulating layers IPD
are isolated from each other.
[0281] The width in the row direction of the opening between the
two inter-electrode insulating layers IPD of two memory cells
adjacent in the row direction is Wsilt.
[0282] The width Wsilt is desirably narrower than a width Ws in the
row direction of two active areas AA adjacent in the row
direction.
[0283] According to the present example, the effect of an increase
in coupling ratio and prevention of inter-cell interference can
further be improved.
Second Modification
[0284] FIG. 38 shows a cell array structure according to the second
modification.
[0285] FIG. 38 corresponds to the sectional view (FIG. 27) in the
row direction according to the second embodiment.
[0286] The cell array structure according to the present example is
different from the cell array structure according to the second
embodiment in that the bottom of two inter-electrode insulating
layers IPD of two memory cells adjacent in the row direction is
flat.
[0287] This structure results from the manufacturing method.
[0288] When the inter-electrode insulating layer IPD is formed from
an insulating layer with poor coverage, a structure according to
the second embodiment or the first modification can be obtained. In
this case, however, a portion of the material constituting the
inter-electrode insulating layer IPD may be deposited inside an air
gap AG between active areas AA.
[0289] Thus, a structure according to the present example may be
obtained by forming the inter-electrode insulating layer IPD while
the air gap AG between active areas AA is filled with a dummy
insulating layer and then selectively removing the dummy insulating
layer.
[0290] According to the manufacturing method, the bottom of the two
inter-electrode insulating layers IPD of two memory cells adjacent
in the row direction becomes flat.
[0291] A concrete manufacturing method will be described below.
[0292] First, as shown in FIG. 39, the gate insulating layer TNL
and the floating gate electrode FG are formed on semiconductor
substrate 11. The gate insulating layer TNL is, for example, a
silicon oxide layer and the floating gate electrode FG is, for
example, a polysilicon layer.
[0293] Then, a photoresist layer is formed on the floating gate
electrode FG by PEP. The photoresist layer has a line & space
pattern aligned with a fixed pitch in the row direction and
extending in the column direction.
[0294] Then, the floating gate electrode FG is patterned by RIE
using the photoresist layer as a mask. The photoresist layer is
removed and subsequently, the gate insulating layer TNL and
semiconductor substrate 11 are etched by dry etching using the
floating gate electrode FG as a mask.
[0295] As a result, the active area AA having a line & space
pattern aligned with a fixed pitch (2.times.half pitch hp) in the
row direction and extending in the column direction is formed. At
the same time, the floating gate electrode FG is partially etched
to form the floating gate electrode FG in a tapering shape upward
from below.
[0296] Then, the surface of semiconductor substrate 11 is covered
with insulating layer 12. Insulating layer 12 may be a natural
oxidation layer. The surface of the floating gate electrode FG may
also be covered with an insulating layer such as a natural
oxidation layer.
[0297] In place of the above process, the floating gate electrode
FG, the gate insulating layer TNL, and semiconductor substrate 11
may successively be etched by RIE using the photoresist layer as a
mask. In this case, after the etching, etching to form the floating
gate electrode FG into a tapering shape is performed.
[0298] Next, as shown in FIG. 40, the air gap AG between active
areas AA is filled with dummy insulating layer 15. The upper
surface of dummy insulating layer 15 is above the bottom of the
floating gate electrode FG.
[0299] That is, the lower edge portion of the floating gate
electrode FG is covered with dummy insulating layer 15. Next, as
shown in FIG. 41, the inter-electrode insulating layer (for
example, a lanthanum aluminosilicate layer) IPD is formed on each
of the floating gate electrode FG and dummy insulating layer 15 by
the sputter process or CVD method.
[0300] Subsequently, the control gate electrode CG is formed on the
inter-electrode insulating layer IPD.
[0301] Then, a mask layer is formed on the control gate electrode
CG. The mask layer has a line & space pattern aligned with a
fixed pitch in the column direction and extending in the row
direction.
[0302] Then, each of the control gate electrode CG and the
inter-electrode insulating layer IPD is patterned by RIE using the
mask layer as a mask. At this point, the floating gate electrode FG
present in a region that is not covered with the mask layer is also
etched.
[0303] That is, the floating gate electrodes FG of memory cells
connected in series in the column direction are isolated from each
other.
[0304] The mask layer is, for example, a hard mask layer to perform
a sidewall patterning process (double patterning process). The
process is known as a technology to realize a narrow line width or
a narrow line pitch.
[0305] Lastly, as shown in FIG. 42, dummy insulating layer 15 in
FIG. 41 is selectively removed from a space between the control
gate electrode CG and the inter-electrode insulating layer IPD
processed as a line & space pattern by, for example, wet
etching using a dilute fluoric acid solution
[0306] As a result, the air gap AG is formed between active areas
AA.
[0307] With the above manufacturing method, the cell array
structure according to the second modification is completed.
Third Modification
[0308] FIG. 43 shows a cell array structure according to the third
modification.
[0309] FIG. 43 corresponds to the sectional view (FIG. 27) in the
row direction according to the second embodiment.
[0310] The present example is a further modification of the second
modification. The cell array structure according to the present
example is different from the cell array structure according to the
second modification in that a top portion of a floating gate
electrode FG is flat.
[0311] That is, the section of the floating gate electrode FG in
the row direction is trapezoidal.
[0312] Moreover, as described above, if the floating gate electrode
FG is designed to be trapezoidal, each side of the trapezoid may be
curved in an actual device, resulting in a shape close to a
semicircular shape.
[0313] Even in such a case, if conditions of the shape (angle
.theta.) of the floating gate electrode FG and the offset of the
inter-electrode insulating layer described in the second embodiment
are met, an increase in coupling ratio and prevention of inter-cell
interference can be realized in the flat cell structure at the same
time.
Fourth Modification
[0314] FIG. 44 shows a cell array structure according to the fourth
modification.
[0315] FIG. 44 corresponds to the sectional view (FIG. 27) in the
row direction according to the second embodiment.
[0316] The present example is also a further modification of the
second modification. The cell array structure according to the
present example is different from the cell array structure
according to the second modification in that a floating gate
electrode FG has a multilayer structure.
[0317] That is, the floating gate electrode FG includes a first
conductive layer FG1 on a gate insulating layer TNL and a second
conductive layer FG2 on the first conductive layer FG1.
[0318] The first conductive layer FG1 is, for example, a
polysilicon layer. The second conductive layer FG2 is, for example,
a titanium layer, tungsten layer, or tantalum layer. The first and
second conductive layers FG1, FG2 are not limited to the above
materials, but have mutually different materials.
[0319] Mutually different materials include a case when the first
conductive layer FG1 contains a portion or all of compositions of
the second conductive layer FG2.
[0320] The above case is, for example, a case when the second
conductive layer FG2 is a titanium layer, tungsten layer, or
tantalum layer and the first conductive layer FG1 is a titanium
silicide layer, tungsten silicide layer, or tantalum silicide
layer.
[0321] Also according to the present example, an increase in
coupling ratio and prevention of inter-cell interference can be
realized in the flat cell structure at the same time.
Fifth Modification
[0322] FIG. 45 shows a cell array structure according to the fifth
modification.
[0323] FIG. 45 corresponds to the sectional view (FIG. 27) in the
row direction according to the second embodiment.
[0324] The present example is also a further modification of the
second modification. The cell array structure according to the
present example is different from the cell array structure
according to the second modification in that the side face in a
lower portion of the floating gate electrode FG in the row
direction is not inclined (tapered) and is almost perpendicular to
the upper surface of semiconductor substrate 11.
[0325] Whether the shape of the floating gate electrode FG is like
in the second embodiment or the present example depends on the
materials constituting the floating gate electrode FG and
conditions for patterning the floating gate electrode FG.
[0326] Also according to the present example, an increase in
coupling ratio and prevention of inter-cell interference can be
realized in the flat cell structure at the same time.
Sixth Modification
[0327] FIG. 46 shows a cell array structure according to the sixth
modification.
[0328] FIG. 46 corresponds to the sectional view (FIG. 27) in the
row direction according to the second embodiment.
[0329] The cell array structure according to the present example is
different from the cell array structure according to the second
modification in that a charge storage layer of a memory cell
includes a floating gate electrode FG as a conductive layer in an
electrically floating state and a charge trap layer CT as an
insulating layer arranged on the floating gate electrode FG to trap
charges.
[0330] For example, the floating gate electrode FG whose sectional
shape in the row direction is trapezoidal is arranged on a gate
insulating layer (tunnel insulating layer) TNL. Further, the charge
trap layer CT whose sectional shape in the row direction is
triangular is arranged on the floating gate electrode FG.
[0331] The floating gate electrode FG includes, as described above,
a polysilicon layer, a metallic layer, or a lamination layer of
these layers. The charge trap layer CT includes an insulating layer
of SiN, SiON, Al.sub.2O.sub.3, HfO or the like.
[0332] In the present example, an insulating layer (ultra-thin
insulating layer) I of, for example, 10 nm or less in thickness is
arranged between the floating gate electrode FG and the charge trap
layer CT. The insulating layer I may be omitted.
[0333] The charge trap layer CT is completely covered with an
inter-electrode insulating layer IPD, but a portion of the charge
trap layer CT may be covered with the inter-electrode insulating
layer IPD or a portion of the floating gate electrode FG may be
covered with the inter-electrode insulating layer IPD.
[0334] The above structure is called the so-called hybrid type.
[0335] According to the hybrid type, the charge storage layer of a
memory cell includes the floating gate electrode FG and the charge
trap layer CT. The charge trap layer CT has a function to raise a
potential barrier by trapping charges and thus has an effect of
preventing a leak current between two charge storage layers
adjacent in the row or column direction.
[0336] The present example can realize an increase in coupling
ratio and prevention of inter-cell interference in the flat cell
structure at the same time.
Seventh Modification
[0337] FIG. 47 shows a cell array structure according to the
seventh modification.
[0338] FIG. 47 is an enlarged view of one memory cell in the sixth
modification.
[0339] The cell array structure according to the present example is
different from the sixth modification in that an entire charge trap
layer CT and further a portion of a floating gate electrode FG are
covered with an inter-electrode insulating layer IPD.
[0340] In other respects, the seventh modification is the same as
the sixth modification.
[0341] With the structure as described above, the same effect as
the above hybrid type can be achieved.
Eighth Modification
[0342] FIG. 48 shows a cell array structure according to the eighth
modification.
[0343] FIG. 48 is also an enlarged view of one memory cell in the
sixth modification.
[0344] The cell array structure according to the present example is
different from the sixth modification in that a portion of a charge
trap layer CT is covered an inter-electrode insulating layer
IPD.
[0345] In other respects, the eighth modification is the same as
the sixth modification.
[0346] With the structure as described above, the same effect as
the above hybrid type can be achieved.
Ninth Modification
[0347] FIG. 49 shows a cell array structure according to the ninth
modification.
[0348] FIG. 49 corresponds to the sectional view (FIG. 27) in the
row direction according to the second embodiment.
[0349] The cell array structure according to the present example
relates, like the sixth modification, to the hybrid type. The
present example is different from the cell array structure
according to the second modification in that a charge trap layer CT
is formed so as to cover a portion of the surface or the entire
surface of a floating gate electrode FG.
[0350] For example, the floating gate electrode FG whose sectional
shape in the row direction is triangular is arranged on a gate
insulating layer (tunnel insulating layer) TNL. Further, an
insulating layer (ultra-thin insulating layer) I of, for example,
10 nm or less in thickness is arranged so as to cover the entire
surface of the floating gate electrode FG. The insulating layer may
be omitted.
[0351] The charge trap layer CT is arranged on the surface of an
upper portion of the floating gate electrode FG via the insulating
layer I.
[0352] The floating gate electrode FG includes, as described above,
a polysilicon layer, a metallic layer, or a lamination layer of
these layers. The charge trap layer CT includes an insulating layer
of SiN, SiON, Al.sub.2O.sub.3, HfO or the like.
[0353] The charge trap layer CT is completely covered with an
inter-electrode insulating layer IPD, but a portion of the charge
trap layer CT may be covered with the inter-electrode insulating
layer IPD or a portion of the floating gate electrode FG may be
covered with the inter-electrode insulating layer IPD.
[0354] According to the above structure, the charge storage layer
of a memory cell includes the floating gate electrode FG and the
charge trap layer CT. The charge trap layer CT has a function to
raise a potential barrier by trapping charges and thus has an
effect of preventing a leak current between two charge storage
layers adjacent in the row or column direction.
[0355] The present example can realize an increase in coupling
ratio and prevention of inter-cell interference in the flat cell
structure at the same time.
Tenth Modification
[0356] FIG. 50 shows a cell array structure according to the tenth
modification.
[0357] FIG. 50 is an enlarged view of one memory cell in the ninth
modification.
[0358] The cell array structure according to the present example is
different from the ninth modification in that an entire charge trap
layer CT and further a portion of a floating gate electrode FG are
covered with an inter-electrode insulating layer IPD.
[0359] For example, a portion in an area between the floating gate
electrode FG and the inter-electrode insulating layer IPD where the
charge trap layer CT is not present is an air gap.
[0360] In other respects, the tenth modification is the same as the
ninth modification.
[0361] With the structure as described above, the same effect as
the above hybrid type can be achieved.
Eleventh Modification
[0362] FIG. 51 shows a cell array structure according to the
eleventh modification.
[0363] FIG. 51 is an enlarged view of one memory cell in the ninth
modification.
[0364] The cell array structure according to the present example is
different from the ninth modification in that an entire charge trap
layer CT covers an entire floating gate electrode FG and further
the surface of an active area AA.
[0365] Even if the charge trap layer CT covers the surface of the
active area AA, a portion that actually traps charges is a portion
adjacent to the floating gate electrode FG and thus, no problem is
caused as memory cell characteristics.
[0366] In other respects, the eleventh modification is the same as
the ninth modification.
[0367] With the structure as described above, the same effect as
the above hybrid type can be achieved.
Summary
[0368] According to the second embodiment as described above, an
increase in coupling ratio and prevention of inter-cell
interference can be realized in the flat cell structure at the same
time.
[0369] The air gap AG in each example according to the second
embodiment described above may be replaced by an insulating layer
(for example, a silicon oxide layer) whose relative dielectric
constant is smaller than that of the inter-electrode insulating
layer IPD.
[0370] In each example of the second embodiment shown in FIGS. 26
to 45, the floating gate electrode FG may be replaced by the charge
trap layer as an insulating layer that traps charges. That is, in
these examples of the second embodiment, the charge storage layer
of a memory cell may be a floating gate electrode or a charge trap
layer.
[0371] While certain embodiments have been described, these
embodiments have been presented by way of example only, and are not
intended to limit the scope of the inventions. Indeed, the novel
embodiments described herein may be embodied in a variety of other
forms; furthermore, various omissions, substitutions and changes in
the form of the embodiments described herein may be made without
departing from the spirit of the inventions. The accompanying
claims and their equivalents are intended to cover such forms or
modifications as would fall within the scope and spirit of the
inventions.
* * * * *