U.S. patent application number 14/502477 was filed with the patent office on 2015-01-15 for semiconductor device and method for manufacturing the same.
The applicant listed for this patent is SK HYNIX INC.. Invention is credited to Kyung Do KIM.
Application Number | 20150017773 14/502477 |
Document ID | / |
Family ID | 48571198 |
Filed Date | 2015-01-15 |
United States Patent
Application |
20150017773 |
Kind Code |
A1 |
KIM; Kyung Do |
January 15, 2015 |
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
Abstract
In the semiconductor device, a line-type buried gate is formed
by burying a non-operating gate (isolation gate) with a polysilicon
material to reduce a work function and a Gate Induced Drain Leakage
(GIDL) caused by the non-operating gate, resulting in improvement
of refresh characteristics of the semiconductor device. Operating
gates including a metal conductive material may be formed in a
separate step.
Inventors: |
KIM; Kyung Do; (Seoul,
KR) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
SK HYNIX INC. |
Icheon |
|
KR |
|
|
Family ID: |
48571198 |
Appl. No.: |
14/502477 |
Filed: |
September 30, 2014 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
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13708905 |
Dec 7, 2012 |
8878289 |
|
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14502477 |
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Current U.S.
Class: |
438/270 |
Current CPC
Class: |
H01L 27/10876 20130101;
H01L 27/10823 20130101; H01L 29/7813 20130101; H01L 27/10891
20130101; H01L 21/28123 20130101; H01L 21/76 20130101; H01L 21/762
20130101; H01L 29/7827 20130101; H01L 29/66666 20130101 |
Class at
Publication: |
438/270 |
International
Class: |
H01L 29/78 20060101
H01L029/78; H01L 21/76 20060101 H01L021/76; H01L 21/28 20060101
H01L021/28 |
Foreign Application Data
Date |
Code |
Application Number |
Dec 8, 2011 |
KR |
10-2011-0130830 |
Claims
1. A method for manufacturing a semiconductor device comprising:
forming a non-operating gate in a semiconductor substrate; forming
a first hard mask layer over the semiconductor substrate and the
non-operating gate; forming a trench by etching the first hard mask
layer; burying an insulation film in the trench; etching a center
portion of the insulation film; burying a second hard mask layer in
spaces formed by etching the center portion of the insulation film;
removing the remaining insulation film; forming an operating gate
region by etching the semiconductor substrate using the second and
first hard mask layers as an etch mask; and forming an operating
gate in the operating gate region.
2. The method according to claim 1, wherein forming the
non-operating gate includes: sequentially forming a hard mask oxide
film and a hard mask carbon film over the semiconductor substrate;
forming a non-operating gate region by etching the hard mask carbon
film and the hard mask oxide film; forming a gate oxide film in the
non-operating gate region; forming a gate polysilicon layer over
the gate oxide film; etching back the gate polysilicon layer; and
forming a nitride film over the etched-back gate polysilicon
layer.
3. The method according to claim 2, wherein forming the
non-operating gate region includes: anisotropically etching the
hard mask carbon film and the hard mask oxide film.
4. The method according to claim 1, wherein forming the first hard
mask layer includes: forming a hard mask oxide film over the
semiconductor substrate including the non-operating gate; and
forming a hard mask polysilicon film over the hard mask oxide
film.
5. The method according to claim 1, wherein forming the trench
includes: anisotropically etching a portion of the first hard mask
layer disposed between the non-operating gates.
6. The method according to claim 1, wherein the insulation film
includes an oxide film.
7. The method according to claim 1, wherein the second hard mask
layer includes a polysilicon film.
8. The method according to claim 1, wherein forming the operating
gate region includes anisotropically etching the semiconductor
substrate.
9. The method according to claim 1, wherein forming the operating
gate in the operating gate region includes: forming a gate oxide
film in the operating gate region; forming a gate electrode layer
over the gate oxide film; etching back the gate electrode layer;
and forming a nitride film over the etched-back gate electrode
layer.
10. The method according to claim 1, wherein the non-operating gate
and the operating gate are formed as line type structures.
11. The method according to claim 1, further comprising: after
forming the operating gate, forming a source/drain region by
implanting N-type impurity ions in the semiconductor substrate.
12.-15. (canceled)
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] The priority of Korean patent application No.
10-2011-0130830 filed on 8 Dec. 2011, the disclosure of which is
hereby incorporated in its entirety by reference, is claimed.
BACKGROUND OF THE INVENTION
[0002] Embodiments of the present invention relate to a
semiconductor device and a method for manufacturing the same in
which a line-type buried gate is formed by burying a non-operating
gate (isolation gate) with a polysilicon material.
[0003] A semiconductor memory device includes a plurality of unit
cells each having a capacitor and a transistor. The capacitor is
used to temporarily store data, and the transistor is used to
transfer data between a bit line and the capacitor in response to a
control signal (word line). The data transfer occurs using a
semiconductor property wherein an electrical conductivity changes
depending on conditions. The transistor has three regions: a gate,
a source, and a drain. Electric charges are moved between the
source and the drain according to a control signal inputted to the
gate of the transistor. The movement of the electric charges
between the source and the drain is achieved through a channel
region.
[0004] Where a general transistor is formed on a semiconductor
substrate, a conventional method of forming a gate on the
semiconductor substrate includes doping impurities into both sides
of the gate to form a source and a drain. As the data storage
capacity of semiconductor memory devices increases and the size of
features decreases, the size of each unit cell also decreases. That
is, a design rule of the capacitor and the transistor included in
the unit cell has been reduced. Thus, while the channel length of a
cell transistor is gradually decreased, the short channel effect,
Drain Induced Barrier Lower (DIBL), etc., occur in a general
transistor and thus operational reliability is decreased. By
maintaining a threshold voltage such that the cell transistor
performs a normal operation, it is possible to solve some of the
problems caused by decreased channel length. In general, as the
channel of the transistor shortens, the concentration of the
impurities doped into a region in which the channel is formed has
been increased.
[0005] However, if the concentration of the impurities doped into
the channel region is increased while the design rule is reduced to
100 nm or less, the electric field of a Storage Node (SN) junction
is increased, thereby lowering the refresh characteristics of a
semiconductor memory device. In order to solve this problem, a cell
transistor having a three-dimensional channel structure in which a
channel extends in a vertical direction is used such that the
channel length of the cell transistor is maintained even when the
design rule is decreased. That is, even when a channel width in a
horizontal direction is short, since the channel length of the
vertical direction is secured, impurity doping concentration may be
reduced and thus, refresh characteristics are maintained.
[0006] In addition, as the degree of integration of semiconductor
devices is increased, the distance between a word line coupled to a
cell transistor and a bit line coupled to the cell transistor is
gradually reduced. As a result, there may arise shortcomings in
which parasitic capacitance is increased such that an operating
margin of a sense amplifier (sense-amp) that amplifies data
transmitted via the bit line is deteriorated, resulting in a
negative influence upon operation of the semiconductor device. In
order to solve the above-mentioned shortcomings while
simultaneously reducing parasitic capacitance between a bit line
and a word line, a buried word line structure in which a word line
is formed only in a recess instead of an upper part of the
semiconductor substrate has been proposed. The buried word line
structure includes a conductive material in a recess formed in a
semiconductor substrate, and an insulation film covering an upper
part of the conductive material such that the word line is buried
in a semiconductor substrate. As a result, the buried word line
structure can be electrically isolated from a bit line formed over
a semiconductor substrate including source/drain regions.
[0007] However, the buried word line (buried gate) structure has
some disadvantages. First, GIDL characteristics of a semiconductor
device are deteriorated between a conductive material (gate
electrode) and an N-type junction of an active region. Second,
refresh characteristics of the whole semiconductor device are
deteriorated due to the deteriorated GIDL characteristics.
BRIEF SUMMARY OF THE INVENTION
[0008] Various embodiments of the present invention are directed to
providing a semiconductor device and a method for manufacturing the
same that substantially obviate one or more problems due to
limitations and disadvantages of the related art, including those
discussed herein.
[0009] An embodiment of the present invention relates to a
semiconductor device and a method for manufacturing the same in
which a line-type buried gate is formed by burying a non-operating
gate (isolation gate) with a polysilicon material to reduce a work
function and a Gate Induced Drain Leakage (GIDL) caused by the
non-operating gate, resulting in improvement of refresh
characteristics of the semiconductor device.
[0010] In accordance with one aspect of the present invention, a
method for manufacturing a semiconductor device includes forming a
non-operating gate in a semiconductor substrate; forming a first
hard mask layer over the semiconductor substrate and the
non-operating gate; forming a trench by etching the first hard mask
layer; burying an insulation film in the trench; after etching a
center part of the insulation film contained in the trench, burying
a second hard mask layer in the etched region; removing the
remaining insulation film; forming an operation gate region by
etching the semiconductor substrate using the second and first hard
mask layers as an etch mask; and forming an operation gate in the
operation gate region.
[0011] The forming of the non-operating gate may include
sequentially forming a hard mask oxide film and a hard mask carbon
film over the semiconductor substrate; forming a non-operating gate
region by etching the hard mask carbon film and the hard mask oxide
film; forming a gate oxide film in the non-operating gate region;
forming a gate polysilicon layer over the gate oxide film; etching
back the gate polysilicon layer; and forming a nitride film over
the etched-back gate polysilicon layer.
[0012] The forming of the non-operating gate region may include
forming the non-operating gate region by anisotropically etching
the hard mask carbon film and the hard mask oxide film.
[0013] The forming of the first hard mask layer may include forming
a hard mask oxide film not only over the semiconductor substrate
but also over the non-operating gate; and forming a hard mask
polysilicon film over the hard mask oxide film.
[0014] The forming of the trench may include anisotropically
etching a first hard mask layer formed over semiconductor substrate
disposed between the non-operating gates.
[0015] The insulation film may include an oxide film.
[0016] The second hard mask layer may include a polysilicon
film.
[0017] The forming of the operation gate region may include
anisotropically etching the semiconductor substrate.
[0018] The forming of the operation gate in the operation gate
region may include forming a gate oxide film in the operation gate
region; forming a gate electrode layer over the gate oxide film;
etching back the gate electrode layer; and forming a nitride film
over the etched-back gate electrode layer.
[0019] The non-operating gate and the operation gate may be formed
as a line type.
[0020] The method may further include after forming the operation
gate, forming a source/drain region by implanting N-type impurity
ions in the semiconductor substrate.
[0021] In accordance with another aspect of the present invention,
a semiconductor device includes an operation gate comprising a
laminate structure of a gate oxide film, a gate metal layer, and a
nitride film and a non-operating gate comprising a laminate
structure of a gate oxide film, a gate polysilicon layer, and a
nitride film formed in a semiconductor substrate.
[0022] The non-operating gate and the operation gate may be formed
as a line type.
[0023] The semiconductor device may further include a source/drain
region disposed between the operation gates.
[0024] It is to be understood that both the foregoing general
description and the following detailed description of the present
invention are only exemplary and are intended to provide further
explanation of the invention as claimed, but are not limited to the
described embodiments.
BRIEF DESCRIPTION OF THE DRAWINGS
[0025] FIG. 1 is a plan view illustrating a semiconductor device
and a method for manufacturing the same according to an embodiment
of the present invention.
[0026] FIGS. 2A to 2H are cross-sectional views illustrating a
semiconductor device and a method for manufacturing the same
according to an embodiment of the present invention.
[0027] FIG. 3 is a block diagram illustrating a cell array
according to the present invention.
[0028] FIG. 4 is a block diagram illustrating a semiconductor
device according to the present invention.
[0029] FIG. 5 is a block diagram illustrating a semiconductor
module according to the present invention.
[0030] FIG. 6 is a block diagram illustrating a semiconductor
system according to the present invention.
[0031] FIG. 7 is a block diagram illustrating an electronic unit
and an electronic system according to embodiments of the present
invention.
DESCRIPTION OF EMBODIMENTS
[0032] Reference will now be made in detail to embodiments of the
present invention, examples of which are illustrated in the
accompanying drawings. Wherever possible, the same reference
numbers will be used throughout the drawings to refer to the same
or like parts.
[0033] FIG. 1 is a plan view illustrating a semiconductor device
and a method for manufacturing the same according to an embodiment
of the present invention.
[0034] Referring to FIG. 1, a device isolation region 225 defining
an active region 215, and buried gates 260' and 350' crossing the
active region 215 are formed over a semiconductor substrate 200. In
an embodiment, the active region 215 is formed as an island type,
and each buried gate 260' or 350' includes an operating gate 350'
and a non-operating gate 260' and is formed as a line type.
[0035] The device isolation region 225 for defining an active
region 215 is formed as described below.
[0036] A pad insulation film (not shown) comprising a pad oxide
film and a pad nitride film is deposited over the semiconductor
substrate 200. Thereafter, a photoresist film (not shown) is
deposited, and an exposure process is carried out using a mask
configured to define the active region 215. Subsequently, a Spin On
Dielectric (SOD) material is buried in a trench (not shown) formed
by etching the exposed pad insulation film and the semiconductor
substrate 200, and is then processed by Chemical Mechanical
Polishing (CMP) until the pad insulation film is exposed, thereby
creating the device isolation region 225.
[0037] FIGS. 2A to 2H are cross-sectional views illustrating a
semiconductor device and a method for manufacturing the same
according to an embodiment of the present invention. In more
detail,
[0038] FIGS. 2A to 2H are cross-sectional views illustrating the
semiconductor device taken along the line A-A' of FIG. 1.
[0039] Referring to FIG. 2A, a hard mask oxide film 210 and a hard
mask carbon film 220 are sequentially formed over the semiconductor
substrate 200.
[0040] Referring to FIG. 2B, after a photoresist film is formed
over the hard mask carbon film 220, a photoresist pattern (not
shown) is formed by an exposure and development process using a
non-operating gate mask (or an isolation gate mask).
[0041] Thereafter, the hard mask carbon film 220 is etched using
the photoresist pattern as an etch mask so that a hard mask carbon
film pattern (not shown) is formed. Subsequently, the hard mask
oxide film 210 and the semiconductor substrate 200 are etched using
the hard mask carbon film pattern as an etch mask, so that a first
trench 230 is formed. In an embodiment, the etching process for
forming the first trench 230 is an anisotropic etching process.
[0042] Referring to FIG. 2C, a gate oxide film 240 is formed in the
first trench 230, a polysilicon film 250 is formed over the gate
oxide film 240, and the gate polysilicon film 250 is then etched
back. In embodiments, the gate oxide film 240 may be formed by
deposition of an oxide film or an oxidation process.
[0043] Then, a nitride film 260 is formed over the etched-back gate
polysilicon film 250 and the semiconductor substrate 200. The
nitride film 260 is then CMP-etched (or planarized) until the
semiconductor substrate 200 is exposed, so that a non-operating
260' (i.e., an isolation gate) is formed. Both the nitride film 260
and the non-operating gate 260' may be formed as line type
structures. In an embodiment, no voltage is applied to
non-operating gate 260'. A non-operating gate may also be referred
to as a dummy gate.
[0044] Referring to FIG. 2D, a hard mask oxide film 270 and a hard
mask polysilicon film 280 are formed over the semiconductor
substrate 200 and the non-operating gate 260'.
[0045] After forming a photoresist film (not shown) over the hard
mask polysilicon film 280, a photoresist pattern (not shown) is
formed by an exposure and development process using a mask defining
an region in which an operational gate will be subsequently formed.
The hard mask polysilicon film 280 and the hard mask oxide film 270
are etched using the photoresist pattern as an etch mask, so that a
second trench 290 is formed. The etching process for forming the
second trench 290 may be an anisotropic etching process.
[0046] Referring to FIG. 2E, an insulation film 300 is buried in
the second trench 290. Preferably, the insulation film 300 may
include an oxide film.
[0047] After forming a photoresist film (not shown) over the
insulation film 300 and the hard mask polysilicon film 280, a
photoresist pattern (not shown) is formed by an exposure and
development process using a mask configured to expose only a center
part of the insulation film 300. The insulation film 300 is etched
using the photoresist pattern as an etch mask so that a hole 305 is
formed.
[0048] Subsequently, a hard mask polysilicon film 310 is buried in
the hole 305.
[0049] Referring to FIG. 2F, the insulation film 300 disposed on
both sides of the hard mask polysilicon film 310 is removed so that
third trenches 315 are formed.
[0050] Referring to FIG. 2G, the hard mask oxide film 270 and the
semiconductor substrate 200 are etched using the hard mask
polysilicon films 310 and 280 as an etch mask, so that a trench is
formed in operating gate region 320.
[0051] Referring to FIG. 2H, after a gate oxide film 330 and a gate
electrode material 340 are formed in the operating gate region 320,
the gate electrode material 340 is etched back. In embodiments, the
gate oxide film 330 may be formed either by deposition of an oxide
film or by an oxidation process. In addition, the gate electrode
material 340 may include aluminium (Al), tungsten (W), tungsten
nitride (WN), titanium (Ti), titanium nitride (TiN), or titanium
nitride/tungsten (TiN/W).
[0052] After forming a nitride film 350 not only over the
etched-back gate electrode material 340 but also over the
semiconductor substrate 200, the nitride film 350 is
planarized-etched until the semiconductor substrate 200 is exposed,
so that an operating gate 350' is formed. Next, exposed portions of
semiconductor substrate 200 may be etched back, and a conductive
material may be deposited to form a junction region 360 between
neighboring gates. In an embodiment, junction region 360 may
include a conductive material such as a metal or doped polysilicon.
The resulting structure may include a plurality of non-operating
gates 260' comprising a conductive polysilicon material, and a
plurality of operating gates 350' comprising a conductive metal
material.
[0053] FIG. 3 illustrates a cell array according to the present
invention.
[0054] Referring to FIG. 3, the cell array includes a plurality of
memory cells, and each memory cell includes one transistor and one
capacitor. Such memory cells are located at intersection points of
bit lines BL1.about.BLn and word lines WL1.about.WLm. The memory
cells may store or output data in response to a voltage applied to
any bit line (BL1, . . . , BLn) and any word line (WL1, . . . ,
WLm) selected by a column decoder and a row decoder.
[0055] As can be seen from FIG. 3, bit lines (BL1, . . . , BLn) in
a first direction (bit-line direction) are formed in the
longitudinal direction, and word lines (WL1, . . . , WLm) in a
second direction (word-line direction) are formed in the
latitudinal direction, such that the bit lines (BL1, . . . , BLn)
are crossed with the word lines (WL1, . . . , WLm). A first
terminal (for example, a drain terminal) of each transistor is
coupled to one of the bit lines (BL1, . . . , BLn), a second
terminal (for example, a source terminal) of each transistor is
coupled to a capacitor, and a third terminal (for example, a gate
terminal) of each transistor is coupled to one of the word lines
(WL1, . . . , WLm). A plurality of memory cells including the bit
lines (BL1, . . . , BLn) and the word lines (WL1, . . . , WLm) are
thus formed in a semiconductor cell array.
[0056] FIG. 4 is a block diagram illustrating a semiconductor
device according to the present invention.
[0057] Referring to FIG. 4, the semiconductor device may include a
cell array, a row decoder, a column decoder, and a sense amplifier
(SA). The row decoder selects a word line corresponding to a memory
cell, in which a read or write operation is to be performed, from
among a plurality of word lines of the semiconductor cell array.
The row decoder further outputs a word line selection signal (RS)
to the semiconductor cell array. In addition, the column decoder
selects a bit line corresponding to a memory cell, in which a read
or write operation is to be performed, from among a plurality of
bit lines of the semiconductor cell array. The column decoder
outputs a bit line selection signal (CS) to the semiconductor cell
array. In addition, the sense-amplifier (SA) senses data (BDS)
stored in a memory cell selected by the row decoder and column
decoder.
[0058] Furthermore, the semiconductor device may be coupled to a
microprocessor or a memory controller. The semiconductor device may
receive control signals such as WE* (write enable signal), RAS*
(row address strobe signal), and CAS* (column address strobe
signal) from the microprocessor, receive data through an
input/output (I/O) circuit, and store the received data. The
semiconductor device may be applied to a Dynamic Random Access
Memory (DRAM), a P-Random Access Memory (P-RAM), an M-Random Access
Memory (M-RAM), a NAND flash memory, and a CMOS Image Sensor (CIS),
and the like. Specifically, the semiconductor device may be
applicable to a desktop computer, a laptop computer, or a server,
and may also be applicable to a graphic memory and a mobile memory.
The NAND flash memory may be applicable not only to a variety of
portable storage media (for example, a memory stick, a multimedia
card (MMC), a secure digital (SD) card, a compact flash (CF) card,
an extreme Digital (XD) picture card, a universal serial bus (USB)
flash drive, etc.), but also to a variety of digital applications
(for example, MP3, PMP, digital camera, camcorder, memory card,
USB, game machine, navigation, laptop computer, desktop computer,
mobile phone, and the like). The CMOS Image Sensor (CIS) is a
charge coupled device (CCD) serving as an electronic film in
digital devices, and is applicable to a camera phone, a Web camera,
a small-sized medical imaging devices, etc.
[0059] FIG. 5 is a block diagram illustrating a semiconductor
module according to the present invention.
[0060] Referring to FIG. 5, a semiconductor module includes a
plurality of semiconductor devices mounted to a module substrate, a
command link, and a data link. The command link enables each
semiconductor device to receive a control signal (address signal
(ADDR)), a command signal (CMD), and a clock signal (CLK) from an
external controller (not shown). The data link is coupled to each
semiconductor device to transmit and receive data to and from each
semiconductor device.
[0061] In one embodiment, the semiconductor device may correspond
to the semiconductor devices disclosed in FIG. 5. In addition, the
command link and the data link may be formed to be identical or
similar to those of general semiconductor modules.
[0062] Although eight semiconductor chips are mounted to the front
surface of the module substrate as shown in FIG. 5, it should be
noted that one or more of the semiconductor chips may also be
mounted to the back surface of the module substrate. That is, the
semiconductor chips may be mounted to one side or both sides of the
module substrate, and the number of mounted semiconductor chips is
not limited only to the example of FIG. 5. In addition, the
material and structure of the module substrate are not limited to
those of FIG. 5, and the module substrate may also be formed of
other materials or structures.
[0063] FIG. 6 is a block diagram illustrating a semiconductor
system according to the present invention.
[0064] Referring to FIG. 6, a semiconductor system includes at
least one semiconductor module, including a plurality of
semiconductor chips, and a controller for providing a bidirectional
interface between each semiconductor module and an external system
(not shown) to control the operations of the semiconductor modules.
The controller may be identical or similar in function to a
controller for controlling a plurality of semiconductor modules for
use in a general data processing system, and as such a detailed
description thereof will herein be omitted for convenience of
description. In one embodiment, the semiconductor module may be,
for example, a semiconductor module shown in FIG. 5.
[0065] FIG. 7 is a block diagram illustrating an electronic unit
and an electronic system according to embodiments of the present
invention.
[0066] Referring to the left side of FIG. 7, the electronic unit
according to the present invention includes an electronic unit and
a processor electrically coupled to the electronic unit. In one
embodiment, the semiconductor system of FIG. 6 is identical to that
of FIG. 7. In one embodiment, the processor may include a Central
Processing Unit (CPU), a Micro Processor Unit (MPU), a Micro
Controller Unit (MCU), a Graphics Processing Unit (GPU), a Digital
Signal Processor (DSP), or a combination thereof.
[0067] In one embodiment, the CPU or MPU is configured in the form
of a combination of an Arithmetic Logic Unit (ALU) serving as
arithmetic and logical operation unit and a Control Unit (CU) for
controlling each unit by reading and interpreting a command.
Preferably, when the processor is a CPU or MPU, the electronic unit
may include a computer device or a mobile device. In addition, the
GPU, serving as a CPU for graphics, is used to calculate numbers
having decimal points, and corresponds to a process for drawing
graphic data as a real-time image. Preferably, when the processor
is a GPU, the electronic unit may include a graphic device. In
addition, a DSP is a processor that converts an analog signal
(e.g., voice signal) into a digital signal at high speed, uses the
calculated result, re-converts the digital signal into the analog
signal, and uses the re-converted result. The DSP mainly calculates
a digital value. When the processor is a DSP, the electronic unit
may preferably include a sound and imaging device.
[0068] The processor may include an Accelerate Processor Unit
(ACU), and may be configured in the form of a CPU integrated into
the GPU to serve as a graphic card.
[0069] Referring to the right side of FIG. 7, the electronic system
may include one or more interfaces electrically coupled to the
electronic unit. In one embodiment, the electronic unit is
identical to that of FIG. 7. In one embodiment, the interface may
include a monitor, a keyboard, a printer, a pointing device
(mouse), a USB, a switch, a card reader, a keypad, a dispenser, a
phone, a display, or speaker. However, it should be noted that the
scope of the interface is not limited thereto and is also
applicable to other examples.
[0070] As is apparent from the above description, a method for
forming the semiconductor device according to the embodiments of
the present invention has a number of advantages. In the
semiconductor device, a void is formed between metal lines of a
peripheral region to minimize parasitic capacitive coupling between
the metal lines, resulting in improvement of the operation
characteristics of the semiconductor device, for example, a sense
amplifier, a sub word line, etc., having a highly-integrated
peripheral region.
[0071] As is apparent from the above description, according to the
semiconductor device and a method for manufacturing the same, a
line-type buried gate is formed by burying a non-operating gate
(isolation gate) with a polysilicon material to reduce a work
function. In addition, a Gate Induced Drain Leakage (GIDL) caused
by the non-operating gate is reduced, resulting in improvement of
refresh characteristics of the semiconductor device.
[0072] The above embodiments of the present invention are
illustrative and not limitative. Various alternatives and
equivalents are possible. The invention is not limited by the type
of deposition, etching, polishing, and patterning steps described
herein. Nor is the invention limited to any specific type of
semiconductor device. For example, the present invention may be
implemented in a dynamic random access memory (DRAM) device or non
volatile memory device. Other additions, subtractions, or
modifications are obvious in view of the present disclosure and are
intended to fall within the scope of the appended claims.
* * * * *