U.S. patent application number 14/324945 was filed with the patent office on 2015-01-01 for high dielectric constant transition metal oxide materials.
The applicant listed for this patent is Micron Technology, Inc.. Invention is credited to Jiutao Li, Shuang Meng.
Application Number | 20150001673 14/324945 |
Document ID | / |
Family ID | 35996827 |
Filed Date | 2015-01-01 |
United States Patent
Application |
20150001673 |
Kind Code |
A1 |
Li; Jiutao ; et al. |
January 1, 2015 |
HIGH DIELECTRIC CONSTANT TRANSITION METAL OXIDE MATERIALS
Abstract
A transition metal oxide dielectric material is doped with a
non-metal in order to enhance the electrical properties of the
metal oxide. In a preferred embodiment, a transition metal oxide is
deposited over a bottom electrode and implanted with a dopant. In a
preferred embodiment, the metal oxide is hafnium oxide or zirconium
oxide and the dopant is nitrogen. The dopant can convert the
crystal structure of the hafnium oxide or zirconium oxide to a
tetragonal structure and increase the dielectric constant of the
metal oxide.
Inventors: |
Li; Jiutao; (Boise, ID)
; Meng; Shuang; (Boise, ID) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Micron Technology, Inc. |
Boise |
ID |
US |
|
|
Family ID: |
35996827 |
Appl. No.: |
14/324945 |
Filed: |
July 7, 2014 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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12776209 |
May 7, 2010 |
8791519 |
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14324945 |
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11499479 |
Aug 3, 2006 |
7723767 |
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12776209 |
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10940803 |
Aug 31, 2004 |
7172947 |
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11499479 |
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Current U.S.
Class: |
257/532 ; 501/1;
501/134 |
Current CPC
Class: |
H01L 21/31155 20130101;
C04B 35/48 20130101; H01L 28/40 20130101; H01L 21/02332 20130101;
H01L 21/02181 20130101; H01L 21/02189 20130101; H01L 21/31691
20130101; H01L 21/3143 20130101 |
Class at
Publication: |
257/532 ; 501/1;
501/134 |
International
Class: |
C04B 35/48 20060101
C04B035/48; H01L 49/02 20060101 H01L049/02 |
Claims
1.-59. (canceled)
60. A dielectric material for an integrated circuit consisting
essentially of a transition metal oxide layer with a non-metal
dopant in a tetragonal crystal structure, wherein the dielectric
material has a dielectric constant at least 30% higher than the
transition metal oxide without the non-metal dopant, wherein the
metal in the transition metal oxide consists essentially of hafnium
or zirconium.
61. The dielectric material of claim 60, wherein the dielectric
material comprises between about 1 atomic % and 20 atomic % of the
non-metal dopant.
62. The dielectric material of claim 60, wherein the dielectric
material comprises between about 3 atomic % and 10 atomic % of the
non-metal dopant.
63. The dielectric material of claim 60, wherein the transition
metal oxide is hafnium oxide.
64. The dielectric material of claim 60, wherein the transition
metal oxide is zirconium oxide.
65. The dielectric material of claim 60, wherein the dielectric
constant is at least 40% higher than the transition metal oxide
without the non-metal dopant.
66. The dielectric material of claim 60, wherein the dielectric
constant is greater than 32.
67. The dielectric material of claim 65, wherein the dielectric
constant is greater than 37.
68. The dielectric material of claim 60, wherein the dielectric
material has a thickness of between about 30 .ANG. and 200
.ANG.
69. A capacitor for an integrated circuit comprising: a bottom
electrode over a substrate; a dielectric layer overlying the bottom
electrode, the dielectric layer consisting essentially of a
transition metal oxide layer with a non-metal dopant in a
tetragonal crystal structure, wherein the dielectric material has a
dielectric constant at least 30% higher than the transition metal
oxide without the non-metal dopant, wherein the metal in the
transition metal oxide consists essentially of hafnium or
zirconium; and an upper electrode extending over the dielectric
layer.
70. The capacitor of claim 69, wherein the non-metal dopant
comprises nitrogen.
71. The capacitor of claim 69, wherein the dielectric material
comprises between about 1 atomic % and 20 atomic % of the non-metal
dopant.
72. The capacitor of claim 69, wherein the transition metal oxide
is hafnium oxide.
73. The capacitor of claim 69, wherein the transition metal oxide
is zirconium oxide.
74. An integrated circuit comprising: a plurality of conductive
bottom electrodes; a dielectric layer extending over each bottom
electrode, the dielectric layer consisting essentially of a
transition metal oxide layer with a non-metal dopant in a
tetragonal crystal structure, wherein the dielectric material has a
dielectric constant greater than 25, wherein the metal in the
transition metal oxide consists essentially of hafnium or
zirconium; and an upper electrode extending over the dielectric
layer.
75. The integrated circuit of claim 74, wherein the non-metal
dopant comprises nitrogen.
76. The integrated circuit of claim 74, wherein the dielectric
material comprises between about 1 atomic % and 20 atomic %
non-metal dopant.
77. The integrated circuit of claim 74, wherein the transition
metal oxide is hafnium oxide.
78. The integrated circuit of claim 74, wherein the transition
metal oxide is zirconium oxide.
79. The integrated circuit of claim 74, wherein the dielectric
constant is greater than 32.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is a continuation of U.S. patent
application Ser. No. 12/776,209, filed May 7, 2010, entitled "HIGH
DIELECTRIC CONSTANT TRANSITION METAL OXIDE MATERIALS," which is a
continuation of U.S. patent application Ser. No. 11/499,479, filed
Aug. 3, 2006, entitled "HIGH DIELECTRIC CONSTANT TRANSITION METAL
OXIDE MATERIALS," which issued as U.S. Pat. No. 7,723,767 on May
25, 2010; which is a continuation of U.S. patent application Ser.
No. 10/940,803, filed Aug. 31, 2004, entitled "HIGH DIELECTRIC
CONSTANT TRANSITION METAL OXIDE MATERIALS," which issued as U.S.
Pat. No. 7,172,947 on Feb. 6, 2007. Each of which are entirely
incorporated by reference herein.
FIELD OF THE INVENTION
[0002] The present invention relates generally to the field of
semiconductor fabrication and more specifically to the field of
high dielectric constant materials.
BACKGROUND OF THE INVENTION
[0003] Since the introduction of the digital computer, electronic
storage devices have been a vital resource for the retention of
data. Conventional semiconductor electronic storage devices
typically incorporate capacitor and transistor structures, such as
Dynamic Random Access Memory (DRAM), which temporarily store data
based on the charged state of the capacitor structure. In general,
this type of semiconductor Random Access Memory (RAM) often
requires densely packed capacitor structures that are easily
accessible for electrical interconnection. Many of these capacitor
structures are fabricated with layers of material including
semiconductor, dielectric, and metal. DRAM typically uses a cell
structure based on a capacitor and a transistor.
[0004] Integrated circuit manufacturers increasingly face
difficulties with scaling. The area of the chip ("real estate")
provided for capacitors in DRAM cells is rapidly shrinking. One way
to attain smaller capacitor sizes and maintain storage capacity is
to make the dielectric constant, or the K value, of the selected
dielectric material very high. Metal oxides, especially transition
metals, are commonly contemplated for high capacity DRAMs. One
example, tantalum oxide (Ta.sub.2O.sub.5) has a K-value of
approximately 25, and is a preferred dielectric material for DRAM
cell capacitors for modern DRAM capacitors. Hafnium oxide
(HfO.sub.2) is also used as a capacitor dielectric, but the K value
is approximately 20. These K-values may not be sufficient as DRAM
memory cell capacitors shrink. Barium strontium titanate
(Ba.sub.0.5Sr.sub.0.5TiO.sub.3), or BST, has a dielectric constant
of approximately 300, but BST is difficult to integrate into an
integrated circuit. For these reasons, additional dielectric
constant materials are needed for capacitors.
SUMMARY OF THE INVENTION
[0005] In one aspect of the invention, a method of forming a high k
material is disclosed. The method comprises implanting nitrogen
into a high dielectric constant transition metal oxide
material.
[0006] In another aspect of the invention, a method of forming a
capacitor dielectric is provided. The method comprises forming a
transition metal oxide layer with a predominantly monoclinic
crystal structure over a capacitor electrode. The transition metal
oxide layer is doped to convert the predominantly monoclinic
crystal structure into a predominantly tetragonal crystal
structure.
[0007] A method of forming a capacitor on an integrated circuit is
disclosed in another aspect of the invention. The method comprises
forming a first capacitor electrode and depositing a high
dielectric constant material over the first capacitor electrode.
The high dielectric constant material is implanted with nitrogen to
form a capacitor dielectric that comprises between about 1 atomic %
and 20 atomic % nitrogen. The method further comprises forming a
second capacitor electrode over the capacitor dielectric.
[0008] In another aspect, a capacitor dielectric material for an
integrated circuit is disclosed. The capacitor dielectric comprises
a nitrogen doped transition metal oxide layer with a tetragonal
crystal structure, wherein the capacitor dielectric material has a
dielectric constant of greater than 32.
[0009] In another aspect of the invention, a high dielectric
constant material for an integrated circuit is disclosed. The
material comprises nitrogen-doped hafnium oxide with a tetragonal
structure.
[0010] An integrated circuit with a capacitor array is disclosed in
another aspect of the invention. The array comprises a plurality of
conductive bottom electrodes. A dielectric layer extends over each
bottom electrode. The dielectric layer comprises a transition metal
oxide with a non-metal dopant and has a dielectric constant at
least 30% higher than the transition metal oxide without the
dopant. A conductive upper electrode overlies over each dielectric
layer
[0011] In another aspect, a capacitor for an integrated circuit is
disclosed. The capacitor comprises a bottom electrode over a
substrate. A dielectric layer overlies the bottom electrode. The
dielectric layer comprises a group IVB metal oxide and a non-metal
dopant in tetragonal crystal structure. An upper electrode extends
over the dielectric layer.
BRIEF DESCRIPTION OF THE DRAWINGS
[0012] FIG. 1 is a schematic cross section of a bottom electrode
layer over a substrate.
[0013] FIG. 2 illustrates the bottom electrode layer of FIG. 1
masked to form an unconnected electrode.
[0014] FIG. 3 illustrates the bottom electrode of FIG. 2 after
etching to isolate and deposition of a metal oxide layer, and shows
implantation of the metal oxide layer.
[0015] FIG. 4 illustrates a doped metal oxide layer over the bottom
electrode of FIG. 3.
[0016] FIG. 5 illustrates a top electrode over the structure of
FIG. 4.
[0017] FIG. 6 schematically illustrates an array of capacitors
according to an embodiment of the invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
[0018] In a preferred embodiment, a transition metal oxide is doped
with ions in order to increase the dielectric constant (K) of the
metal oxide. Preferably, the dopant is provided via ion
implantation. Implantation alters the crystal structure of the
dielectric material and enhances the insulating properties.
Preferably, a non-metal is implanted into a transition metal oxide
dielectric layer, preferably an early transition metal oxide layer.
In one preferred embodiment, nitrogen ions are implanted into
hafnium oxide. The crystal structure of the hafnium oxide material
can be changed from a monoclinic structure to a tetragonal
structure using nitrogen ion implantation.
[0019] Ion implantation is a materials engineering process by which
ions of a source material can be implanted into a target solid
material in order to change the physical properties of the target
material. When performing ion implantation, atoms or molecules of
the source material are ionized and accelerated in an electric
field. The ions collide with the target material and travel until
their motion is slowed to a stop.
[0020] A wide variety of combinations of target material and
implanted ions is possible. The dose of the implanted ions can vary
between 10.sup.11 and 10.sup.18 cm.sup.-2. Usually, the
acceleration energy lies between several keV and several hundred
keV, but some equipment allows energies up to several MeV. The
depth of the implanted ions in the substrate depends on the mass of
the implanted ions, their energy, the mass of the atoms of the
target material, crystal structure and the direction of incidence.
As an example, the mean range of 100 keV phosphorus ions in silicon
is about 150 nm.
[0021] Implantation offers several advantages over other processes
to introduce nitrogen. First, implantation is generally a short
process that is easily repeatedly reproduced. Unlike thermal
nitridation (e.g. by ammonia anneal), implantation employs
relatively low temperatures. Also, previous nitrogen-doped hafnium
oxide layers had only somewhat increased dielectric constants,
which were typically below 25. Implantation is also especially
useful for thin layers, such as capacitor dielectric layers. The
ability to configure and control the depth and concentration of the
dopants within the target material is also helpful to control
dopant distribution.
Capacitor Embodiment
[0022] In a preferred embodiment, nitrogen is implanted in a
transition metal oxide in order to increase the dielectric
constant. The crystal structure of the dielectric, which affects
the dielectric constant, can be altered by the implantation. Some
layers with particular crystal structures can be difficult to form
in the context of an integrated circuit. For example, it is very
difficult to deposit HfO.sub.2 in its tetragonal crystal structure.
However, by doping the layer, the monoclinic structure of HfO.sub.2
can be altered to form a predominantly tetragonal structure. A
table of transition metal oxides and other capacitor dielectrics
with their dielectric constants and possible crystal structures
appears below.
TABLE-US-00001 TABLE I Properties of Dielectric Materials:
Dielectric Band gap Material constant Energy (eV) Possible crystal
structures SiO.sub.2 3.9 8.9 Amorphous Si.sub.3N.sub.4 7.5 1
Amorphous Al.sub.2O.sub.3 9 8.7 Amorphous Y.sub.2O.sub.3 15 5.6
Cubic La.sub.2O.sub.3 30 4.3 Hexagonal, cubic Ta.sub.2O.sub.5 26
4.5 Orthorhombic TiO.sub.2 80 3.5 Tetragonal (rutile, anatase)
HfO.sub.2 25 5.7 Monoclinic, tetragonal, cubic ZrO.sub.2 25 7.8
Monoclinic, tetragonal, cubic
[0023] In order to increase capacitance per unit area, a capacitor
dielectric preferably has a constant of greater than silicon oxide.
High dielectric constant capacitor dielectrics, as used herein,
have a dielectric constant greater than aluminum oxide (K=9).
Transition metal oxides are particularly suited to use as capacitor
dielectric because, among other reasons, of the wide range of
deposition options available, such as chemical vapor deposition
(CVD) and atomic layer deposition (ALD). Individual metal oxides
have particularly promising properties. For example, hafnium oxide
combines a high dielectric constant with excellent thermal
stability and high band gap.
[0024] In an embodiment illustrated in FIG. 1, a bottom, or lower,
electrode 20 is formed on a substrate that includes a thick
insulating layer 10, which insulates devices beneath the bottom
electrode 20. The bottom electrode 20 serves as the storage
electrode. A plug 25, such as polysilicon or tungsten, connects
bottom electrode 20 to underlying devices, such as memory cell
transistors. Many conductive materials can be used as the bottom
electrode 20, including titanium nitride, polysilicon, and metals.
Skilled artisans will appreciate that the bottom electrode can be
deposited by any of several deposition processes. The material of
the bottom electrode 20 is preferably selected to resist oxidation
and oxygen diffusion during capacitor dielectric processing.
Examples of such materials include conductive barrier materials,
such as tantalum nitride (TaN), titanium nitride (TiN), and
tungsten nitride (WN).
[0025] FIG. 2 illustrates forming a mask 30 over the bottom
electrode 20. In a preferred embodiment, a photoresist layer is
formed, patterned, and developed over the bottom electrode 30.
However, other masking processes, such as hard masking can also be
used. Once the mask 30 is formed, the unmasked portions of the
bottom electrode layer 20 are removed to form a properly shaped
bottom electrode 20 as seen in FIG. 3. Other, more complex, shapes
can be used for the bottom electrode, including containers, fins,
rugged surfaces, etc., to further increase capacitance.
[0026] As illustrated in FIG. 3, a metal oxide layer 40 is
deposited over the bottom electrode 20. In a preferred embodiment,
the metal oxide layer 40 is a transition metal oxide, more
preferably a group IVB metal oxide. Most preferably the metal oxide
layer 40 is hafnium oxide or zirconium oxide. Hafnium oxide
(HfO.sub.2) or zirconium oxide (ZrO.sub.2) can be deposited by a
CVD or an ALD process. Preferably the metal oxide layer 40 has a
thickness of between about 30 .ANG. and 200 .ANG., more preferably
between about 70 .ANG. and 120 .ANG.. In a preferred embodiment, a
hafnium oxide metal oxide layer 40 is deposited over the bottom
electrode 20 in a CVD chamber using a hafnium precursor selected
from the group consisting of tetrakis (ethylmethylamido)hafnium
(Hf(NEtMe).sub.4), tetrakis(dimethylamido)hafnium
([(CH.sub.3).sub.2N].sub.4Hf), and hafnium chloride (HfCl.sub.4).
In another preferred embodiment, a zirconium oxide metal oxide
layer 40 is deposited over the bottom electrode 20 in a CVD chamber
using a zirconium precursor selected from the group consisting of
tetrakis (ethylmethylamido)zirconium (Zr(NEtMe).sub.4),
tetrakis(dimethylamido)zirconium ([(CH.sub.3).sub.2N].sub.4Zr,),
and zirconium chloride (ZrCl.sub.4). Preferably, the temperature of
the deposition process is between 275.degree. C. and 375.degree.
C., more preferably between about 300.degree. C. and 350.degree. C.
Preferably, the pressure for the deposition process is greater than
1 Torr. The hafnium oxide or zirconium oxide metal oxide layer 40
generally has a monoclinic crystal structure as deposited, as is
typically the case of CVD-deposited films of these materials.
[0027] As illustrated in FIG. 3, ions 50, preferably nitrogen ions,
are implanted into the metal oxide layer 40. Neutral elements, such
as argon and neon may also be implanted. Preferably, using ion-beam
implantation, a very low energy is used to accelerate the ions into
the metal oxide layer 40 so that the quantity of ions that
infiltrate the bottom electrode 20 can be minimal. However, the
exact energy depends on the thickness of the metal oxide layer 40.
Additionally, if the bottom electrode 20 includes a metal nitride,
such as TiN, infiltration of the bottom electrode 20 does not
substantially alter the properties of the electrode 20. In a
preferred embodiment, the energy level is just sufficient for ions
50 to reach the interface between the metal oxide layer 40 and the
bottom electrode layer 20 and to attain even ion distribution
throughout the depth of the metal oxide layer 40. For example, when
the metal oxide layer 40 has a thickness of 90 .ANG., the energy is
preferably between about 1.2 KeV and 1.8 KeV, more preferably
between about 1.3 KeV and 1.7 KeV. Preferably, the crystal
structure of hafnium oxide or zirconium oxide is converted from a
predominantly monoclinic structure to a predominantly tetragonal
structure during this implantation step. A skilled practitioner
will be able to determine a proper energy setting in order to
satisfy the aim of evenly distributing the ions throughout the
metal oxide layer 40 without infiltrating the bottom electrode
layer 20.
[0028] As noted, the implant dose is also dependent upon the
thickness of the metal oxide layer 40. Preferably, the metal oxide
layer 40 after implantation incorporates between about 1 atomic %
and 20 atomic % of the dopant, more preferably between about 3
atomic % and 10 atomic %. To achieve these concentrations at
approximately 90 .ANG., a preferred nitrogen ion dose is between
about 1*10.sup.15 cm.sup.-2 and 2*10.sup.16 cm.sup.-2, more
preferably between about 3*10.sup.15 cm.sup.-2 and 1*10.sup.16
cm.sup.-2. For neutral materials, such as argon, similar doses can
be used.
[0029] In addition to traditional beam implantation, ion doping by
pulsed laser ablation and deposition (PLAD) or plasma doping can
also be used to dope the dielectric material. These techniques are
readily adaptable to the materials described herein by the skilled
practitioner. In particular, PLAD provides a very uniform doping
profile in the metal oxide layer. PLAD is particularly useful in
the use of doping a trench capacitor dielectric or a container
capacitor, whereby interior sidewalls are doped with nitrogen ions.
Conditions to achieve conversion from a predominantly monoclinic
crystal structure to a predominantly tetragonal structure can be
determined by the skilled artisan using routine experimentation in
view of the disclosure herein.
[0030] Referring to FIG. 4, in a preferred embodiment, the wafer is
annealed after a high-K resultant metal oxynitride layer 60 has
been implanted. A preferred anneal process is conducted for between
about one and ten minutes in an inert environment in a single wafer
chamber, preferably a rapid thermal processing (RTP) chamber. More
preferably, the anneal process is conducted in argon. Preferably,
the temperature in the chamber is between about 400.degree. C. and
900.degree. C., more preferably between about 500.degree. C. and
700.degree. C.
[0031] The implantation has several benefits for the dielectric
layer. First, the dielectric constant substantially increases post
anneal. For hafnium oxide, the dielectric constant preferably rises
from about 25 to over 32, more preferably greater than 35, most
preferably greater than 37. The dielectric constant of the
dielectric layer 60 thus preferably increases by more than 30%,
more preferably by at least 40%, most preferably by at least 45%.
The capacitance for a capacitor incorporating such material
similarly increases. In one example, the capacitance is increased
from about 5.9*10.sup.-7 F to 9*10.sup.-7 F. The implantation into
the transition metal oxide also decreases the leakage current,
preferably at least a 50% reduction, more preferably at least a 75%
reduction, most preferably at least a 85% reduction. For example,
implantation of nitrogen into hafnium oxide reduces the leakage
current by approximately an order of magnitude. The implantation of
ions, particularly nitrogen, into the dielectric layer 60 can also
improve the electrical properties of the interface between the
dielectric layer 60 and the lower electrode 20.
[0032] Referring to FIG. 5, once the high-K metal oxynitride
capacitor dielectric layer 60 has been formed, a conductive upper
electrode 70 is deposited. Preferably a metallic upper electrode 70
is formed. Metals such as tungsten and platinum can be used as the
upper electrode 70.
[0033] The upper electrode could be a common electrode for use as a
reference electrode for the whole array, or the upper electrode 70
could be patterned to form an individual top electrode. The
capacitor can then be incorporated into a memory cell or other
integrated circuit device, which in turn is employed in a larger
computer system.
Structure
[0034] The increased dielectric constant material can be used for
many types of capacitors, especially those that require thin
dielectric layers. In a preferred embodiment illustrated in FIG. 5,
a capacitor is formed with a bottom electrode 20 over a substrate,
illustrated as including a thick insulating layer 10 and a plug 25.
Preferably, the bottom electrode 20 includes titanium nitride. A
high-K dielectric constant material, preferably hafnium oxide or
zirconium oxide, that includes a dopant is used as the capacitor
dielectric 60. Preferably, the capacitor dielectric 60 has nitrogen
implanted into the crystal structure. In a preferred embodiment,
the capacitor dielectric 60 has a predominantly tetragonal crystal
structure, more preferably the capacitor dielectric 60 has a
completely tetragonal structure. The dielectric layer preferably
has between 1 atomic % and 20 atomic % nitrogen, more preferably
between about 3 atomic % and 10 atomic %. Small thickness changes
have also been found at the corners of patterned capacitors,
resulting in slight rounding of sharp corners. This thickness
change is possibly due to a sputter etch effect from ion
implantation.
[0035] The capacitors can be used to form a capacitor array that
can be used in a memory device, such as a DRAM. FIG. 6
schematically illustrates such an array. An actual memory array has
a large number of capacitors in a similar arrangement. Further
connections can be made to the capacitor through the bottom
electrode to underlying transistors and through the upper
electrodes 70 to logic circuitry for sensing capacitor storage
state. While the upper electrodes are shown as a plurality of
separate electrodes in FIG. 6, the upper electrode can also be a
common electrode to the entire array. In a preferred embodiment the
capacitor array is used to form memory cells for a DRAM device by
connecting the capacitor to a transistor.
[0036] It will be appreciated by those skilled in the art that
various omissions, additions and modifications may be made to the
methods and structures described above without departing from the
scope of the invention. All such modifications and changes are
intended to fall within the scope of the invention, as defined by
the appended claims.
* * * * *