U.S. patent application number 14/487201 was filed with the patent office on 2015-01-01 for gate constructions of recessed access devices and methods of forming gate constructions of recessed access devices.
The applicant listed for this patent is Micron Technology, Inc.. Invention is credited to Jaydip Guha, Suraj J. Mathew.
Application Number | 20150001605 14/487201 |
Document ID | / |
Family ID | 45438906 |
Filed Date | 2015-01-01 |
United States Patent
Application |
20150001605 |
Kind Code |
A1 |
Mathew; Suraj J. ; et
al. |
January 1, 2015 |
Gate Constructions Of Recessed Access Devices And Methods Of
Forming Gate Constructions Of Recessed Access Devices
Abstract
A method of forming a gate construction of a recessed access
device includes forming a pair of sidewall spacers laterally over
opposing sidewalls of a gate dielectric and elevationally over
first conductive gate material. The gate dielectric, the first
conductive gate material, and the sidewall spacers are received
within a trench formed in semiconductive material. Second
conductive gate material is deposited within the semiconductive
material trench between the pair of sidewall spacers in electrical
connection with the first conductive gate material. Other
implementations are disclosed, including recessed access device
gate constructions independent of method of manufacture.
Inventors: |
Mathew; Suraj J.; (Boise,
ID) ; Guha; Jaydip; (Boise, ID) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Micron Technology, Inc. |
Boise |
ID |
US |
|
|
Family ID: |
45438906 |
Appl. No.: |
14/487201 |
Filed: |
September 16, 2014 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
12833071 |
Jul 9, 2010 |
8859367 |
|
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14487201 |
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Current U.S.
Class: |
257/314 ;
438/589 |
Current CPC
Class: |
H01L 29/4236 20130101;
H01L 21/28008 20130101; H01L 27/10894 20130101; H01L 29/66621
20130101; H01L 27/10876 20130101; H01L 29/78 20130101; H01L
29/66553 20130101; H01L 21/28114 20130101; H01L 29/42364 20130101;
H01L 29/42376 20130101 |
Class at
Publication: |
257/314 ;
438/589 |
International
Class: |
H01L 29/423 20060101
H01L029/423; H01L 21/28 20060101 H01L021/28 |
Claims
1-21. (canceled)
22. A method of forming recessed access device gate constructions
within a memory array area and peripheral circuitry gate
constructions in a peripheral circuitry area, comprising: forming
peripheral circuitry gate dielectric and conductive peripheral
circuitry gate material over a peripheral circuitry area and over a
memory array area of a semiconductor substrate; in the memory array
area, etching recessed access device trenches through the
conductive peripheral circuitry gate material and through the
peripheral circuitry gate dielectric to within semiconductive
material under the peripheral circuitry gate dielectric; forming
memory array gate dielectric over sidewalls of the semiconductive
material within the trenches in the memory array area; depositing
first conductive gate material over the memory array gate
dielectric within the semiconductive material trenches in the
memory array area; in the memory array area, etching the first
conductive gate material to recess it within the trenches to below
elevationally outermost surfaces of the semiconductive material
adjacent the trenches and exposing memory array gate dielectric
within the trenches; in the memory array area, forming etched
sidewall spacers that are above and below the elevationally
outermost surfaces of the semiconductive material adjacent the
trenches; depositing second conductive gate material within the
trenches between the etched spacers and in electrical connection
with the first conductive gate material within the memory array
area and over and in electrical connection with the conductive
peripheral circuitry gate material in the peripheral circuitry
area; and in a single masking step, removing the second conductive
gate material within the memory array area to form recessed access
device gate constructions within the memory array area and removing
the second conductive gate material and the conductive peripheral
circuitry gate material within the peripheral circuitry area to
form peripheral circuitry gate constructions.
23. The method of claim 0 comprising forming an oxidation barrier
over the conductive peripheral gate material in the memory array
area and in the peripheral circuitry area prior to etching the
trenches.
24. The method of claim 23 wherein the oxidation barrier comprises
Si.sub.3N.sub.4.
25. The method of claim 23 comprising removing the oxidation
barrier after the gate dielectric is formed.
26. The method of claim 25 comprising removing the oxidation
barrier before forming the etched sidewall spacers.
27. The method of claim 0 comprising: depositing the second
conductive gate material elevationally over the etched spacers; and
patterning the second conductive gate material such that the
respective conductive portions of the gate constructions are wider
in cross section above and below the etched spacers than
there-between.
28. A recessed access device gate construction comprising: a trench
within semiconductive material, the trench comprising
semiconductive material sidewalls and a semiconductive material
base extending between the semiconductive material sidewalls; a
gate dielectric lining over the semiconductive material trench
sidewalls and the semiconductive material trench base; blocks
received within an upper portion of the trench which project
laterally into the trench, the blocks being laterally thicker than
thickness of the gate dielectric lining received over the trench
sidewalls and trench base; and conductive gate material received
within the trench between, below, and above the blocks.
29. The gate construction of claim 28 wherein the conductive
portion of the gate construction is wider in cross section above
and below the blocks than there-between.
30. The gate construction of claim 27 wherein the blocks protrude
above the semiconductive material in which the trench is
received.
31. The gate construction of claim 30 wherein the conductive
portion of the gate construction is wider in cross section above
and below the blocks than there-between.
32. The gate construction of claim 28 wherein the blocks are wider
at their bottoms than at their tops.
33. The gate construction of claim 28 wherein the blocks have
lateral sidewall surfaces, the conductive gate material that is
over the blocks having lateral sidewall surfaces that are laterally
coincident with those of the blocks.
34. The gate construction of claim 33 wherein the blocks protrude
above the semiconductive material in which the trench is
received.
35. The method of claim 22 wherein the sidewall spacers are formed
by anisotropic etching.
36. The method of claim 22 wherein the first and second conductive
gate materials are of the same composition.
37. The method of claim 22 wherein the second conductive gate
material is deposited into physical contact with the first
conductive gate material that is within the trench.
Description
RELATED PATENT DATA
[0001] This patent resulted from a divisional application of U.S.
patent application Ser. No. 12/833,071, filed Jul. 9, 2010,
entitled "Gate Constructions Of Recessed Access Devices And Methods
Of Forming Gate Constructions Of Recessed Access Devices", naming
Suraj J. Mathew and Jaydip Guha as inventors, the disclosure of
which is incorporated by reference.
TECHNICAL FIELD
[0002] Embodiments disclosed herein pertain to gate constructions
of recessed access devices and to methods of forming gate
constructions of recessed access devices.
BACKGROUND
[0003] Embodiments of the invention were motivated in addressing
current leakage that occurs in recessed access devices. A recessed
access device is a field effect transistor having its gate
construction received within a trench formed in semiconductive
material. The gate construction includes a gate dielectric which
lines the trench and conductive gate material received within the
trench laterally inward of the gate dielectric. Source/drain
regions are formed within the semiconductive material on opposing
sides of the trench in outermost regions of the semiconductive
material. Application of suitable voltage to the conductive gate
material within the trench enables current to flow through the
semiconductive material between the source/drains along the trench
sidewalls and around the base of the trench.
[0004] Gate induced drain leakage (GIDL) is a negative attribute
associated with field effect transistors, and can be problematic
with recessed access devices, particularly at the elevationally
outermost regions of the source/drains adjacent the uppermost
portions of the trench.
BRIEF DESCRIPTION OF THE DRAWINGS
[0005] FIG. 1 is a diagrammatic sectional view of a substrate
fragment in process in accordance with an embodiment of the
invention.
[0006] FIG. 2 is a view of the FIG. 1 substrate at a processing
step subsequent to that shown by FIG. 1.
[0007] FIG. 3 is a view of the FIG. 2 substrate at a processing
step subsequent to that shown by FIG. 2.
[0008] FIG. 4 is a view of the FIG. 3 substrate at a processing
step subsequent to that shown by FIG. 3.
[0009] FIG. 5 is a view of the FIG. 4 substrate at a processing
step subsequent to that shown by FIG. 4.
[0010] FIG. 6 is a view of the FIG. 5 substrate at a processing
step subsequent to that shown by FIG. 5.
[0011] FIG. 7 is a view of the FIG. 6 substrate at a processing
step subsequent to that shown by FIG. 6.
[0012] FIG. 8 is a view of the FIG. 7 substrate at a processing
step subsequent to that shown by FIG. 7.
[0013] FIG. 9 is a view of the FIG. 8 substrate at a processing
step subsequent to that shown by FIG. 8.
[0014] FIG. 10 is a diagrammatic sectional view of a substrate
fragment in process in accordance with an embodiment of the
invention.
[0015] FIG. 11 is a view of the FIG. 10 substrate at a processing
step subsequent to that shown by FIG. 10.
[0016] FIG. 12 is a view of the FIG. 11 substrate at a processing
step subsequent to that shown by FIG. 11.
[0017] FIG. 13 is a view of the FIG. 12 substrate at a processing
step subsequent to that shown by FIG. 12.
[0018] FIG. 14 is a view of the FIG. 13 substrate at a processing
step subsequent to that shown by FIG. 13.
[0019] FIG. 15 is a view of the FIG. 14 substrate at a processing
step subsequent to that shown by FIG. 14.
[0020] FIG. 16 is a view of the FIG. 15 substrate at a processing
step subsequent to that shown by FIG. 15.
[0021] FIG. 17 is a view of the FIG. 16 substrate at a processing
step subsequent to that shown by FIG. 16.
DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS
[0022] Embodiments of the invention encompass methods of forming a
gate construction of a recessed access device. The discussion
initially proceeds with reference to FIGS. 1-9 of an example method
of forming recessed access device gate constructions within a
memory array area and forming peripheral circuitry gate
constructions in a peripheral circuitry area.
[0023] Referring to FIG. 1, a semiconductor substrate 10 includes a
memory array area 12 and a peripheral circuitry area 14. In the
context of this document, the term "semiconductor substrate" or
"semiconductive substrate" is defined to mean any construction
comprising semiconductive material, including, but not limited to,
bulk semiconductive materials such as a semiconductive wafer
(either alone or in assemblies comprising other materials thereon),
and semiconductive material layers (either alone or in assemblies
comprising other materials). The term "substrate" refers to any
supporting structure, including, but not limited to, the
semiconductive substrates described above. Substrate 10 may
comprise semiconductive material 16, for example monocrystalline
silicon having trench isolation regions 18 formed therein. Active
area of material 16 for device fabrication, for example field
effect transistors, is received between or surrounded by trench
isolation regions 18. Example trench isolation material is silicon
dioxide which may be lined with silicon nitride. A sacrificial
oxide 20 has been formed over substrate material 16/18, and
photoresist-comprising material 22 has been formed thereover.
[0024] Referring to FIG. 2, photoresist-comprising material 22 has
been patterned to form elongated trench openings therein. Material
22 has then been used as an etch mask in etching into material
20/16 in forming recessed access device trenches 24 within
semiconductive material 16 within memory array area 12. Such
trenches may also be formed in peripheral circuitry area 14 which,
however, is not germane to embodiments of the invention. Trench
openings (not shown) may also be formed through materials 22 and 20
into trench isolation 18. Trenches 24 would likely be elongated in
a longitudinal direction into and out of the plane of the page upon
which FIG. 2 lies. The respective recessed access device trenches
may be considered as having opposing semiconductive material
sidewalls 28 and a semiconductive material base 30 extending
there-between. The discussion proceeds with example fabrication of
dynamic random access memory (DRAM) circuitry, although any
circuitry may be fabricated. Further, the above-described
processing implies use of photoresist and photolithography,
although recessed access device trenches 24 may be formed by any
other existing or yet-to-be-developed process.
[0025] Referring to FIG. 3, oxide 20 (not shown) and
photoresist-comprising material 22 (not shown) have been removed
from the substrate. Thereafter, gate dielectric 26 has been formed
over semiconductive material sidewalls 28 within trenches 24 in
memory array area 12 and over semiconductive material 16 within
peripheral circuitry area 14. Such may be homogenous or
non-homogenous and comprise any suitable dielectric material, with
thermally grown silicon dioxide being an example. Further, such may
be subjected to plasma nitridation processing, or other processing,
during or after its deposition. Any suitable thickness may be used,
with from about 80 Angstroms to about 100 Angstroms being an
example.
[0026] First conductive gate material 32 has been deposited over
gate dielectric 26 within semiconductive material trenches 24 in
memory array area 12 and over gate dielectric 26 in peripheral
circuitry area 14. Material 32 may be deposited to physically
contact gate dielectric 26. Material 32 may be homogenous or
non-homogenous, and may comprise any one or combination of
elemental metals, alloys of elemental metals, conductive metal
compounds, and/or conductively doped semiconductive material.
Conductively doped polysilicon is one example. An example thickness
for first conductive gate material 32 is about half of an ultimate
desired thickness of the conductive portions of gate constructions
in the peripheral circuitry area where gate constructions are to be
there-fabricated. An example thickness range is from about 250
Angstroms to about 450 Angstroms, with about 350 Angstroms being a
specific example. In one embodiment, an etch barrier 34 may be
deposited over first conductive gate material 32 in memory array
area 12 and in peripheral circuitry area 14. An example material is
silicon nitride deposited to an example thickness of about 300
Angstroms. Such may be used to protect the outermost surface of
first conductive gate material 32 within peripheral circuitry area
14 during processing specific to memory array area 12. In one
embodiment, a photoresist-comprising material 36 may be formed over
etch barrier 34. Such may be homogenous or non-homogenous
comprising multiple different composition materials and/or
layers.
[0027] Referring to FIG. 4, photoresist-comprising material 36 has
been patterned to form a mask having openings there-through, with
such mask being used to etch trench openings 38 through first
conductive gate material 32 over recessed access device trenches 24
within memory array area 12. Trench openings 38 may be of the same
size and configuration of trench openings 24 which were formed
within material 16. Trench openings 38 may be considered as having
opposing sidewalls 35 of first conductive gate material 32.
Regardless, first conductive gate material 32 has been recessed
within trenches 24, for example by etching, to expose sidewalls of
elevationally outermost portions of gate dielectric 26 within
semiconductive material trenches 24 in memory array area 12. In one
embodiment, first conductive gate material 32 within respective
recessed access device trenches 24 has a planar elevationally
outermost (upper) surface 37 that spans completely across the
respective trench 24 between gate dielectric 26 elevationally
inward of an outermost surface 17 of semiconductive material 16
immediately adjacent the respective trenches 24. In one embodiment,
surface 37 of the first conductive gate material within the
respective trenches 24 is recessed from about 200 Angstroms to
about 500 Angstroms from surface 17. In one embodiment, surface 37
within the respective trenches 24 is recessed from about 200
Angstroms to about one-third of the depths of trenches 24 within
material 16 from surface 17.
[0028] Referring to FIG. 5, photoresist-comprising material 36 (not
shown) has been removed. Further in one example embodiment where an
etch barrier 34 (not shown) has been used, such has also been
removed from the substrate after trench openings 38 have been
etched. Subsequently, spacer material 40 has been deposited over
first conductive gate material 32, including within trench openings
38 over material 32 within recessed access device trenches 24. In
one embodiment, material 40 is dielectric. Material 40 may be
homogenous or non-homogenous, and regardless may be of the same
composition or different composition from that of gate dielectric
26.
[0029] Referring to FIG. 6, anisotropically etched sidewall spacers
42 have been formed from material 40. Such may be received
laterally over the opposing sidewalls of the exposed portions of
gate dielectric 26 that are within semiconductive material trenches
24. Such may also be received laterally over opposing sidewalls 35
of first conductive gate material 32 of trench openings 38. Spacers
42 may be formed to be wider at their bottoms/bases than at their
tops, for example as shown. Such describes and depicts but one
method of forming a pair of sidewall spacers laterally over
opposing sidewalls of a gate dielectric and elevationally over
first conductive gate material. Alternate etching or growth
techniques may be used. A pair of spacers may be interconnected
within one or both opposing ends of a trench, but regardless may be
considered as a pair of spacers in at least one straight line cross
section, for example as shown. Further, the spacers may or may not
be dielectric. Spacers 42 may be considered as having laterally
outermost sidewall surfaces 48 and laterally innermost sidewall
surfaces 49.
[0030] Referring to FIG. 7, second conductive gate material 46 has
been deposited within semiconductive material trenches 24 between
the respective pairs of sidewall spacers 42 and may physically
contact and be in electrical connection with first conductive gate
material 32 in memory array area 12. Second conductive gate
material 46 has also been formed over and may physically contact
and be in electrical connection with first conductive gate material
32 in peripheral circuitry area 14. Second conductive gate material
46 may be homogenous or non-homogenous, may or may not be of the
same composition as first gate material 32, and may be deposited to
any suitable thickness. In some embodiments, second conductive gate
material 46 may not be deposited into physical contact with first
conductive gate material 32. In one embodiment, second conductive
gate material 46 may be deposited above spacers 42. In other words,
embodiments of the invention contemplate second conductive material
46 not being deposited or remaining in a finished circuitry
construction with spacers 42. Additionally, other material (not
shown) may be deposited over second conductive gate material 46. As
an example, an insulator (not shown) such as silicon nitride may be
deposited over gate material 46 to be used in the fabrication of
insulative gate caps.
[0031] Referring to FIG. 8, and in a single masking step, second
conductive gate material 46 within memory array area 12 has been
etched or otherwise removed to form recessed access device gate
constructions 50 within memory array area 12. Similarly, first and
second conductive gate materials 32, 46 have been etched or
otherwise removed within peripheral circuitry area 14 to form
peripheral circuitry gate constructions 52. Such masking step may
comprise, by way of example, deposition and patterning of a
photosensitive material (not shown) to comprise masking blocks (not
shown) of the same lateral and longitudinal configuration of the
elevationally outermost portions of gate constructions 50 and 52.
Some or all of gate dielectric 26 may or may not (as shown) be
removed laterally outward of gate constructions 50 and/or gate
constructions 52. In one embodiment, the patterning of second
conductive gate material 46 forms the respective conductive
portions of gate constructions 50 to be wider in cross section
above and below dielectric spacers 42 than there-between. For
example, the conductive portion of a gate construction 50 in the
depicted example is encompassed by the combination of first
conductive gate material 32 and second conductive gate material 46.
Such conductive portion has a greater or wider upper lateral
expanse A above dielectric spacers 42 and a greater or wider
lateral expanse B below dielectric spacers 42 than every portion of
lateral expanse C between dielectric spacers 42. Regardless, in one
embodiment, the patterning may form second conductive gate material
46 to have laterally outermost sidewall surfaces 54 that are
laterally coincident with those surfaces 48 of dielectric spacers
42. Provision of dielectric spacers 42 results in an effective
widening of the gate dielectric region for the transistor at the
locations where the outermost surfaces of material 16 join or
define trenches 24. Such may reduce GIDL in circuit operation.
[0032] Processing may proceed subsequently in fabrication of
completed field effect transistor devices using recessed access
gate constructions 50 within memory array area 12 and gate
constructions 52 within peripheral circuitry area 14. For example
as shown in FIG. 9, suitable source/drain regions 54 have been
fabricated in memory array area 12 and peripheral circuitry area
14. In one example embodiment, two recessed access device
transistors in memory array area 12 are shown as comprising part of
DRAM circuitry. A center and shared source/drain region 54 of the
two transistors is shown connected schematically with a data/sense
line 58 (for example a bit line), while the laterally outer
source/drain regions 54 are shown connected schematically with a
respective capacitor 56, thus forming two memory cells of DRAM
circuitry.
[0033] Example alternate embodiments of a method of forming
recessed access device gate constructions within a memory array
area and peripheral circuitry gate constructions in a peripheral
circuitry area are next described with reference to FIGS. 10-17.
Like numerals from the above-described embodiments have been used
where appropriate, with some construction differences being
indicated with the suffix "a" or with different numerals.
[0034] Referring to FIG. 10, peripheral circuitry gate dielectric
60 and conductive peripheral circuitry gate material 62 have been
formed over peripheral circuitry area 14 and over memory array area
12 of semiconductor substrate 10a. Attributes of dielectric
material 60 may be as described above with respect to gate
dielectric 26. Example conductive peripheral circuitry gate
material 62 may be as described above with respect to first and
second conductive gate materials 32, 46. In one embodiment and as
shown, an oxidation barrier 64 may be formed over conductive
peripheral gate material 62 in memory array area 12 and in
peripheral circuitry area 14. An example material is silicon
nitride deposited to an example thickness of about 300
Angstroms.
[0035] Referring to FIG. 11, recessed access device trenches 24
have been etched to within semiconductive material 16 by etching
through material 64, 62 and 60. Such may be formed using
photolithographic or other method.
[0036] Referring to FIG. 12, memory array gate dielectric 26a has
been formed over sidewalls 28 of semiconductive material 16 within
trenches 24 in memory array area 12. Such may be formed by any
suitable method and have any of the attributes of dielectric 26
described above. If formed by oxidation and where conductive
peripheral circuitry gate material 62 comprises an oxidizable
material, such may also form laterally over sidewalls of such
material above semiconductive material trenches 24, as shown.
[0037] Referring to FIG. 13, first conductive gate material 32a has
been deposited over a memory array gate dielectric 26a within
semiconductive material trenches 24 in memory array area 12 and
over peripheral circuitry area 14. Such may have any one or more of
the attributes described above with respect to first conductive
gate material 32.
[0038] Referring to FIG. 14, first conductive gate material 32a has
been etched to recess it within trenches 24 to below surfaces 17 of
semiconductive material 16 adjacent trenches 24 within memory array
area 12. Further, opposing sidewalls of a portion of memory array
gate dielectric 26a within trenches 24 have been exposed. Any one
or more attributes as described above with respect to the
processing of FIG. 4 may be used in the processing of FIG. 14.
[0039] Referring to FIG. 15 an in one embodiment where an oxidation
barrier 64 (not shown) has been used, such may be removed from the
substrate. Subsequently, respective pairs of etched sidewall
spacers 42a have been formed within memory array area 12 from
deposited material 40. Such may be formed, for example, as
described above in connection with the processing of FIG. 7.
Regardless in FIG. 15, spacers 42a are shown as being received
laterally over the exposed portions of memory array gate dielectric
26a within trenches 24 below surfaces 17 of semiconductive material
16 adjacent trenches 24. Such are also received laterally over
opposing sidewalls of peripheral circuitry gate dielectric 60 above
surfaces 17 of semiconductive material 16. Further, spacers 42a are
also received laterally over opposing sidewalls of conductive
peripheral circuitry gate material 62 above surfaces 17 of
semiconductive material 16 adjacent trenches 24. In one embodiment
as shown where dielectric material 26a is also formed over
sidewalls of material 62, material 26a is received between spacers
42a and material 62.
[0040] Referring to FIG. 16, second conductive gate material 46 has
been deposited within trenches 24 between the respective pairs of
spacers 42a in electrical connection with first conductive gate
material 32a within memory array area 12. Such has also been
deposited over and in electrical connection with conductive
peripheral circuitry gate material 62 in peripheral circuitry area
14. Any one or more of the attributes described above may be used
or result.
[0041] Referring to FIG. 17, and in a single masking step, second
conductive gate material 46 within memory array area 12 has been
etched or otherwise removed to form recessed access device gate
constructions 50a within memory array area 12. Similarly, second
conductive gate material 46 and conductive peripheral circuitry
gate material 62 have been etched or otherwise removed within
peripheral circuitry area 14 to form peripheral circuitry gate
constructions 52a. Some or all of peripheral circuitry gate
dielectric 60 may (as shown) or may not be removed laterally
outward of gate constructions 50a and/or gate constructions 52a.
Any attribute and/or subsequent processing may occur or result as
described above, or otherwise.
[0042] In one embodiment of the invention, a method of forming a
gate construction of a recessed access device includes forming a
pair of sidewall spacers laterally over opposing sidewalls of a
gate dielectric and above first conductive gate material. The gate
dielectric, the first conductive gate material, and the spacers
over which such are formed are collectively received within a
trench formed in semiconductive material. Such spacers may or may
not project outwardly of the semiconductive material in which the
trench is formed. Further, other material may or may not be
received over the semiconductive material in which the trench is
formed. The above-described embodiments show spacers 42 and 42a as
projecting elevationally outward of a trench 24 in semiconductive
material 16. Alternately and by way of example, such spacers might
have uppermost surfaces which are elevationally coincident with
uppermost surfaces 17 of material 16 immediately adjacent a trench
24, or which are recessed within a trench 24 below such surfaces
17. However, greater reduction in GIDL may occur by having
dielectric spacers 42/42a project elevationally outward of material
16 as shown.
[0043] Regardless, second conductive gate material is deposited
within the semiconductive material trench between the pair of
sidewall spacers to be in electrical connection with the first
conductive gate material. One or more attributes may be as
described above with respect to composition, deposition, and any
subsequent patterning with respect to the first and second
conductive gate materials.
[0044] In one embodiment of the invention, a method of forming a
gate construction of a recessed access device comprises forming
gate dielectric and first conductive gate material within a trench
in semiconductive material. The first conductive gate material is
recessed, for example by etching, within the trench to have an
elevationally outermost (upper) surface that spans completely
across the trench between the gate dielectric. A pair of etched
sidewall spacers is formed within the trench laterally over
opposing sidewalls of the gate dielectric and over the first
conductive gate material. Second conductive gate material is
deposited within the trench between the pair of etched sidewall
spacers in electrical connection with the first conductive gate
material.
[0045] Embodiments of the invention also encompass recessed access
device gate constructions independent of method of fabrication. In
one embodiment, such a gate construction comprises a trench within
semiconductive material, with the trench comprising semiconductive
material sidewalls and a semiconductive material base extending
between the semiconductive material sidewalls. A gate dielectric
lining is received over the semiconductive material trench
sidewalls and the semiconductive material trench base. A pair of
laterally spaced and laterally opposed blocks is received within an
upper portion of the trench, and which project laterally into the
trench. The above-described sidewall spacers are example such
blocks. Regardless, the blocks are laterally thicker than thickness
of the gate dielectric lining that is received over the trench
sidewalls and the trench base. Conductive gate material is received
within the trench between and below the blocks, and extends
elevationally outward of the semiconductive material trench to
elevationally over the dielectric blocks.
[0046] In one embodiment, the conductive portion of the gate
construction is wider in cross section above and below the blocks
than there-between. Any one or other attributes of the
constructions as described above and/or shown in the drawings may
constitute an attribute of such a recessed access device gate
construction.
[0047] In compliance with the statute, the subject matter disclosed
herein has been described in language more or less specific as to
structural and methodical features. It is to be understood,
however, that the claims are not limited to the specific features
shown and described, since the means herein disclosed comprise
example embodiments. The claims are thus to be afforded full scope
as literally worded, and to be appropriately interpreted in
accordance with the doctrine of equivalents.
* * * * *