U.S. patent application number 14/297248 was filed with the patent office on 2014-12-11 for using compute shaders as front end for vertex shaders.
The applicant listed for this patent is Sony Computer Entertainment Inc.. Invention is credited to Mark Evan Cerny, Jason Scanlin, David Simpson.
Application Number | 20140362081 14/297248 |
Document ID | / |
Family ID | 52005082 |
Filed Date | 2014-12-11 |
United States Patent
Application |
20140362081 |
Kind Code |
A1 |
Cerny; Mark Evan ; et
al. |
December 11, 2014 |
USING COMPUTE SHADERS AS FRONT END FOR VERTEX SHADERS
Abstract
A set of graphics primitive information for a virtual object may
be processed with compute shader running on a graphics processing
unit (GPU) to generate a modified set of primitive information. The
modified set of primitive information may be passed to a vertex
shader running on the GPU. The vertex shader may perform vertex
shading on the modified set of primitive information. It is
emphasized that this abstract is provided to comply with the rules
requiring an abstract that will allow a searcher or other reader to
quickly ascertain the subject matter of the technical disclosure.
It is submitted with the understanding that it will not be used to
interpret or limit the scope or meaning of the claims.
Inventors: |
Cerny; Mark Evan; (Los
Angeles, CA) ; Simpson; David; (Los Angeles, CA)
; Scanlin; Jason; (Los Angeles, CA) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Sony Computer Entertainment Inc. |
Tokyo |
|
JP |
|
|
Family ID: |
52005082 |
Appl. No.: |
14/297248 |
Filed: |
June 5, 2014 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
61833229 |
Jun 10, 2013 |
|
|
|
Current U.S.
Class: |
345/426 |
Current CPC
Class: |
G06T 15/40 20130101;
G06T 15/005 20130101; G06T 15/30 20130101 |
Class at
Publication: |
345/426 |
International
Class: |
G06T 15/00 20060101
G06T015/00; G06T 15/80 20060101 G06T015/80 |
Claims
1. A computer graphics processing method, comprising: processing a
set of graphics primitive information for a virtual object with
compute shader running on a GPU to generate a modified set of
primitive information; passing the modified set of primitive
information to a vertex shader running on the GPU; and performing
vertex shading on the modified set of primitive information with
the vertex shader.
2. The method of claim 1, wherein processing the set of graphics
primitive information with compute shader running on a GPU includes
performing position computations on the set of to generate a
reduced set of primitive information, wherein the reduced set of
primitive information omits one or more items of primitive
information of the virtual object.
3. The method of claim 2, wherein the primitive information
includes information representative of one or more polygons.
4. The method of claim 3, wherein the one or more omitted items of
primitive information include indices corresponding to one or more
backfaced polygons.
5. The method of claim 3, wherein the one or more omitted items of
primitive information include indices corresponding to one or more
off-screen polygons.
6. The method of claim 3, wherein the one or more omitted items of
primitive information include indices corresponding one or more
zero-pixel polygons.
7. The method of claim 3, wherein said processing a set of graphics
primitive information for a virtual object includes culling an
index table for a set of polygons to remove polygons that will not
be presented on a display.
8. The method of claim 1, further comprising: compiling a vertex
shader instruction a first time to generate the compute shader; and
compiling the vertex shader instruction a second time to generate
the vertex shader.
9. The method of claim 1, wherein said passing the modified set of
primitive information to a vertex shader includes passing the
modified set of primitive information through a ring buffer.
10. The method of claim 1, wherein the vertex shader does not
repeat any processing of the graphics primitive information
performed by the compute shader.
11. A computer graphics system, comprising: a graphics processing
unit (GPU) configured to process a set of graphics primitive
information for a virtual object with compute shader running on the
GPU to generate a modified set of primitive information and pass
the modified set of primitive information to a vertex shader
running on the GPU and performing vertex shading on the modified
set of primitive information with the vertex shader.
12. The system of claim 11, wherein processing the set of graphics
primitive information with compute shader running on a GPU includes
performing position computations on the set of to generate a
reduced set of primitive information, wherein the reduced set of
primitive information omits one or more items of primitive
information of the virtual object.
13. The system of claim 12, wherein the primitive information
includes information representative of one or more polygons.
14. The system of claim 13, wherein the polygons are triangles.
15. The system of claim 13, wherein the one or more omitted items
of primitive information include indices corresponding to one or
more backfaced polygons.
16. The system of claim 13, wherein the one or more omitted items
of primitive information include indices corresponding to one or
more off-screen polygons.
17. The system of claim 13, wherein the one or more omitted items
of primitive information include indices corresponding one or more
zero-pixel polygons.
18. The system of claim 13, wherein said processing a set of
graphics primitive information for a virtual object includes
culling an index table for a set of polygons to remove polygons
that will not be presented on a display.
19. The system of claim 11, further comprising a central processing
unit (CPU), wherein the CPU is configured to compile a vertex
shader instruction a first time to generate the compute shader; and
compile the vertex shader instruction a second time to generate the
vertex shader.
20. The system of claim 11, wherein the GPU further comprises a
ring buffer, wherein the GPU is configured to pass the modified set
of primitive information from the compute shader to the vertex
shader through the ring buffer.
21. The system of claim, 11, wherein the system is an embedded
system, mobile phone, personal computer, tablet computer, portable
game device, workstation, or game console.
22. A non-transitory computer readable medium having computer
readable instructions embodied therein, the computer readable
instructions being configured to implement a graphics processing
method when executed, the graphics processing method comprising:
processing a set of graphics primitive information for a virtual
object with compute shader running on a GPU to generate a modified
set of primitive information; passing the modified set of primitive
information to a vertex shader running on the GPU; and performing
vertex shading on the modified set of primitive information with
the vertex shader.
Description
CLAIM OF PRIORITY
[0001] This application claims the priority benefit of
commonly-assigned U.S. provisional patent application No.
61/833,229 filed Jun. 10, 2013, the entire disclosures of which are
incorporated herein by reference.
FIELD OF THE DISCLOSURE
[0002] Aspects of the present disclosure are related to computer
graphics. In particular, the present disclosure is related to use
of compute shaders and vertex shaders in a graphics processing
unit.
BACKGROUND
[0003] Graphics processing typically involves coordination of two
processors, a central processing unit (CPU) and a graphics
processing unit (GPU). The GPU is a specialized electronic circuit
designed to accelerate the creation of images in a frame buffer
intended for output to a display. GPUs are used in embedded
systems, mobile phones, personal computers, tablet computers,
portable game devices, workstations, and game consoles. A GPU is
typically designed to be efficient at manipulating computer
graphics. GPU's often have a highly parallel processing
architecture that makes the GPU more effective than a
general-purpose CPU for algorithms where processing of large blocks
of data is done in parallel.
[0004] The CPU may send commands to the GPU to implement a
particular graphics processing task, e.g. render a particular
texture that has changed with respect to a previous frame in an
image. These draw commands may be coordinated by the CPU with a
graphics application interface (API) in order to issue graphics
rendering commands that correspond to the state of the particular
application's virtual environment.
[0005] In order to render textures for a particular program, a GPU
may perform a series of processing tasks in a "graphics pipeline"
to translate the visuals in the virtual environment into images
that can be rendered onto a display. A typical graphics pipeline
may include performing certain rendering or shading operations on
virtual objects in the virtual space, transformation and
rasterization of the virtual objects in the scene to produce pixel
data suitable for output display, and additional rendering tasks on
the pixels (or fragments) before outputting the rendered image on a
display.
[0006] Virtual objects of an image are often described in virtual
space in terms of shapes known primitives, which together make the
shapes of the objects in the virtual scene. For example, objects in
a three-dimensional virtual world to be rendered may be reduced to
a series of distinct triangle primitives having vertices defined in
terms of their coordinates in three-dimensional space, whereby
these polygons make up the surfaces of the objects. Each polygon
may have an associated index that can be used by the graphics
processing system to distinguish a given polygon from other
polygons. Likewise, each vertex may have an associated index that
can be used to distinguish a given vertex from other vertices. A
graphics pipeline may perform certain operations on these
primitives to produce visuals for the virtual scene and transform
this data into a two-dimensional format suitable for reproduction
by the pixels of the display. The term graphics primitive
information (or simply "primitive information"), as used herein, is
used to refer to data representative of a graphics primitive. Such
data includes, but is not limited to, vertex information (e.g.,
data representing vertex positions or vertex indices) and polygon
information, e.g., polygon indices and information that associates
particular vertices with particular polygons.
[0007] A GPU may perform rendering tasks of the graphics pipeline
by implementing programs commonly known as shaders. A typical
graphics pipeline may include vertex shaders, which may manipulate
certain properties of the primitives on a per-vertex basis, as well
as pixel shaders (also known as "fragment shaders"), which operate
downstream from the vertex shaders in the graphics pipeline and may
manipulate certain values on a per-pixel basis before transmitting
the pixel data to a display. The pipeline may also include other
shaders at various stages in the pipeline, such as geometry shaders
that use the output of the vertex shaders to generate a new set of
primitives, as well as compute shaders (CS) which may implemented
by a GPU to perform certain other general computational tasks.
[0008] Because many of the polygons that make up a virtual object
may share common vertices, shader programs may utilize vertex
buffers defining coordinates of distinct vertices in conjunction
with index buffers that identify which coordinates belong to which
triangles. The index buffers may include index tables identifying
draw objects by their corresponding vertices defined in the vertex
buffer.
[0009] In any particular image to be rendered, an object in a
virtual world may include many polygons that are hidden from view
in the image, such as backfaced and off-screen triangles. Moreover,
virtual objects in an image may include zero-pixel triangles that
are so small in size that they have no pixel centers to render on a
display. It is useful to remove such polygons from the graphics
pipeline to speed up the graphics pipeline.
[0010] It is within this context that the present disclosure
arises.
SUMMARY
[0011] According to an aspect of the present invention, a computer
graphics processing method may include processing a set of graphics
primitives for a virtual object with compute shader running on a
GPU to generate a modified set of primitive information, passing
the modified set of primitive information to a vertex shader
running on the GPU, and performing vertex shading on the modified
set of primitives with the vertex shader.
[0012] The aforementioned aspects of the present disclosure may be
implemented using a computer graphics system, having a graphics
processing unit (GPU) configured to process a set of graphics
primitives for a virtual object with compute shader miming on the
GPU to generate a modified set of primitive information and pass
the modified set of primitive information to a vertex shader
running on the GPU and performing vertex shading on the modified
set of primitive information with the vertex shader.
[0013] The aforementioned aspects of the present disclosure may be
implemented using a non-transitory computer readable medium having
computer readable instructions embodied therein. The computer
readable instructions may be configured to implement the
aforementioned graphics processing method when executed.
[0014] In certain implementations processing the set of graphics
primitive information includes performing position computations on
the set to generate a reduced set of primitive information, wherein
the reduced set of primitive information omits one or more items of
primitive information of the virtual object. In certain
implementations, the primitive information may include information
representative of one or more polygons. In some such
implementations, the one or more omitted primitive information may
include indices corresponding to one or more backfaced polygons or
more off-screen polygons or zero pixel polygons. In some such
implementations, processing the set of graphics primitive
information includes culling an index table for a set of polygons
to remove polygons that will not be presented on a display.
[0015] In some implementations, the method may further include
compiling a vertex shader instruction a first time to generate the
compute shader; and
[0016] compiling the vertex shader instruction a second time to
generate the vertex shader.
[0017] In some implementations, the modified set of primitive
information may be passed to the vertex shader through a ring
buffer.
[0018] In some implementations, the vertex shader does not repeat
any processing of the graphics primitive information performed by
the compute shader.
BRIEF DESCRIPTION OF THE DRAWINGS
[0019] The teachings of the present disclosure can be readily
understood by considering the following detailed description in
conjunction with the accompanying drawings, in which:
[0020] FIG. 1A is a block diagram of a conventional graphics
processing implementation.
[0021] FIG. 1B is a block diagram illustrating a graphics
processing in accordance with an aspect of the present
disclosure.
[0022] FIG. 2 is a block diagram of a portion of a graphics
processing system in accordance with aspects of the present
disclosure.
[0023] FIG. 3 is a block diagram of a graphics processing system in
accordance with aspects of the present disclosure.
DESCRIPTION OF THE DRAWINGS
[0024] Although the following detailed description contains many
specific details for the purposes of illustration, anyone of
ordinary skill in the art will appreciate that many variations and
alterations to the following details are within the scope of the
invention. Accordingly, the exemplary embodiments of the invention
described below are set forth without any loss of generality to,
and without imposing limitations upon, the claimed invention.
[0025] Introduction
[0026] As seen in FIG. 1A, conventional graphics processing is
typically implemented by a system 100 having a CPU and a GPU. The
CPU typically implements a graphics application program interface
(API) 102 that produces shader input for the GPU. In general the
CPU may obtain data regarding vertices that make up an object to be
rendered by the GPU and perform some processing on the data before
it is rendered. Such processing may include culling an index table.
This type of operation involves analyzing the set of polygons
(e.g., triangles) that make up the object to determine whether any
of the polygons do not need to be rendered. Each polygon in the set
may be identified by an index that identifies polygon. Each polygon
may be further characterized by a set of vertices, each of which
may have a corresponding index as well as a set of coordinates
(e.g., x,y,z,w) coordinates. A vertex is a data structure that
describes a point in 2D or 3D space. Display objects are composed
of arrays of flat surfaces (e.g., triangles) and vertices define
the location and other attributes of the corners of the surfaces.
Vertices may be associated not only with position but also with
other graphical attributes used to render the object correctly.
Such attributes may include, but are not limited to color at the
vertex point, reflectance of the surface at the vertex, coordinates
of textures to apply to the surface at the vertex, and the normal
of an approximated curved surface at the location of the vertex.
The normal can be used to determine a surface's orientation toward
a light source for flat shading using Lambert's cosine law, or the
orientation of each of the vertices to mimic a curved surface with
Phong shading. A vertex shader 104 may use these properties in
performing vertex shading. The vertex shader 104 typically
transforms each vertex's 3D position in virtual space to the 2D
coordinate at which it appears on the screen (as well as a depth
value for a Z-buffer).
[0027] The graphics API may generate an index table for the object
may store the indices for the polygons that make up the object. By
way of example, the culling operation implemented by the graphics
API may determine whether any of the polygons are backfaced or
offscreen (i.e., not visible in the final image), contain no
pixels, or are viewed on edge and therefore have zero area. The
indices for such polygons may be removed from the index table to
produce a culled index table that is sent to the GPU for further
processing. In particular, a vertex shader 104 running in the GPU
can convert the coordinates for each of the polygons in the culled
index table from 3D global coordinates to 2D local coordinates for
rendering on a display. The resulting vertex shader output 105 can
then be sent to a fragment shader 106 that fills in the resulting
polygons with pixels. Vertex shaders are typically run once for
each vertex given to the GPU. The GPU hardware typically can
implement a limited number of instances of vertex shaders.
[0028] Culling the index table with the CPU works well where the
CPU hardware is relatively powerful compared to the GPU in terms of
processing capabilities. However, as GPU hardware becomes more
capable, it would be desirable to perform tasks like index culling
on the GPU. Modern GPUs can implement highly parallel processing
and it would be advantageous to utilize this capability to reduce
bottlenecks in the graphics pipeline.
[0029] Method
[0030] According to Aspects of the present disclosure certain parts
of the graphics pipeline traditionally performed by the CPU using a
compute shader running on the GPU.
[0031] As shown in the method 100B of FIG. 1B, according to aspects
of the present disclosure processing of a set of graphics primitive
information 103' can be done by the compute shader 101 running on a
GPU and the resulting modified set of primitive information 105'
can be passed to a vertex shader 104 miming on the GPU without
having to have the vertex shader repeat any of the processing done
by the compute shader. This avoids having to perform the processing
that produces the modified set of primitive information with the
CPU and thereby avoids bottlenecks associated with transferring
data between the CPU and the GPU. The vertex shader 104 can produce
output 107 that can be sent to a fragment shader 106 that fills in
the resulting polygons with pixels.
[0032] According to certain aspects of the present disclosure, a
graphics API 102 can invoke a vertex shader as indicated at 112.
The graphics API may run on a CPU that is separate and distinct
from the GPU. The vertex shader invocation may be compiled once by
a compiler 114.sub.C to generate the compute shader 101 and
compiled a second time by a compiler 114.sub.V to generate the
vertex shader 104.
[0033] A compute shader is a shader stage that can be run on the
GPU to perform arbitrary computations. Although compute shaders
could do rendering, they are generally used for tasks not directly
related to drawing polygons and pixels. Compute shaders operate
differently from other shader stages in that all of the other
shader stages (e.g., vertex shaders and pixel shaders) a
well-defined sets of input and output values, which may be built-in
or user-defined. The frequency at which a shader stage executes is
specified by the nature of that stage; vertex shaders execute once
per input vertex, for example (though some executions can be
skipped via caching). Fragment (or pixel) shader execution is
defined by the fragments generated from the rasterization
process.
[0034] Compute shaders, by contrast operate on a data "space" that
is largely abstract. Each compute shader decides what the space
means. The number of compute shader executions is defined by the
function used to execute the compute operation. As a result, the
number of compute shader instances that can be run at one time is
almost unlimited. Most important of all, compute shaders have no
user-defined inputs and no outputs at all. The built-in inputs only
define where in the "space" of execution a particular compute
shader invocation is.
[0035] Therefore, if a compute shader wants to take some values as
input, it is up to the shader itself to fetch that data, via
texture access, arbitrary image load, shader storage blocks, or
other forms of interface. Similarly, if a compute shader is to
actually compute anything, it must explicitly write to an image or
shader storage block.
[0036] Because of these properties, a compute shader may be used to
implement tasks such as index culling on the GPU that were formerly
performed on the CPU. According to aspects of the present
disclosure this may be implemented as shown in FIG. 2.
[0037] In FIG. 2, a GPU 200 may be configured to run a compute
shader 202 and a vertex shader 204. The compute shader 202 may
operate on input data received from a source outside the GPU, e.g.,
from a CPU (not shown). Output generated by the compute shader 202
may be passed to the vertex shader 204 for further processing.
[0038] In certain implementations, the data may be passed from the
compute shader to the vertex shader via one or more ring buffers
210. This type of buffer uses a single fixed sized buffer that is
configured as if it were connected end to end. When the buffer is
full and new data is to be added to the buffer existing data is
overwritten. However, if the ring buffer is large enough and the
operations of the compute shader and vertex shader are sufficiently
synchronized the vertex shader can access data written by the
compute shader before it is overwritten. The ring buffer 210 reuses
the same piece of memory and stores the index data only for as long
as it is needed. As soon as the data in the ring buffer 210 is
passed to the vertex shader 204 that data can be written over.
[0039] It is noted that there may be more than one ring buffer
depending on the type of data to be buffered. For example, index
data may be buffered in an index ring buffer IRB and vertex data
may be buffered in a separate detected vertex ring buffer VRB. The
ring buffers 210 may be mapped to the memory 206. The compute
shader 202 may write index data through the index ring buffer IRB
and write vertex data through the vertex ring buffer VRB.
[0040] Although the ring buffers 210 are mapped to memory writes to
the ring buffers initially sit in a GPU cache 208. If the vertex
shader 204 can read the data as it is going into the GPU cache 208
and before its overwritten and before other processes that are
running on the GPU 204 flush it out because they need space in the
cache then the data will go into the ring buffer 210 from the
compute shader 202 and out of the ring buffer 210 to the vertex
shader 204. Many cycles of such writing and reading of data through
the ring buffer 210 can take place without the data ever being
written to a memory 206. Only after the system is run will the
small amount of data in the ring buffer 210 be evicted into memory
206. Therefore the only memory bandwidth need for the data that is
passed from the compute shader 202 to the vertex shader 204 is the
size of the relevant ring buffer 210. By way of example, and not by
way of limitation, the size of the index ring buffer IRB can be
much smaller than the total size of index data that is being passed
from the compute shader 202 to the vertex shader 204. For example,
the total amount of index data in a culled index table may be about
1 MB but the size of the index ring buffer IRB may be only 48 KB.
The GPU 200 therefore only needs 48 KB of memory bandwidth to
implement the culling with the compute shader 202. If, by contrast
the compute shader 202 runs a long time ahead of running the vertex
shader 204 1 MB of space would be required to hold all 1 MB of
indices until the vertex shader 204 runs the graphics tasks that
use the indices. By using a tightly coupled system with a ring
buffer 210 the memory footprint for the index data can be greatly
reduced.
[0041] Access to the index ring buffer 210 should be synchronized
in order to tightly couple the operations of the compute shader 202
and vertex shader 204. Such synchronization involves making sure
that data is not flushed or overwritten before the vertex processor
204 has used it. The speed of the synchronization determines the
size of the ring buffer 210 that is needed. In general faster
synchronization results in a smaller required ring buffer size.
Furthermore, if the synchronization requires too much overhead
bottlenecks may be introduced into the GPU. To implement the
synchronization, the hardware of the GPU 200 may be configured to
control access to the ring buffers 210 prevent data from being
discarded from a ring buffer before it is needed by the vertex
shader 204.
[0042] There are a number of ways in which the GPU 200 may be used.
For example, the compute shader 202 may be configured to implement
polygon culling (e.g., triangle culling), as discussed above. In
such a case, the culled index data may be passed through to the
vertex shader via the index ring buffer IRB. It is noted that the
three-dimensional positions of the vertices are generated as part
of the process of polygon culling. Once the positions of the
vertices have been computed by the compute shader 202 they can be
stored in the vertex ring buffer VRB and passed through to the
vertex shader so that the vertex shader does not have to re-compute
them.
[0043] As noted above, the GPU 200 can be configured to pass vertex
data as well as index data. As such, implementations of aspects of
the present disclosure are not limited to those involving
generation of culled index tables using a compute shader. Examples
of operations that could be implemented with the compute shader 202
include vertex transforms that are closely related to an underlying
physics simulation. One such example is known as skinning of
vertices, which is a common operation in computer games or video
games. In a skinning operation, the locations of the vertices that
are passed to the vertex shader are tied in some way to underlying
structures sometimes known as "bones". The bones may be thought of
as skeletal features that are subject to constraints (e.g.,
joints). The movements of the bones may be determined through a
physics simulation run on a CPU. The vertices are said to be
"skinned" to one or more bones through corresponding transform
matrices. In general, there may be one local transform matrix per
bone. Each vertex may reference some number of bones with a
different weight for each reference. To calculate the vertex
position, the vertex may be transformed separately according to
each affecting bone's transform matrix, and the separate results
may then be blended (interpolated) based on the weights to
determine the final position of the vertex.
[0044] Normally a compute shader would have to perform the skinning
work to determine the vertex positions then write up the index data
for the corresponding polygons and pass that data to the vertex
shader. The vertex shader would then re-do all of the skinning
work. However, according to aspects of the present disclosure, the
ring buffer 210 may be used to pass the skinned vertex data from
the compute shader 202 to the vertex shader 204 without having to
have the vertex shader re-do the vertex calculations. The compute
shader 202 would just pass the skinned vertex data to the vertex
shader via the vertex ring buffer VRB.
[0045] Aspects of the present disclosure include graphics
processing systems that are configured to implement the features
discussed above. By way of example, and not by way of limitation,
FIG. 3 illustrates a block diagram of a computer system 300 that
may be used to implement graphics processing according to aspects
of the present disclosure. According to aspects of the present
disclosure, the system 400 may be an embedded system, mobile phone,
personal computer, tablet computer, portable game device,
workstation, game console, and the like.
[0046] The system 300 generally may include a central processor
unit (CPU) 302, a graphics processor unit (GPU) 304, and a memory
308 that is accessible to both the CPU and GPU. The CPU 302 and GPU
304 may each include one or more processor cores, e.g., a single
core, two cores, four cores, eight cores, or more. The memory 308
may be in the form of an integrated circuit that provides
addressable memory, e.g., RAM, DRAM, and the like.
[0047] By way of example, and not by way of limitation, the CPU 302
and GPU 304 may access the memory 308 using a data bus 309. In some
cases, it may be useful for the system 300 to include two or more
different buses. The memory 308 may contain data that can be
accessed by the CPU 302 and GPU 304. The GPU 304 may include a
plurality of compute units configured to perform graphics
processing tasks in parallel. Each compute unit may include its own
dedicated local memory store, such as a local data share.
[0048] The CPU may be configured to execute CPU code 303.sub.C,
which may include an application that utilizes graphics, a compiler
and a graphics API. The graphics API can be configured to issue
draw commands to programs implemented by the GPU. The CPU code
303.sub.C may also implement physics simulations and other
functions. The GPU may be configured to operate as discussed above
with respect to FIG. 2. In particular, the GPU may execute GPU code
303G, which may implement compute shaders CS and vertex shaders VS,
as discussed above. To facilitate passing of data between the
compute shaders CS and the vertex shaders VS the system may include
one or more ring buffers 305, which may include index ring buffers
IRB and vertex ring buffers VRB. The GPU code 303.sub.G may also
optionally implement other types of shaders (not shown), such as
pixel shaders or geometry shaders. Each compute unit may include
its own dedicated local memory store, such as a local data
share.
[0049] The system 300 may also include well-known support functions
310, which may communicate with other components of the system,
e.g., via the bus 309. Such support functions may include, but are
not limited to, input/output (I/O) elements 311, power supplies
(P/S) 312, a clock (CLK) 313 and cache 314. In addition to the
cache 314, the GPU 304 may include its own GPU cache 314.sub.G, and
the GPU may be configured so that programs running on the GPU 304
can read-through or write-though the GPU cache 314.sub.G in
particular, the system may be configured so that compute shaders
running on the GPU can write-through the GPU cache to the memory or
buffers and vertex shaders can read through the GPU cache 314.sub.G
from the memory or buffers.
[0050] The system 300 may optionally include a mass storage device
315 such as a disk drive, CD-ROM drive, flash memory, tape drive,
or the like to store programs and/or data. The system 300 may also
optionally include a display unit 306 and user interface unit 318
to facilitate interaction between the system 300 and a user. The
display unit 306 may be in the form of a flat panel display,
cathode ray tube (CRT) screen or other device that can display
text, numerals, graphical symbols or images. The user interface 318
may include a keyboard, mouse, joystick, light pen, game
controller, or other device that may be used in conjunction with a
graphical user interface (GUI). The system 300 may also include a
network interface 320 to enable the device to communicate with
other devices over a network 322. The network 322 may be, e.g., a
local area network (LAN), a wide area network such as the internet,
a personal area network, such as a Bluetooth network or other type
of network. These components may be implemented in hardware,
software, or firmware, or some combination of two or more of
these.
[0051] While the above is a complete description of the preferred
embodiment of the present invention, it is possible to use various
alternatives, modifications and equivalents. Therefore, the scope
of the present invention should be determined not with reference to
the above description but should, instead, be determined with
reference to the appended claims, along with their full scope of
equivalents. Any feature described herein, whether preferred or
not, may be combined with any other feature described herein,
whether preferred or not. In the claims that follow, the indefinite
article "A", or "An" refers to a quantity of one or more of the
item following the article, except where expressly stated
otherwise. The appended claims are not to be interpreted as
including means-plus-function limitations, unless such a limitation
is explicitly recited in a given claim using the phrase "means
for."
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