U.S. patent application number 13/913617 was filed with the patent office on 2014-12-11 for multi-metal gate semiconductor device having triple diameter metal opening.
The applicant listed for this patent is UNITED MICROELECTRONICS CORP.. Invention is credited to Chih-Sen Huang, Ching-Wen Hung, Yi-Ching Wu.
Application Number | 20140361381 13/913617 |
Document ID | / |
Family ID | 52004757 |
Filed Date | 2014-12-11 |
United States Patent
Application |
20140361381 |
Kind Code |
A1 |
Hung; Ching-Wen ; et
al. |
December 11, 2014 |
MULTI-METAL GATE SEMICONDUCTOR DEVICE HAVING TRIPLE DIAMETER METAL
OPENING
Abstract
A method for manufacturing a semiconductor device and a device
manufactured using the same are provided. A substrate with plural
metal gates formed thereon is provided, wherein the adjacent metal
gates are separated by insulation. A sacrificial layer is formed
for capping the metal gates and the insulation, and the sacrificial
layer and the insulation are patterned to form at least an opening
for exposing the substrate. A silicide is formed corresponding to
the opening at the substrate, and a conductive contact is formed in
the opening. The conductive contact has a top area with a second
diameter CD2 for opening the insulation. A patterned dielectric
layer, further formed on the metal gates, the insulation and the
conductive contact, at least has a first M0 opening with a third
diameter CD3 for exposing the conductive contact, wherein
CD2>CD3.
Inventors: |
Hung; Ching-Wen; (Tainan
City, TW) ; Huang; Chih-Sen; (Tainan City, TW)
; Wu; Yi-Ching; (Kaohsiung City, TW) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
UNITED MICROELECTRONICS CORP. |
Hsinchu |
|
TW |
|
|
Family ID: |
52004757 |
Appl. No.: |
13/913617 |
Filed: |
June 10, 2013 |
Current U.S.
Class: |
257/384 ;
438/653 |
Current CPC
Class: |
H01L 21/76895 20130101;
H01L 21/76843 20130101; H01L 21/76897 20130101; H01L 2924/0002
20130101; H01L 21/28518 20130101; H01L 23/485 20130101; H01L
2924/0002 20130101; H01L 2924/00 20130101; H01L 21/76855 20130101;
H01L 29/458 20130101 |
Class at
Publication: |
257/384 ;
438/653 |
International
Class: |
H01L 21/768 20060101
H01L021/768; H01L 29/45 20060101 H01L029/45 |
Claims
1-16. (canceled)
17. A semiconductor device, comprising: a substrate with a gate
layer formed thereon and silicides formed therein, and the gate
layer comprising plural metal gates separated by an insulation,
said silicides positioned between the metal gates; at least a
conductive contact formed in the insulation between adjacent metal
gates for electrically connecting the silicide; and a patterned
dielectric layer formed on the metal gates, the insulation and the
conductive contact, and the patterned dielectric layer at least
having a first metal-0(M0) opening exposing the conductive contact;
wherein the conductive contact has a bottom area with a first
diameter (CD1) for electrically connecting the silicide, and has a
top area with a second diameter (CD2) for opening the insulation,
wherein the first M0 opening has a bottom area with a third
diameter (CD3) for exposing the conductive contact, and the third
diameter (CD3) is smaller than the second diameter (CD2).
18. The semiconductor device according to claim 17, wherein the
patterned dielectric layer further has a second M0 opening exposing
the metal gate, and the semiconductor device further comprises a
first M0 contact and a second M0 contact respectively formed in the
first M0 opening and the second M0 opening.
19. The semiconductor device according to claim 17, wherein said
silicide is NiSi with a concave surface to the substrate, or TiSi
with a convex surface to the substrate.
20. The semiconductor device according to claim 17, wherein the
conductive contact comprises: a first barrier metal deposited in an
opening of the insulation as a liner; and a conductive material
fills up the opening.
21. The semiconductor device according to claim 20, wherein the
first barrier metal is a Ti/TiN multilayer.
22. The semiconductor device according to claim 17, wherein the
insulation comprises: spacers, formed at sidewalls of the metal
gates; a contact etch stop layer (CESL), formed on the substrate as
an U-shape between the spacers; and a patterned ILD, filled in a
space of the U-shaped CESL.
23. The semiconductor device according to claim 17, wherein the
second diameter (CD2) is larger than the first diameter (CD1).
24. The semiconductor device according to claim 17, wherein a
diameter of CD1 is in a range from 20 nm to 40 nm, a diameter of
CD2 is in a range from 50 nm to 80 nm, and a diameter of CD3 is in
a range from 30 nm to 50 nm.
Description
BACKGROUND
[0001] 1. Technical Field
[0002] The disclosure relates in general to a method for
manufacturing a semiconductor device and device manufactured using
the same, and more particularly to the method for manufacturing a
semiconductor device with a sacrificial layer for silicide
formation, thereby preventing possible damages to the metal gate
due to the oxide loss in the subsequent procedures.
[0003] 2. Description of the Related Art
[0004] Size of semiconductor device has been decreased for these
years. Reduction of feature size, improvements of the rate, the
efficiency, the density and the cost per integrated circuit unit
are the important goals in the semiconductor technology. The
electrical properties of the device have to be maintained even
improved with the decrease of the size, to meet the requirements of
the commercial products in applications. For example, the layers
and components with damages, which have considerable effects on the
electrical properties, would be one of the important issues of the
device for the manufacturers.
SUMMARY
[0005] The disclosure is directed to a method for manufacturing a
semiconductor device and device manufactured using the same, which
a sacrificial layer is added before silicide formation, and
possible damages to the metal gate due to the oxide loss in the
subsequent patterning procedures would be effectively prevented,
thereby improving the electrical properties of the device.
[0006] According to the disclosure, a method for manufacturing a
semiconductor device is provided. A substrate with plural metal
gates formed thereon is provided, wherein the adjacent metal gates
are separated by insulation. A sacrificial layer is formed for
capping the metal gates and the insulation, and the sacrificial
layer and the insulation are patterned to form at least an opening
for exposing the substrate. A silicide is formed corresponding to
the opening at the substrate, and a conductive contact is formed in
the opening.
[0007] According to the disclosure, a semiconductor device is
provided, comprising a substrate with a gate layer formed thereon
and silicides formed therein, and the gate layer comprising plural
metal gates separated by an insulation, said silicides positioned
between the metal gates; at least a conductive contact formed in
the insulation between adjacent metal gates for electrically
connecting the silicide; and a patterned dielectric layer formed on
the metal gates, the insulation and the conductive contact, and the
patterned dielectric layer at least having a first metal-0(M0)
opening exposing the conductive contact. The conductive contact has
a bottom area with a first diameter (CD1) for electrically
connecting the silicide, and has a top area with a second diameter
(CD2) for opening the insulation. Also, the first M0 opening has a
bottom area with a third diameter (CD3) for exposing the conductive
contact. The third diameter (CD3) is smaller than the second
diameter (CD2).
BRIEF DESCRIPTION OF THE DRAWINGS
[0008] FIG. 1A-FIG. 1H illustrate a method for manufacturing a
semiconductor device according to a first embodiment of the present
disclosure.
[0009] FIG. 2A is a simple drawing showing a method of patterning
split.
[0010] FIG. 2B is a simple drawing showing a method of slot
cut.
[0011] FIG. 3 shows formation of TiSi in the method for
manufacturing a semiconductor device according to the second
embodiment of the present disclosure.
DETAILED DESCRIPTION
[0012] In the present disclosure, a method for manufacturing a
semiconductor device is provided to effectively prevent the
possible damages to the components (such as metal gate, etch stop
layer...etc.), and the electrical properties of the device
manufactured using the method of the present disclosure could be
greatly improved. The embodiments are described in details with
reference to the accompanying drawings. The identical and/or
similar elements of the embodiments are designated with the same
and/or similar reference numerals. Also, it is also important to
point out that the illustrations may not be necessarily be drawn to
scale, and that there may be other embodiments of the present
disclosure which are not specifically illustrated. Thus, the
specification and the drawings are to be regard as an illustrative
sense rather than a restrictive sense.
[0013] In the present disclosure, a sacrificial layer is added
before silicide formation, and the method for manufacturing a
semiconductor device would be slightly different, and could be
modified and changed according to the selected material of the
silicide and the patterning procedures in practical applications.
Two different materials of silicides are taken for describing the
embodiments, but the present disclosure is not limited thereto.
First Embodiment
[0014] FIG. 1A-FIG. 1H illustrate a method for manufacturing a
semiconductor device according to a first embodiment of the present
disclosure. First, a substrate 10 having plural gate structures
such as metal gates 12 formed thereon is provided, wherein the
adjacent metal gates 12 are separated by an insulation, as shown in
FIG. 1A. In one embodiment, a RMG (replacement metal gate) process
would have been done, and a metal portion 121 and a hard mask layer
122 on the metal portion 121 constitute a metal gate 12 of the
device. Also, two spacers 14 are formed at the sidewalls of the
metal gate 12, and a contact etch stop layer (CESL) 16 is formed on
the substrate 10 as an U-shape between the spacers 14. An
interlayer dielectric (ILD) layer 18 fills into the space of the
U-shaped CESL 16. Accordingly, the insulation for separating the
adjacent metal gates 12 comprises the spacers 14, the CESL 16 and
the ILD layer 18, as shown in FIG. 1A.
[0015] In one embodiment, the substrate 10 could be a silicon
substrate, the spacers 14 and the CESL 16 could be made of the same
material such as SICN, formed by atomic layer deposition (ALD).
Also, the hard mask layer 122 could be made of nitrite or oxide;
for example, the hard mask layer 122 is made of silicon nitrite
(SIN). Also, the spacers 14 could be one layer or multi-layer,
which are not limited particularly.
[0016] Afterward, a sacrificial layer 19 is formed for capping the
metal gates 12 and the insulation (including the spacers 14, the
CESL 16 and the ILD layer 18), and the sacrificial layer 19 and the
insulation are patterned to form at least an opening 191 for
exposing the substrate 10, as shown in FIG. 1B. Two openings 191
are illustrated in the drawings, but the number of the openings 191
would be determined depending on the actual needs of the practical
applications. In one embodiment, each opening 191 could be formed
by lithography and etching procedures, and the ILD layer 18, parts
of the CESL 16 and the spacers 14 are removed. In the etching
procedure, top rounding is performed, and the top of the opening
191 is wider than the bottom of the opening 191, as shown in FIG.
1B. In one embodiment, a thickness of the sacrificial layer 19 is
in a range of about 300 .ANG.-about 500 .ANG., such as about 400
.ANG., but those values are not for limiting the scope of the
disclosure.
[0017] The material of the sacrificial layer 19 is different from
that of the hard mask layer 122. In one embodiment, the sacrificial
layer 19 is (but not limited to) made of SiON, SiCN, or oxides.
[0018] Also, after forming the openings 191, the substrate 10 and
the openings 191 could be subjected to a treatment, such as a
SiCoNi pre-clean treatment or an Ar pre-clean treatment, to clean
the impurities (ex: native oxides).
[0019] A silicide is then formed corresponding to the opening 191
at the substrate 10, as shown in FIG. 1C. The silicide may be NiSi,
TiSi or cold Ti, which is not limited particularly. NiSi 20 is
taken for exemplifying the silicide of the first embodiment. In the
step of forming the NiSi 20, a Ni containing layer (such as NiPt)
is deposited at the substrate 10 within the openings 191, and then
subjected to a thermal treatment to form a Ni containing portion
such as the NiSi 20 at the substrate 10. Then, the unreacted Ni
containing portion is removed, such as by wet etching using
suitable chemical agents/solution. The NiSi 20 has a surface
concave to the substrate 10 as depicted in FIG. 1C.
[0020] In the first embodiment, the thermal treatment could be a
rapid thermal process (RTP), which is performed to make a portion
of the Ni containing layer (such as NiPt) react with the substrate
10 (such as the silicon substrate) to form a Ni containing portion
such as the NiSi 20. The rapid thermal process could be conducted
at the temperature sufficient to conduct the Ni-silicide
formation.
[0021] After formation of silicide, a conductive contact 23' is
further formed in the opening 191 (FIG. 1F). In the first
embodiment, formation of the conductive contact 23' could be
implemented by depositing a first barrier metal 21 in the opening
191 as a liner (FIG. 1D), depositing a conductive material 23 on
the substrate 10 and filling the opening 191 (FIG. 1E), and
planarizing the conductive material 23 to expose the metal gate 12
(FIG. 1F). In the first embodiment, the NiSi 20 and the conductive
contact 23' are separated by the first barrier metal 21.
[0022] In the first embodiment with the formation of NiSi 20, the
first barrier metal 21 could be Ti/TiN (Ti improving adhesion
between TiN and dielectric) or other suitable materials. The
conductive material 23 could be tungsten (W), and planarized by
chemical-mechanical polishing (CMP) or other suitable planarization
methods to expose the metal gate 12. As shown in FIG. 1F, the hard
mask layer 122 of the metal gate 12 is exposed after planarization
of the conductive material 23. The sacrificial layer 19 could be
also removed during planarization.
[0023] In the embodiment, the thickness of the sacrificial layer 19
could be determined by evaluating the insulation and hard mask
layer 122 loss in sum in the subsequent procedures, such as
insulation and hard mask layer 122 loss in the open-forming step,
the pre-clean step (SiCoNi pre-clean or Ar pre-clean) and tungsten
(W)-planarizing step.
[0024] After formation of the conductive contact 23' in the opening
191, a dielectric layer 25 such as a post-metal dielectric (PMD) is
formed on the metal gates 12, the insulation and the conductive
contact 23', followed by patterning. After patterning the
dielectric layer 25, at least a first metal-0 (M0) opening 25a and
a second M0 opening 25b are formed for respectively exposing the
conductive contact 23' and the metal gate 12. As shown in FIG. 1G,
patterning procedures (such as lithography and etching) for forming
the first M0 opening 25a and the second M0 opening 25b could be
performed according to the designs and pattern requirements of the
practical application, and the overlapping area(s) denoted as
25a+25b could be created. In the practical application, the first
M0 opening 25a could be the M0 S/D contact hole, and the second M0
opening 25b could be the M0 gate contact hole. Furthermore,
formation of the M0 openings 25a could be performed before or after
that of the second M0 opening 25b, which is not limited
particularly.
[0025] Afterwards, steps of deposition of a barrier metal layer 26
(such as Ti/TiN), deposition of a conductive material (such as W)
for filling the first M0 opening 25a and the second M0 opening 25b,
followed by planarizing the conductive material are performed to
respectively form a first M0 contact 27a and a second M0 contact
27b in the first M0 opening 25a and the second M0 opening 25b, as
shown in FIG. 1H. In the practical application, the first M0
contact 27a could be a conductive M0 S/D contact, and the second M0
contact 27b could be a conductive M0 gate contact.
[0026] Please refer to FIG. 1B and FIG. 1G. The opening 191 has a
bottom area with a first diameter (denoted as CD1) for exposing the
substrate 10, and has a top area with a second diameter (denoted as
CD2) for opening the insulation. In one embodiment, the top area of
the opening 191 having the second diameter CD2 exposes the CESL 16.
Also, the first M0 opening 25a has a bottom area with a third
diameter (denoted as CD3) for exposing the conductive contact 23'.
According to the method of manufacturing the device of the
embodiment, the second diameter CD2 would be larger than the first
diameter CD1, and the third diameter CD3 would be smaller than the
second diameter CD2. This structural feature could be easily
identified by the microscopic examination.
[0027] In one embodiment, the diameter CD1 is in a range from 20 nm
to 40 nm, the diameter of CD2 is in a range from 50 nm to 80 nm,
and the diameter of CD3 is in a range from 30 nm to 50 nm. However,
it is known that the diameter of CD1/CD2/CD3 would be determined
according to structural design and device requirements of the
practical application, and/or processing ability, and could be
modified and changed depending on different conditions.
[0028] Additionally, contact patterning (to form the openings 191)
and/or M0 patterning (to form the first M0 opening and the second
M0 opening) could be carried out by two different methods: (1)
patterning split; and (2) slot cut. Take formation of the first M0
opening and the second M0 opening for example. FIG. 2A is a simple
drawing showing a method of patterning split. FIG. 2B is a simple
drawing showing a method of slot cut. In FIG. 2A and FIG. 2B, it is
assumed that formation of two first M0 opening 35a and two second
M0 opening 35b are required in a pattern design, which are arranged
with an alternate order (as shown in the top pictures of FIG. 2A
and FIG. 2B). In the method of patterning split (FIG. 2A), a first
mask is used for transferring pattern to form the trenches 1 as the
first M0 openings 35a, and a second mask is then used for
transferring pattern to form the trenches 2 as the second M0
openings 35b, as shown in FIG. 2A. In the method of slot cut (FIG.
2B), a first mask is used for transferring pattern to form the
trenches 1, which are plural fine-striped regions 41 related to the
min-pitch and/or the dense areas of the substrate. The trenches 1
are neither the final pattern of the first M0 openings 35a nor the
second M0 openings 35b. Then, a second mask may include a pattern
42 with opaque regions and/or transmissive regions for slot-cutting
the unwanted portions of the trenches 1 correspondingly, thereby
defining plural trenches (1+2) as the first M0 openings 35a and the
second M0 openings 35b, respectively.
Second Embodiment
[0029] The method for manufacturing a semiconductor device of the
second embodiment is similar to that of the first embodiment. In
the first embodiment, a Ni containing material such as NiSi 20 is
taken for exemplifying the silicide of the device (FIG. 1C). In the
second embodiment, a Ti containing material such as TiSi is taken
for exemplifying the silicide of the device. FIG. 3 shows formation
of TiSi in the method for manufacturing a semiconductor device
according to the second embodiment of the present disclosure. The
identical elements of FIG. 3 and FIG. 1A-FIG. 1H are designated
with the same reference numerals, and explanation of identical or
similar part is not repeated redundantly.
[0030] Similarly, a substrate 10 having plural gate structures such
as metal gates 12 formed thereon is provided, wherein the adjacent
metal gates 12 are separated by an insulation (as presented in FIG.
1A). A sacrificial layer 19 for capping the metal gates 12 and the
insulation is formed, followed by the patterning steps to form the
openings 191 (as presented in FIG. 1B). A treatment, such as a
SiCoNi pre-clean treatment or an Ar pre-clean treatment, could be
performed for cleaning the impurities (ex: native oxides).
[0031] Then, a silicide is then formed corresponding to the opening
191 at the substrate 10. In the second embodiment, a Ti containing
layer such as a multi-layer of Ti/TiN is deposited on the substrate
10 within the opening 191, and then subjected to a thermal
treatment to form a Ti containing portion such as the TiSi 40 at
the substrate 10. The TiSi 40 has a surface convex to the substrate
10 as depicted in FIG. 3. There is no need to remove the unreacted
Ti containing portion (such as Ti/TiN) since it could act as a
barrier metal layer for the subsequent process. Thus, the unreacted
Ti containing portion is remained in the opening 191 as a first
barrier metal 41. Also, if Ti/TiN is deposited as the first barrier
metal 41, the thickness of the bottom Ti is smaller than the
thickness of the sidewall Ti, due to the loss of bottom Ti caused
by the bottom Ti reacting with silicon of the substrate for forming
TiSi.
[0032] In the second embodiment, the thermal treatment could be a
rapid thermal process (RTP), which is performed to make a portion
of the Ti containing layer (such as Ti/TiN) react with the
substrate 10 (such as the silicon substrate) to form a Ti
containing portion such as the TiSi 40. The rapid thermal process
could be conducted at the temperature sufficient to conduct the
Ti-silicide formation.
[0033] Other steps of forming the conductive contact 23' in the
opening 191, comprising depositing a conductive layer (such as W)
on the substrate 10 and filling the opening 191, followed by
planarization (ex: CMP), are similar to the descriptions of the
first embodiment, which are not redundantly repeated.
[0034] According to the aforementioned descriptions, the provided
methods for manufacturing the semiconductor device of the
embodiments adopt an extra sacrificial layer before silicide
formation, thereby effectively preventing the possible damages to
the components (such as the metal gate, the etch stop layer . . .
etc.) of the device. The electrical properties of the device
manufactured using the method of the present embodiments could be
greatly improved consequently.
[0035] Other embodiments with different configurations of contacts,
gates, (source and drain) are also applicable, which could be
varied depending on the actual needs of the applications. It is, of
course, noted that the configurations of FIG. 1A-FIG. 1H and FIG. 3
are depicted only for demonstration, not for limitation. It is
known by people skilled in the art that the shapes or positional
relationship of the constituting elements could be adjusted
according to the requirements and/or manufacturing methods of the
practical applications.
[0036] While the disclosure has been described by way of example
and in terms of the exemplary embodiment(s), it is to be understood
that the disclosure is not limited thereto. On the contrary, it is
intended to cover various modifications and similar arrangements
and procedures, and the scope of the appended claims therefore
should be accorded the broadest interpretation so as to encompass
all such modifications and similar arrangements and procedures.
* * * * *