U.S. patent application number 14/463392 was filed with the patent office on 2014-12-04 for nano-pillar transistor fabrication and use.
The applicant listed for this patent is CALIFORNIA INSTITUTE OF TECHNOLOGY. Invention is credited to Michael D. HENRY, Andrew P. HOMYK, Aditya RAJAGOPAL, Axel SCHERER, Thomas A. TOMBRELLO, Sameer WALAVALKAR.
Application Number | 20140357974 14/463392 |
Document ID | / |
Family ID | 49882571 |
Filed Date | 2014-12-04 |
United States Patent
Application |
20140357974 |
Kind Code |
A1 |
RAJAGOPAL; Aditya ; et
al. |
December 4, 2014 |
NANO-PILLAR TRANSISTOR FABRICATION AND USE
Abstract
A field effect nano-pillar transistor has a pillar shaped gate
element incorporating a biomimitec portion that provides various
advantages over prior art devices. The small size of the
nano-pillar transistor allows for advantageous insertion into
cellular membranes, and the biomimitec character of the gate
element operates as an advantageous interface for sensing small
amplitude voltages such as transmembrane cell potentials. The
nano-pillar transistor can be used in various embodiments to
stimulate cells, to measure cell response, or to perform a
combination of both actions.
Inventors: |
RAJAGOPAL; Aditya; (IRVINE,
CA) ; SCHERER; Axel; (BARNARD, VT) ; HENRY;
Michael D.; (ALTADENA, CA) ; WALAVALKAR; Sameer;
(STUDIO CITY, CA) ; TOMBRELLO; Thomas A.;
(ALTADENA, CA) ; HOMYK; Andrew P.; (SOUTH
PASADENA, CA) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
CALIFORNIA INSTITUTE OF TECHNOLOGY |
PASADENA |
CA |
US |
|
|
Family ID: |
49882571 |
Appl. No.: |
14/463392 |
Filed: |
August 19, 2014 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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13852480 |
Mar 28, 2013 |
8841712 |
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14463392 |
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61617528 |
Mar 29, 2012 |
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Current U.S.
Class: |
600/377 ;
257/288; 600/395 |
Current CPC
Class: |
G01R 1/07342 20130101;
H01L 29/78 20130101; H01L 29/42376 20130101; H01L 29/413 20130101;
H01L 29/4966 20130101; C12Q 1/02 20130101; H01L 29/66477 20130101;
G01N 27/3275 20130101; G01N 27/4146 20130101; G01R 1/06711
20130101; H01L 29/7831 20130101; A61B 5/04001 20130101 |
Class at
Publication: |
600/377 ;
257/288; 600/395 |
International
Class: |
H01L 29/423 20060101
H01L029/423; A61B 5/04 20060101 A61B005/04; H01L 29/49 20060101
H01L029/49; H01L 29/78 20060101 H01L029/78; H01L 29/41 20060101
H01L029/41 |
Goverment Interests
STATEMENT OF FEDERAL GOVERNMENT SUPPORT
[0002] This invention was made with government support under
W911NF-07-1-0277 awarded by the Army Research Office. The
government has certain rights in the invention.
Claims
1-12. (canceled)
13. A nano-pillar transistor, comprising: a planar substrate
comprising a source segment and a drain segment; and a biomimetic
gate arranged between the source segment and the drain segment, the
gate comprising a pillar structure with a linear axis oriented
orthogonal to the planar substrate, the pillar structure
incorporating a first platinum-gold-platinum metal portion that
mimics a hydrophilic-hydrophobic-hydrophilic structure of a
cellular membrane.
14. The nano-pillar transistor of claim 13, further comprising a
first platinum portion fabricated upon the source segment and a
second platinum portion fabricated upon the drain segment.
15. The nano-pillar transistor of claim 14, wherein the pillar
structure is a serrated pillar structure configured for anchoring
the biomimetic gate to animal tissue.
16. A system comprising: a nano-pillar transistor having a
biomimetic gate configured as a pillar structure with a linear axis
of the pillar structure oriented orthogonal to a substrate, the
pillar structure incorporating a platinum-gold-platinum metal
portion that mimics a hydrophilic-hydrophobic-hydrophilic structure
of a cellular membrane.
17. The system of claim 16, comprising a common-source amplifier
that is implantable in the cellular membrane, the common-source
amplifier including the nano-pillar transistor.
18. The system of claim 16, comprising a current mirror circuit
incorporating the nano-pillar transistor.
19. The system of claim 18, wherein a gate terminal of the
nano-pillar transistor is arranged to make contact with animal
tissue for sensing a voltage provided by the animal tissue.
20. The system of claim 19, wherein the voltage provided by the
animal tissue is a trans-membrane cellular voltage.
21. The system of claim 19, further comprising: a variable
frequency generator, wherein the current mirror circuit is coupled
to the variable frequency generator for providing at least a first
control current and a second control current, the variable
frequency generator configured to generate a first signal having a
first frequency or a second signal having a second frequency, in
response to receiving the first or the second control current
respectively.
22. The system of claim 21, wherein the variable frequency
generator comprises a voltage controlled oscillator.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application claims priority under 35 U.S.C.
.sctn.119(e) from U.S. Provisional Patent Application No.
61/617,528 entitled "Transmembrane Pillar FET" filed on Mar. 29,
2012, which is incorporated herein by reference in its entirety.
Furthermore, the present application is related to US Patent
Application No. ______ filed on even date herewith, entitled
"Sensor Probe for Bio-sensing and Chemical-sensing Applications,"
Attorney Docket No. P1228-US, which is also incorporated herein by
reference in its entirety.
FIELD
[0003] The present teachings relate to nano-transistors. In
particular, the present teachings relate to fabricating and using a
field-effect nano-transistor having a biomimitec
characteristic.
BACKGROUND
[0004] Extracellular electrodes are often too large for use in
applications where the target cells have small size. For example,
extracellular electrodes are generally too big for measuring single
neuron behavior. Even when miniaturized, many prior art electrodes
suffer from other handicaps such as being vibration sensitive and
causing cell death due to materials incompatibility. It is
therefore desirable to provide an implantable electrode device that
is not only small in size but also contains materials that are
suitable for benign implantation of the device into cellular
entities.
SUMMARY
[0005] According to a first aspect of the present disclosure, a
method of fabricating a nano-pillar transistor, includes the
following steps: providing a polymer coating upon a silicon
substrate; using electron beam lithography to fabricate a mask
pattern in the polymer coating; depositing an alumina film upon the
mask pattern; creating a hard-etch mask by using a solvent to
remove a portion of the alumina film and a portion of the polymer
coating; using the hard-etch mask for executing a first etching
procedure to create a plurality of nano-pillars; executing a second
etching procedure for reducing a diameter of each of the plurality
of nano-pillars, wherein the plurality of nano-pillars having the
reduced diameter constitutes a plurality of gates of an array of
nano-pillar transistors; using an ion beam procedure to introduce
dopants for fabricating each of a source region and a drain region
adjacent to each of the plurality of gates; applying electron beam
annealing of the dopants; using one of an ion milling procedure or
a reactive ion etching procedure to remove deposited alumina film
from a top portion of each of the plurality of gates; applying
metallization upon each of the plurality of gates and upon each of
the source region and the drain region adjacent to each of the
plurality of gates; and depositing alternating metal stacks between
each of the metalized plurality of gates, wherein the alternating
metal stacks mimic a hydrophilic-hydrophobic-hydrophilic structure
of a cellular membrane.
[0006] According to a second aspect of the present disclosure, a
nano-pillar includes a planar substrate and a biomimitec gate. The
planar substrate includes a source segment and a drain segment. The
biomimetic gate, which is arranged between the source segment and
the drain segment, has a pillar structure with a linear axis
oriented orthogonal to the planar substrate, the pillar structure
incorporating a first platinum-gold-platinum metal portion that
mimics a hydrophilic-hydrophobic-hydrophilic structure of a
cellular membrane.
[0007] According to a third aspect of the present disclosure, a
system includes a nano-pillar transistor having a biomimetic gate
configured as a pillar structure with a linear axis of the pillar
structure oriented orthogonal to a substrate. The pillar structure
incorporates a platinum-gold-platinum metal portion that mimics a
hydrophilic-hydrophobic-hydrophilic structure of a cellular
membrane.
[0008] Further aspects of the disclosure are shown in the
specification, drawings and claims of the present application.
BRIEF DESCRIPTION OF THE DRAWINGS
[0009] Many aspects of the present disclosure can be better
understood with reference to the following drawings. The components
in the drawings are not necessarily drawn to scale. Instead,
emphasis is placed upon clearly illustrating various principles.
Moreover, in the drawings, like reference numerals designate
corresponding parts throughout the several views.
[0010] FIG. 1 shows various stages during fabrication of an array
of nano-pillar transistors in accordance with the disclosure.
[0011] FIG. 2 shows a structural cross-section of a nano-pillar
transistor in accordance with the disclosure.
[0012] FIG. 3 shows an example nano-pillar transistor having a gate
that is shaped to provide improved anchoring in cellular entities
in accordance with the disclosure.
[0013] FIG. 4 shows a common-source voltage amplifier incorporating
a nano-pillar transistor in accordance with the disclosure.
[0014] FIG. 5 shows a current mirror circuit incorporating a
nano-pillar transistor in accordance with the disclosure.
[0015] FIG. 6 shows a detection system incorporating the current
mirror circuit shown in FIG. 5.
DETAILED DESCRIPTION
[0016] Throughout this description, embodiments and variations are
described for the purpose of illustrating uses and implementations
of the inventive concept. The illustrative description should be
understood as presenting examples of the inventive concept, rather
than as limiting the scope of the concept as disclosed herein. It
will be understood that various labels such as, for example,
nano-pillar transistor, nano-transistor, field effect nano-pillar
transistor, field effect transistor, contacts, and terminals are
used herein in an alternative manner as a matter of convenience and
are to be interpreted appropriately in the context of the
description, without attaching illogical and unusual restrictions
to these terms. It will be also understood that phrases such as
plurality of nano-pillar transistors, plurality of gates, and
plurality of nano-pillar field effect transistors are used herein
in an alternative manner as a matter of convenience and are to be
interpreted appropriately in the context of the description,
without attaching illogical and unusual restrictions to these
phrases.
[0017] Field effect transistors can be used as sensors for a
variety of applications, including bio-sensing applications. In
accordance with the disclosure, a field effect nano-pillar
transistor has a pillar shaped gate element incorporating a
biomimitec portion that provides various advantages over prior art
devices. The small size of the nano-pillar transistor disclosed
herein allows for advantageous insertion into cellular membranes,
and the biomimitec character of the gate element operates as an
advantageous interface for sensing small amplitude voltages such as
trans-membrane cell potentials. The nano-pillar transistor can be
used in various embodiments to stimulate cells, to measure cell
response, or to perform a combination of both actions.
[0018] In some example embodiments, the nano-pillar transistor
disclosed herein can be configured to execute a multiplexed mode of
operation (for example, a time multiplexed mode of operation)
whereby the same nano-pillar transistor can be used to inject a
current into a cell (writing to the cell) and then measure the
electrical response to the current injection (reading the
cell).
[0019] Attention is now drawn to FIG. 1, which shows various stages
during fabrication of an array of nano-pillar transistors in
accordance with the disclosure. Each of the stages is referenced by
a numeric label, and these numerical labels will be used below as a
matter of convenience for purposes of description.
[0020] In stage 101, a highly doped silicon wafer 150 is spin
coated with a polymer (not shown). In one example embodiment, the
polymer is poly-methyl-methacrylate (PMMA). In stage 102, a soft
mask 155 is written into the polymer using electron beam
lithography for example. The resulting mask pattern is shown in
stage 103, where the dark shaded areas 160 indicate areas in which
material is to be removed in subsequent stages of fabrication. In
stage 104, a polymer development procedure is performed, followed
(in stage 105) by sputter deposition of an alumina film 165. In one
example implementation, the alumina film is about 45 nm thick. In
another example implementation, RF sputtering is used to deposit
stoichiometric Al.sub.2O.sub.3.
[0021] In stage 106, excess alumina and polymer is removed, leaving
behind a hard etch-mask that is in direct contact with the silicon
wafer 150. In one example implementation, excess alumina and
polymer is removed by lift-off in dichloromethane.
[0022] In stage 107, a plurality of silicon nano-pillars are
defined using deep reactive ion etching techniques. Each of the
plurality of silicon nano-pillars is used to fabricate an
individual biomimetic gate terminal of an individual nano-pillar
field-effect transistor. Side-wall passivation is achieved by using
cryogenic cooling of the sidewalls of the nano-pillars. In one
example implementation, the cryogenic cooling temperature is about
-140.degree. Celsius. A 90 sccm:10 sccm SF6:02 gas ratio may be
used during the etching. An inductively coupled plasma power of
1800 W and a forward power of about 5 W may be used to define
silicon nano-pillars that are between 100 nm and 10 microns tall.
The height may be selected in order to provide aspect ratios
(height:width) extending up to 100:1.
[0023] In stage 108, a short, under-passivated Bosch etch is used
to shrink the width of the plurality of silicon nano-pillars,
followed by oxidization (stage 109) to provide isolation between
the silicon nano-pillars. The oxidation stage is carried out when
the silicon nano-pillars are intended for fabricating MOSFET, JFET,
or MESFET types of nano-transistors. However, stage 109 may be
omitted when fabricating other types of nano-transistors.
[0024] In stage 110, focused-ion beam lithography is used for
introducing dopants into silicon substrate 150 in order to define
source segment 175 and drain segment 180. In stage 111,
electron-beam annealing of the dopants is performed.
[0025] In stage 112, source, drain and gate metallization is
carried out using electron-beam evaporation techniques. When the
plurality of silicon nano-pillars (gates) are intended for
bio-sensing applications, a biomimitec structure is fabricated upon
each of the nano-pillars. In one embodiment, the biomimitec
structure is a platinum-gold-platinum metal stack formed of a gold
layer 190 sandwiched between a pair of platinum layers 185. The
platinum-gold-platinum metal stack mimics the
hydrophilic-hydrophobic-hydrophilic structure of cellular
membranes, allowing for easy integration into biological systems.
In stage 103, metal contacts are fabricated upon each of the source
segment 175 and drain segment 180. In one implementation, the metal
used is gold. Sulfur chemistry is then used to form Au-S thiol
bonds and complete the fabrication of the array of nano-pillar
transistors.
[0026] After stage 113 is completed, a singulating procedure is
performed to produce individual nano-pillar transistors from the
array of nano-pillar transistors.
[0027] FIG. 2 shows a structural cross-section of one such
individual nano-pillar transistor 200 in accordance with the
disclosure. The structural cross-section provides an indication of
some dimensional values that may be used in the nano-pillar
transistor. Furthermore, the gate terminal of the nano-pillar
transistor, which is located between the source and the drain, has
a pillar structure with a linear axis 201 oriented orthogonal to
the planar substrate 150.
[0028] FIG. 3 shows a nano-pillar transistor 300 having a gate that
is shaped to provide improved anchoring in cellular membranes.
While one example shape is indicated in the embodiment shown in
FIG. 3, it will be understood that in other embodiments, the gate
can be fabricated in a variety of shapes including, for example,
one having a serrated surface texture, a tapered straight line
profile, a tapered curved profile, a multi-curved profile etc.
These various shapes and surface textures can be fabricated for
example by using repeated under-passivated and
critically-passivated pseudo-Bosch etches. The serrated surface can
be based on the type of anchoring desired, such as for anchoring on
to neurons or to other types of biological surfaces.
[0029] A nano-pillar transistor in accordance with the disclosure
can be used in a variety of devices, circuits and systems. A few
examples are described below.
[0030] FIG. 4 shows a common-source voltage amplifier 400
incorporating a nano-pillar transistor 410 in accordance with the
disclosure. A transmembrane cellular potential, which in one
implementation is in the range of -200 mV to 200 mV with respect to
solution potential, affects a change to the gate 411 of nano-pillar
transistor 410. This change results in placing nano-pillar
transistor 410 in a saturated conduction state. Careful tuning of
gate dimensions such as length, width, and geometry can be used to
adjust gain, sensitivity, and bandwidth parameters.
[0031] FIG. 5 shows a current mirror circuit 500 incorporating a
nano-pillar transistor 510 in accordance with the disclosure. It
should be understood that in some embodiments the other transistors
shown in FIG. 5 may also be nano-pillar transistors, while in other
embodiments other types of transistors may be used. A neuron
voltage at gate 511 of nano-pillar transistor 510 is converted by
current mirror circuit 500 into a current that can be decoded by
various detection circuits, such as, for example, detection circuit
600 shown in FIG. 6.
[0032] Detection circuit 600 includes current mirror 500 coupled to
a variable frequency generator 605. In some implementations,
variable frequency generator 605 includes a voltage controlled
oscillator (not shown).
[0033] In one example embodiment, current mirror 500 generates a
first control current in response to a first neuron voltage present
on line 511. The first control current is propagated via line 610
from current mirror 500 to variable frequency generator 605.
Furthermore, current mirror 500 generates a second control current
in response to a second neuron voltage present on line 511. The
second control current is also propagated via line 610 from current
mirror 500 to variable frequency generator 605.
[0034] Variable frequency generator 605 generates a first signal at
a first frequency when the first control current is provided via
line 610. The first signal is output on line 615. Variable
frequency generator 605 generates a second signal at a second
frequency when the second control current is provided via line 610.
The second signal is also output on line 615. The occurrence of the
first and second signals are indicative of different voltage levels
produced by one or more neurons and can be used for carrying out
various measurement procedures.
[0035] Drawing attention once again to FIG. 1, it will be
understood that as a result of the fabrication process, which can
be carried out using standard CMOS fabrication techniques,
nano-pillar transistor 510 can be incorporated into various types
of integrated circuits. For example, a nano-pillar transistor in
accordance with the disclosure can be fabricated in the form of an
application specific integrated circuit (ASIC) for use as an
integrated sensor device.
[0036] Furthermore, a plurality of nano-pillar transistors can be
coupled together in a parallel configuration in order to provide
more current capacity and/or to reduce parasitic capacitances and
resistances in various measurement applications.
[0037] All patents and publications mentioned in the specification
may be indicative of the levels of skill of those skilled in the
art to which the disclosure pertains. All references cited in this
disclosure are incorporated by reference to the same extent as if
each reference had been incorporated by reference in its entirety
individually.
[0038] It is to be understood that the disclosure is not limited to
particular methods or systems, which can, of course, vary. It is
also to be understood that the terminology used herein is for the
purpose of describing particular embodiments only, and is not
intended to be limiting. As used in this specification and the
appended claims, the singular forms "a," "an," and "the" include
plural referents unless the content clearly dictates otherwise. The
term "plurality" includes two or more referents unless the content
clearly dictates otherwise. Unless defined otherwise, all technical
and scientific terms used herein have the same meaning as commonly
understood by one of ordinary skill in the art to which the
disclosure pertains.
[0039] A number of embodiments/implementations of the disclosure
have been described. Nevertheless, it will be understood that
various modifications may be made without departing from the spirit
and scope of the present disclosure. Accordingly, other embodiments
are within the scope of the following claims.
* * * * *