U.S. patent application number 14/019621 was filed with the patent office on 2014-11-20 for semiconductor system.
This patent application is currently assigned to SK hynix Inc.. The applicant listed for this patent is SK hynix Inc.. Invention is credited to Hyeng Ouk LEE.
Application Number | 20140344654 14/019621 |
Document ID | / |
Family ID | 51896819 |
Filed Date | 2014-11-20 |
United States Patent
Application |
20140344654 |
Kind Code |
A1 |
LEE; Hyeng Ouk |
November 20, 2014 |
SEMICONDUCTOR SYSTEM
Abstract
A semiconductor system including a semiconductor circuit
configured to compare a first error detection code generated by
performing an operation on read data to a second error detection
code and determine a data transmission error, and a controller
configured to provide the second error detection code, generated by
performing an operation on expect data based on the read data, to
the semiconductor circuit.
Inventors: |
LEE; Hyeng Ouk; (Icheon-si,
KR) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
SK hynix Inc. |
Icheon-si |
|
KR |
|
|
Assignee: |
SK hynix Inc.
Icheon-si
KR
|
Family ID: |
51896819 |
Appl. No.: |
14/019621 |
Filed: |
September 6, 2013 |
Current U.S.
Class: |
714/807 |
Current CPC
Class: |
G06F 11/10 20130101;
G06F 11/1004 20130101 |
Class at
Publication: |
714/807 |
International
Class: |
G06F 11/10 20060101
G06F011/10 |
Foreign Application Data
Date |
Code |
Application Number |
May 20, 2013 |
KR |
10-2013-0056427 |
Claims
1. A semiconductor system comprising: a semiconductor circuit
configured to compare a first error detection code generated by
performing an operation on read data to a second error detection
code and determine a data transmission error; and a controller
configured to provide the second error detection code, generated by
performing an operation on expect data based on the read data, to
the semiconductor circuit.
2. The semiconductor system of claim 1, wherein the semiconductor
circuit is configured to output an error address signal
corresponding to the read data, when a result obtained by
determining the data transmission error corresponds to an
error.
3. The semiconductor system of claim 2, further comprising an error
address storage unit configured to store the error address
signal.
4. The semiconductor system of claim 3, wherein the error address
storage unit is provided inside or outside the semiconductor
circuit.
5. The semiconductor system of claim 3, wherein the error address
storage unit is configured to store the error address signal in
response to a test mode signal.
6. The semiconductor system of claim 2, wherein the semiconductor
circuit is configured to output the error address signal through
any one of input/output pins.
7. The semiconductor system of claim 1, wherein the semiconductor
circuit comprises: a data input/output unit configured to perform a
data interface operation between a memory area of the semiconductor
circuit and the controller; and an error detection unit configured
to generate the first error detection code by performing an
operation on the read data provided through the data input/output
unit, and transmit an error detection signal generated by comparing
the second error detection code and the first error detection code
to the controller.
8. The semiconductor system of claim 7, wherein the error detection
unit comprises: error detection code generation logic configured to
generate the first error detection code by performing a
predetermined operation on the read data; a comparator configured
to sequentially compare a plurality of signal bits of the first
error detection code to a plurality of signal bits of the second
detection code, and output the comparison results; and a detector
configured to generate an error detection signal having different
logic values depending on the sequential outputs of the
comparator.
9. The semiconductor system of claim 2, wherein the semiconductor
circuit comprises: a data input/output unit configured to perform a
data interface operation between a memory area of the semiconductor
circuit and the controller; an error detection unit configured to
generate the first error detection code by performing an operation
on the read data and transmit an error detection signal generated
by comparing the second error detection code and the first error
detection code to the controller; and a storage control unit
configured to output the error address signal when the error
detection signal has a value corresponding to a data transmission
error.
10. The semiconductor system of claim 1, wherein the controller
comprises: a data input/output unit configured to perform a data
interface operation between a memory area of the controller and the
semiconductor circuit; and an error detection unit configured to
transmit the second error detection code, generated by performing
an operation on the expect data, to the semiconductor circuit.
11. The semiconductor system of claim 1, wherein the semiconductor
circuit is configured to transmit an error detection signal, based
on the result obtained by determining the data transmission error,
to the controller after column address strobe latency from the time
point at which a read command is inputted.
12. A semiconductor system comprising: a plurality of semiconductor
circuits configured to compare a first error detection code
generated by performing an operation on commonly-provided expect
data to a second error detection code generated by performing an
operation on read data, generate an error detection code, and
output the generated error detection signal; and a tester
configured to commonly provide write data, provided to the
plurality of semiconductor circuits during a write operation before
the expect data are provided, as the expect data to the plurality
of semiconductor circuits.
13. The semiconductor system of claim 12, wherein each of the
semiconductor circuits is configured to determine a data
transmission error according to the result obtained by comparing
the first and second error detection codes and output an error
address signal corresponding to the read data to the outside when
the determination result corresponds to an error.
14. The semiconductor system of claim 13, wherein the semiconductor
circuit provides the error address signal to the outside through
any one of input/output pins thereof.
15. The semiconductor system of claim 12, wherein each of the
semiconductor circuits comprises: a data input/output unit
configured to perform a data interface operation between a memory
area thereof and the tester; and an error detection unit configured
to transmit an error detection signal generated by comparing the
second error detection code and the first error detection code to
the tester.
16. The semiconductor system of claim 15, wherein the error
detection unit comprises: error detection code generation logic
configured to generate the first error detection code by performing
a predetermined operation on the expect data provided through the
data input/output unit, and generate the second error detection
code by performing a predetermined operation on the read data
provided through the data input/output unit; a comparator
configured to sequentially compare a plurality of signal bits of
the first error detection code to a plurality of signal bits of the
error detection code and output the comparison results; and a
detector configured to generate the error detection signal
according to the sequential outputs of the comparator.
17. The semiconductor system of claim 13, wherein the semiconductor
circuit comprises: a data input/output unit configured to perform a
data interface operation between a memory area thereof and the
tester; an error detection unit configured to transmit the error
detection signal generated by comparing the second error detection
code and the first error detection code to the tester; and a
storage control section configured to output the error address
signal to the outside of the semiconductor circuit, when the error
detection signal has a value corresponding to a data transmission
error.
18. The semiconductor system of claim 12, wherein the tester
comprises a tester configured to provide the write data to the
plurality of semiconductor circuits during the write operation and
commonly provide the write data as the expect data to the plurality
of semiconductor circuits during a read operation.
19. The semiconductor system of claim 12, wherein the tester
comprises: a data input/output unit configured to perform a data
interface operation between a memory area thereof and the plurality
of semiconductor circuits; and an error information storage unit
configured to store the error detection signal.
20. The semiconductor system of claim 13, wherein the tester
comprises: a data input/output unit configured to perform a data
interface operation between a memory area thereof and the plurality
of semiconductor circuits; and an error information storage unit
configured to store the error detection signal and the error
address signal.
21. The semiconductor system of claim 12, wherein the plurality of
semiconductor circuits are configured to transmit the error
detection signal to the tester after column address strobe latency
from the time point at which a read command is inputted.
Description
CROSS-REFERENCES TO RELATED APPLICATION
[0001] The present application claims priority under 35 U.S.C.
.sctn.119(a) to Korean application number 10-2013-0056427, filed on
May 20, 2013, in the Korean Intellectual Property Office, which is
incorporated herein by reference in its entirety.
BACKGROUND
[0002] 1. Technical Field
[0003] Various embodiments relate to a semiconductor circuit, and
more particularly, to a semiconductor system.
[0004] 2. Related Art
[0005] Due to various causes including noise introduced into a
transmission line, an error may occur in data transmitted between a
first device (for example, a semiconductor circuit) and a second
device (for example, a controller to control the semiconductor
circuit or a tester for testing the semiconductor circuit).
[0006] Thus, there is a demand for a method for checking and
detecting whether or not the data was or is being normally
transmitted between the two devices.
SUMMARY
[0007] Various embodiments are directed to a semiconductor system
capable of detecting whether data was or is being normally
transmitted or not and an error address.
[0008] In an embodiment of the present invention, a semiconductor
system includes: a semiconductor circuit configured to compare a
first error detection code generated by performing an operation on
read data to a second error detection code and determine a data
transmission error; and a controller configured to provide the
second error detection code, generated by performing an operation
on expect data based on the read data, to the semiconductor
circuit.
[0009] The semiconductor circuit may be configured to output an
error address signal corresponding to the read data to the outside,
when a result obtained by determining the data transmission error
corresponds to an error.
[0010] In an embodiment of the present invention, a semiconductor
system includes: a plurality of semiconductor circuits configured
to compare a first error detection code generated by performing an
operation on commonly-provided expect data to a second error
detection code generated by performing an operation on read data,
generate an error detection code, and output the generated error
detection signal; and a tester configured to commonly provide write
data, provided to the plurality of semiconductor circuits during a
write operation before the expect data are provided, as the expect
data to the plurality of semiconductor circuits.
[0011] Each of the semiconductor circuits may be configured to
determine a data transmission error according to the result
obtained by comparing the first and second error detection codes
and output an error address signal corresponding to the read data
to the outside when the determination result corresponds to an
error.
[0012] In an embodiment of the present invention, a semiconductor
system includes: a semiconductor circuit including a first data
input/output unit and a first error detection unit, the first data
input/output unit being communicatively coupled with the first
error detection unit, and the first error detection unit configured
to generate a first error detection code based on data provided
from the first data input/output unit; and a controller including a
second data input/output unit and a second error detection unit,
the second data input/output unit being communicatively coupled
with the second error detection unit, and the second error
detection unit configured to generate a second error detection code
based on data provided from the second data input/output unit;
wherein the semiconductor circuit and controller are
communicatively coupled to each other through input/output pins;
and wherein the second error detection unit compares the first
error detection code with the second error detection code.
BRIEF DESCRIPTION OF THE DRAWINGS
[0013] Features, aspects, and embodiments are described in
conjunction with the attached drawings, in which:
[0014] FIG. 1 is a block diagram illustrating the configuration of
a semiconductor system 100 according to an embodiment of the
present invention;
[0015] FIG. 2 is a block diagram illustrating the configuration of
a semiconductor system 200 according to an embodiment of the
present invention;
[0016] FIG. 3 is an operation timing diagram based on FIG. 2;
[0017] FIG. 4 is a block diagram illustrating the configuration of
a semiconductor system 300 according to an embodiment of the
present invention; and
[0018] FIG. 5 is an operation timing diagram based on FIG. 4.
DETAILED DESCRIPTION
[0019] Hereinafter, a semiconductor system according to the present
invention will be described below with reference to the
accompanying drawings through various examples of embodiments.
[0020] FIG. 1 is a block diagram illustrating the configuration of
a semiconductor system 100 according to an embodiment of the
present invention.
[0021] FIG. 1 illustrates an example of a semiconductor system
based on a semiconductor circuit and a controller.
[0022] Referring to FIG. 1, the semiconductor system 100 according
to the embodiments of the present invention may include a
semiconductor circuit 110 and a controller 120.
[0023] The semiconductor circuit 110 may include input/output pins
PIN<0:k> coupled to input/output pins PIN<0:k> of the
controller 120, respectively.
[0024] Additionally, error information may be transmitted through
any one of the input/output pins PIN<0:k>, for example, the
input/output pin PIN<k>, and data may be transmitted through
the other input/output pins PIN<0:j>.
[0025] The semiconductor circuit 110 may include a data
input/output unit 111 and error detection code generation logic
113.
[0026] The data input/output unit 111 may be configured to perform
a data interface operation between a memory area thereof and the
controller 120 and the error detection code generation logic 113
according to a write command or read command. The memory area is
not illustrated and may be referred to as a first memory area, for
convenience of description.
[0027] The data input/output unit 111 may transmit data,
transmitted through the input/output pins PIN<0:j> from the
controller 120, to the error detection code generation logic 113 or
the first memory area according to a write command.
[0028] The data input/output unit 111 may transmit data outputted
from the first memory area to the error detection code generation
logic 113 or transmit the data to the controller 120 through the
input/output pins PIN<0:j> according to a read command.
[0029] The data input/output unit 111 may include a
serializer/deserializer (SERDES).
[0030] Additionally, although not illustrated, various commands
including write and read commands, addresses, clock signals and the
like may be provided from the controller 120.
[0031] The error detection code generation logic 113 is configured
to generate an error detection code (referred to as a first error
detection code, for convenience of description) for the data
provided from the data input/output unit 111.
[0032] In these embodiments associated with FIG. 1 of the present
invention, cyclic redundancy check (CRC) may be used as the error
detection code generation logic 113.
[0033] The first error detection code may include a plurality of
signal bits.
[0034] The controller 120 may include a data input/output unit 121
and an error detection unit 122.
[0035] The data input/output unit 121 may be configured to perform
a data interface operation between the outside of the system or a
memory area thereof and the semiconductor circuit 110 and the error
detection unit 122. The memory area is not illustrated and may be
referred to as a second memory area, for convenience of
description.
[0036] The error detection unit 122 may be configured to generate
an error detection code (referred to as a second error detection
code, for convenience of description) for data provided from the
data input/output unit 121, compare the error detection code to the
first error detection code provided from the semiconductor circuit
110, and determine whether or not the data is being or has been
normally transmitted (pass or fail).
[0037] When the determination result is a fail, the error detection
unit 122 may retransmit a write command or read command to the
semiconductor circuit 110.
[0038] The error detection unit 122 may include error detection
code generation logic 123, a comparator 124, and a detector
125.
[0039] In these embodiments associated with FIG. 1 of the present
invention, CRC may be used as the error detection code generation
logic 123.
[0040] The CRC 123 may be configured to perform a predetermined
operation on the data provided from the data input/output logic 121
and generate the second error detection code.
[0041] Additionally, the second error detection code may include a
plurality of signal bits.
[0042] The comparator 124 may be configured to sequentially compare
the plurality of signal bits of the second error detection code to
the respective signal bits of the first detection code provided
from the semiconductor circuit 110 and sequentially output the
comparison results.
[0043] The detector 125 may be configured to determine whether or
not the sequential outputs of the comparator 124 define normal data
transmission (pass or fail).
[0044] FIG. 2 is a block diagram illustrating the configuration of
a semiconductor system 200 according to an embodiment of the
present invention.
[0045] FIG. 2 illustrates a semiconductor system based on a
semiconductor circuit and a controller, and a data transmission
test may be performed in connection with the controller in a state
where the semiconductor circuit is mounted in the system.
[0046] Referring to FIG. 2, the semiconductor system 200 according
to the embodiments of the present invention may include a
semiconductor circuit 210, a controller 220, and an error address
storage unit 230.
[0047] The semiconductor circuit 210 may include input/output pins
PIN<0:k> coupled to input/output pins PIN<0:k> of the
controller 220, respectively.
[0048] Additionally, error information may be transmitted through
any one of the error input/output pins PIN<0:k>, for example,
the input/output pin PIN<k>, and data may be transmitted
through the other input/output pins PIN<0:j>.
[0049] The semiconductor circuit 210 may include a data
input/output unit 211, an error detection unit 212, and a storage
control unit 216.
[0050] The data input/output unit 211 may be configured to perform
a data interface operation between a memory area thereof and the
controller 220 and the error detection unit 212 according to a
write command or read command. The memory area is not illustrated
and may be referred to as a first memory area, for convenience of
description.
[0051] The data input/output unit 211 may transmit data,
transmitted through the input/output pins PIN<0:j> from the
controller 220, to the error detection unit 212 or the first memory
area according to a write command.
[0052] The data input/output unit 211 may transmit data outputted
from the first memory area to the error detection unit 212 or
transmit the data to the controller 220 through the input/output
pins PIN<0:j> according to a read command.
[0053] The data input/output unit 211 may include a
serializer/deserializer (SERDES).
[0054] Additionally, although not illustrated, various commands
including write and read commands, addresses, clock signals CK (see
FIG. 3 as well) and the like may be provided from the controller
220.
[0055] The error detection unit 212 may be configured to generate
an error detection code (referred to as a first error detection
code, for convenience of description) for the data provided from
the data input/output unit 211.
[0056] The error detection unit 212 may be configured to generate
an error detection signal by comparing an error detection code
provided from the controller 220 (referred to as a second error
detection code, for convenience of description) to the first error
detection code, and transmit the generated error detection signal
to the controller 220.
[0057] The error detection unit 212 may include error detection
code generation logic 213, a comparator 214, and a detector
215.
[0058] In these embodiments associated with FIG. 2 of the present
invention, CRC may be used as the error detection code generation
logic 213.
[0059] The CRC 213 may be configured to perform a predetermined
operation on the data provided from the data input/output unit 211
and generate the first error detection code.
[0060] Additionally, the first error detection code may include a
plurality of signal bits.
[0061] The comparator 214 may be configured to sequentially compare
the plurality of signal bits of the first error detection code to
the respective signal bits of the second error detection code
provided from the controller 220 and sequentially output the
comparison results.
[0062] The detector 215 may be configured to generate an error
detection signal having a different logic value depending on
whether or not the sequential outputs of the comparator 214 define
normal data transmission (pass or fail), and provide the generated
error detection signal to the storage control unit 216 or transmit
the generated error detection signal to the controller 220 through
the input/output pin PIN<k>.
[0063] The storage control unit 216 may be configured to store an
error address signal, that is, an address signal ADD corresponding
to a fail in the error address storage unit 213 through the
input/output pin PIN<k>, when the error detection signal
outputted from the detector 215 indicates a fail.
[0064] The storage control unit 216 may be configured to operate
during a test mode.
[0065] Additionally, the semiconductor circuit 210 may enter the
test mode through the controller 220. As the semiconductor circuit
210 enters the test mode, the storage control unit 216 may be
enabled.
[0066] The error address storage unit 230 may be configured to
store the error address signal transmitted through the input/output
pin PIN<k>.
[0067] The error address storage unit 230 may be configured to
store the error address signal when a test mode signal TM is
activated.
[0068] Additionally, the test mode signal TM may be provided from
the controller 220 or the semiconductor circuit 210.
[0069] The controller 220 may include a data input/output unit 221
and an error detection unit 222.
[0070] The data input/output unit 221 may be configured to perform
a data interface operation between the outside of the system or a
memory area thereof and the semiconductor circuit 210 and the error
detection unit 222. The memory area is not illustrated and may be
referred to as a second memory area, for convenience of
description.
[0071] The data input/output unit 221 may be configured to transmit
data provided from the outside of the system or the second memory
area to the error detection unit 222 according to control of the
controller 220.
[0072] Additionally, the controller 220 may previously designate a
specific address with a write command to write specific data to the
semiconductor circuit 210 during a test process of the
semiconductor circuit 210.
[0073] Thus, the controller 220 may recognize expect data. That is,
the controller 220 may designate the same address as the address
designated with the write command in the semiconductor circuit 210
and output a read command, thereby recognizing data to be outputted
from the semiconductor circuit 220.
[0074] The error detection unit 222 may be configured to provide a
second error detection code, generated according to the expect
data, to the semiconductor circuit 210.
[0075] The error detection unit 222 may compare the second error
detection code to the first error detection code provided from the
semiconductor circuit 210 and may determine whether or not data is
being or has been normally transmitted (pass or fail).
[0076] When the determination result is a fail, the error detection
unit 222 may retransmit a write command or read command to the
semiconductor circuit 210.
[0077] The error detection unit 222 may include error detection
code generation logic 223, a comparator 224, and a detector
225.
[0078] In these embodiments associated with FIG. 2 of the present
invention, the CRC may be used as the error detection code
generation logic 223.
[0079] The CRC 223 may be configured to perform a predetermined
operation on the expect data and generate the second error
detection code.
[0080] Additionally, the second error detection code may include a
plurality of signal bits.
[0081] The comparator 224 may be configured to sequentially compare
the plurality of signal bits of the second error detection code to
the respective signal bits of the first error detection code
provided from the semiconductor circuit 210 and sequentially output
the comparison results.
[0082] The detector 225 may generate an error detection signal
having a different logic value depending on whether or not the
sequential outputs of the comparator 224 define normal data
transmission (pass or fail).
[0083] Hereafter, a data transmission test of the semiconductor
system 200 according to the embodiments of the present invention
will be described as follows.
[0084] FIG. 3 is an operation timing diagram based on FIG. 2.
[0085] First, the controller 220 controls the semiconductor circuit
210 to enter the test mode.
[0086] Then, the controller 220 designates a specific address with
a write command to write specific data to the semiconductor circuit
210.
[0087] Thus, the controller 220 may recognize expect data. That is,
the controller 220 may designate the same address as the address
designated with the write command and output a read command,
thereby recognizing data to be outputted from the semiconductor
circuit 210.
[0088] The controller 220 provides the expected data to the error
detection unit 222 through the data input/output unit 221.
[0089] Referring to FIG. 3, the controller 220 provides a read
command RD0 and the second error detection code generated through
the error detection unit 222 to the semiconductor circuit 210
through the input/output pin PIN<k>.
[0090] The semiconductor circuit 210 provides data (i.e., D0 to D7)
corresponding to the read command RD0 to the error detection unit
212 through the data input/output unit 211 in a state where the
semiconductor circuit 210 entered the test mode through the
controller 220.
[0091] The error detection unit 212 generates a first error
detection code for the data corresponding to the read command RD0,
and compares the generated first error detection code to the second
error detection code to generate an error detection signal.
[0092] When the error detection signal outputted from the error
detection unit 212 has a level defining a fail (for example, logic
low `L`), the storage control unit 216 outputs the error detection
signal and an error address signal, that is, address signals A0 to
A6 corresponding to the read command to the error address storage
unit 230 through the input/output pin PIN<k>.
[0093] At this time, the error detection signal and the error
address signal may be transmitted after column address strobe CAS
latency (CL).
[0094] The error address storage unit 230 stores the error address
signal when the test mode signal TM is activated.
[0095] FIG. 4 is a block diagram illustrating the configuration of
a semiconductor system 300 according to an embodiment of the
present invention.
[0096] FIG. 4 illustrates a semiconductor system based on a
plurality of semiconductor circuits and a tester, and a data
transmission test may be performed through the tester before the
plurality of semiconductor circuits are mounted in the system.
[0097] Referring to FIG. 4, the semiconductor system 300 according
to the embodiments of the present invention may include the
plurality of semiconductor circuits 310 to 330 and the tester
340.
[0098] The tester 340 may include input/output pins PIN<0:j>
which are commonly coupled to input/output pins PIN<0:j> of
the plurality of semiconductor circuits 310 to 330.
[0099] The tester 340 may further include input/output pins
PIN<k, l, m> which are independently coupled to an
input/output pin PIN<k> of the semiconductor circuit 310, an
input/output pin PIN<l> of the semiconductor circuit 320, and
an input/output pin PIN<m> of the semiconductor circuit
330.
[0100] The plurality of semiconductor circuits 310 to 330 may be
configured in substantially the same manner, and each of the
semiconductor circuits 310 to 330 may include a data input/output
unit 311, an error detection unit 312, and a storage control unit
316.
[0101] The data input/output unit 311 may be configured to perform
a data interface operation between a memory area thereof and the
tester 340 and the error detection unit 312 according to a write
command or read command. The memory area is not illustrated, and
may be referred to as a first memory area, for convenience of
description.
[0102] The data input/output unit 311 may transmit data,
transmitted through the input/output pins PIN<0:j> from the
tester 340, to the error detection unit 312 or the first memory
area according to a write command.
[0103] The data input/output unit 311 may transmit data outputted
from the first memory area to the error detection unit 312 or
transmit the data to the tester 340 through the input/output pins
PIN<0:j> according to a read command.
[0104] The data input/output unit 311 may include a
serializer/deserializer (SERDES).
[0105] Additionally, although not illustrated, various commands
including write and read commands, addresses, clock signals CK (see
FIG. 5 as well) and the like may be provided from the tester
340.
[0106] The error detection unit 312 may be configured to generate a
first error detection code and a second error detection code for
write data and read data provided through the data input/output
unit 311, respectively.
[0107] The error detection unit 312 may be configured to generate
an error detection signal by comparing the first and second error
detection codes and transmit the generated error detection signal
to the tester 340 through the input/output pin PIN<k>.
[0108] The error detection unit 312 may include error detection
code generation logic 313, a comparator 314, and a detector
315.
[0109] In these embodiments associated with FIG. 4 of the present
invention, CRC is used as the error detection code generation logic
313.
[0110] The error detection code generation logic 313 may include a
write cyclic redundancy check (WCRC) block and a read cyclic
redundancy check (RCRC) block.
[0111] The WCRC block may be configured to perform a predetermined
operation on write data provided through the data input/output unit
211 from the tester 340 and generate the first error detection
code.
[0112] At this time, the first error detection code may include a
plurality of signal bits.
[0113] The RCRC block may be configured to perform a predetermined
operation on read data provided from the first memory area, that
is, the memory area thereof and generate the second error detection
code.
[0114] At this time, the second error detection code may include a
plurality of signal bits.
[0115] The RCRC block may be configured to sequentially compare the
plurality of signal bits of the first error detection code to the
respective signal bits of the second error detection code and
sequentially output the comparison results.
[0116] The detector 315 may be configured to generate an error
detection signal having a different logic value depending on
whether the sequential outputs of the comparator 314 correspond to
a desired value or not (pass or fail).
[0117] The detector 315 may be configured to provide the error
detection signal to the storage control unit 316 or transmit the
data to the tester 340 through the input/output pin
PIN<k>.
[0118] The storage control unit 316 may be configured to transmit
an error address signal, that is, an address signal ADD
corresponding to a fail to the tester 340 through the input/output
pin PIN<k>, when the error detection signal outputted from
the detector 315 has a value defining a fail.
[0119] The tester 340 may include a data input/output unit 341 and
an error information storage unit 342.
[0120] The data input/output unit 341 may be configured to perform
a data interface operation between the outside or a memory area
thereof and the plurality of semiconductor memory circuits 310 to
330. The memory area is not illustrated and may be referred to as a
second memory area, for convenience of description.
[0121] The data input/output unit 341 may be configured to provide
write data to the plurality of semiconductor circuits 310 to 330
according to control of the tester 340.
[0122] The error information storage unit 342 may be configured to
store the error detection signal and the error address signal
provided from the semiconductor circuit 310.
[0123] Hereafter, a data transmission test of the semiconductor
system 300 according to the embodiments of the present invention
will be described.
[0124] FIG. 5 is an operation timing diagram based on FIG. 4.
[0125] The tester 340 transmits a write command and write data
designating a specific address to the plurality of semiconductor
circuits 310 to 330 at the same time or substantially the same
time.
[0126] Thus, the same data are written to the specific addresses of
the plurality of semiconductor circuits 310 to 330.
[0127] Referring to FIG. 5, the tester 340 transmits a read command
RD0 and expect data to the plurality of semiconductor circuits 310
to 330.
[0128] At this time, the expect data, which have been transmitted
with the write command to the plurality of semiconductor circuits
310 to 330 at the same time or substantially the same time, may
include data which are expected to be outputted from the plurality
of semiconductor circuits 310 to 330 according to the read command
RD0.
[0129] The plurality of semiconductor circuits 310 to 330 provide
data (i.e., D0 to D7) corresponding to the read command RD0 to the
error detection unit 312 through the data input/output unit
311.
[0130] The error detection unit 312 generates the first error
detection code for the expect data transmitted from the tester 340
using the WCRC block, and generates the second error detection code
for read data corresponding to the read command RD0 using the RCRC
block.
[0131] The error detection unit 312 compares the first and second
error detection codes and generates an error detection signal.
[0132] When the error detection signal outputted from the error
detection unit 312 has a level defining a data transmission fail
(for example, logic low `L`), the storage control unit 316 outputs
the error detection signal and an error address signal, that is, an
address signal ADD corresponding to the read command to the
input/output pin PIN<k>.
[0133] At this time, suppose that the error detection signal of the
semiconductor circuit 310 among the plurality of semiconductor
circuits 310 to 330 has a logic low level and the error detection
signals of the other semiconductor circuits 320 and 330 have a
logic high level.
[0134] After CAS latency (CL), the low-level error detection signal
(i.e., L) and the error address signal (i.e., A0 to A5) are
transmitted through the input/output pin PIN<k> of the tester
340, and the high-level error detection signal (i.e., H) is
transmitted through the input/output pins PIN<l,m>.
[0135] The error address signal and the error detection signals
transmitted from the plurality of semiconductor circuits 310 to 330
are stored in the error information storage unit 342.
[0136] According to the embodiments of the present invention, the
semiconductor system may detect whether data is being or has been
normally transmitted or not and an error address, and reduce a test
time.
[0137] While various embodiments have been described above, it will
be understood to those skilled in the art that the embodiments
described are by way of example only. Accordingly, the
semiconductor system described herein should not be limited based
on the described embodiments. Rather, the semiconductor system
described herein should only be limited in light of the claims that
follow when taken in conjunction with the above description and
accompanying drawings.
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