U.S. patent application number 13/893635 was filed with the patent office on 2014-11-20 for semiconductor structure and method for manufacturing the same.
This patent application is currently assigned to UNITED MICROELECTRONICS CORP.. The applicant listed for this patent is UNITED MICROELECTRONICS CORP.. Invention is credited to Kun-Huang Yu.
Application Number | 20140339632 13/893635 |
Document ID | / |
Family ID | 51895125 |
Filed Date | 2014-11-20 |
United States Patent
Application |
20140339632 |
Kind Code |
A1 |
Yu; Kun-Huang |
November 20, 2014 |
SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
Abstract
A semiconductor structure comprises a substrate having a first
conductive type; a deep well having a second conductive type formed
in the substrate and extending down from a surface of the
substrate; a first well and a second well respectively having the
first and second conductive types formed in the deep well, and
extending down from the surface of the substrate; a gate electrode
formed on the substrate and disposed between the first and second
wells; an isolation extending down from the surface of the
substrate and disposed between the gate electrode and the second
well; a conductive plug including a first portion and a second
portion electrically connected to each other, and the first portion
electrically connected to the gate electrode, and the second
portion comprising at least two fingers penetrating into the
isolation, and the fingers spaced apart and electrically connected
to each other.
Inventors: |
Yu; Kun-Huang; (New Taipei
City, TW) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
UNITED MICROELECTRONICS CORP. |
Hsinchu |
|
TW |
|
|
Assignee: |
UNITED MICROELECTRONICS
CORP.
Hsinchu
TW
|
Family ID: |
51895125 |
Appl. No.: |
13/893635 |
Filed: |
May 14, 2013 |
Current U.S.
Class: |
257/339 ;
438/286 |
Current CPC
Class: |
H01L 29/66689 20130101;
H01L 29/404 20130101; H01L 29/0649 20130101; H01L 29/407 20130101;
H01L 29/4238 20130101; H01L 29/7816 20130101; H01L 29/42376
20130101; H01L 29/66681 20130101; H01L 29/42372 20130101 |
Class at
Publication: |
257/339 ;
438/286 |
International
Class: |
H01L 29/40 20060101
H01L029/40; H01L 29/66 20060101 H01L029/66; H01L 29/78 20060101
H01L029/78 |
Claims
1. A semiconductor structure, comprising: a substrate having a
first conductive type; a deep well having a second conductive type,
formed in the substrate and extending down from a surface of the
substrate; a first well having the first conductive type, extending
down from the surface of the substrate and formed in the deep well;
a second well having the second conductive type, extending down
from the surface of the substrate and formed in the deep well, and
the second well spaced apart from the first well; a gate electrode,
formed on the substrate and disposed between the first and second
wells; an isolation, extending down from the surface of the
substrate and substantially disposed between the gate electrode and
the second well; a conductive plug, comprising: a first portion
connecting the gate electrode; and a second portion comprising at
least two fingers penetrating into the isolation, and the second
portion electrically connected to the first portion, and the
fingers spaced apart and electrically connected to each other; a
first doping electrode region having the second conductive type,
extending down from the surface of the substrate and formed within
the first well; and a second doping electrode region having the
second conductive type, extending down from the surface of the
substrate and formed within the second well; wherein the fingers
are disposed between the first doping electrode region and the
second doping electrode region.
2. The semiconductor structure according to claim 1, wherein one of
the fingers closest to a first side wall of the isolation near the
gate electrode is spaced apart from the first side wall of the
isolation at a first distance.
3. The semiconductor structure according to claim 2, wherein the
first distance is in a range of about 300 .ANG. to about 800
.ANG..
4. The semiconductor structure according to claim 1, wherein the
fingers of the second portion of the conductive plug are spaced
apart from a bottom surface of the isolation at a second
distance.
5. The semiconductor structure according to claim 4, wherein the
second distance is in a range of about 0.05 .mu.m to about 0.15
.mu.m.
6. The semiconductor structure according to claim 1, wherein the
gate electrode is extended toward to the second well and partially
overlapped with the isolation.
7. The semiconductor structure according to claim 1, wherein the
gate electrode is substantially aligned with a first side wall of
the isolation.
8. (canceled)
9. The semiconductor structure according to claim 1, wherein the
isolation is disposed between the gate electrode and the second
doping electrode region.
10. The semiconductor structure according to claim 1, wherein the
first portion of the conductive plug is disposed on the gate
electrode and contacts the gate electrode.
11. The semiconductor structure according to claim 1, wherein the
isolation is a single layer or a combination of multi-layers.
12. The semiconductor structure according to claim 11, wherein the
isolation is a shallow trench isolation (STI) or an oxide.
13. The semiconductor structure according to claim 11, wherein the
isolation comprises multi-layers selected from SiO.sub.2, SiON,
Si.sub.3N.sub.4, and materials with high dielectric constant.
14. A method of manufacturing a semiconductor structure,
comprising: providing a substrate having a first conductive type;
forming a deep well having a second conductive type in the
substrate and extending down from a surface of the substrate;
forming a first well having the first conductive type in the deep
well and extending down from the surface of the substrate; forming
a second well having the second conductive type in the deep well,
the second well extending down from the surface of the substrate
and spaced apart from the first well; forming an isolation
extending down from the surface of the substrate and part of the
isolation disposed in the second well; forming a gate electrode on
the substrate and disposed between the first and second wells; and
forming a conductive plug comprising a first portion and a second
portion electrically connected to each other, the first portion
connecting the gate electrode, and the second portion comprising at
least two fingers penetrating into the isolation, and the fingers
are spaced apart and electrically connected to each other; forming
a first doping electrode region having the second conductive type
within the first well and extending down from the surface of the
substrate; and forming a second doping electrode region having the
second conductive type within the second well and extending down
from the surface of the substrate, so as to dispose the fingers
between the first doping electrode region and the second doping
electrode region.
15. The method according to claim 14, wherein the gate electrode is
extended toward to the second well and partially overlapped with
the isolation.
16. The method according to claim 14, wherein the gate electrode is
substantially aligned with a first side wall of the isolation.
17. The method according to claim 14, wherein the first portion and
the second portion of the conductive plug are formed as one
integrated piece.
18. (canceled)
19. The method according to claim 14, wherein the isolation is
disposed between the gate electrode and the second doping electrode
region.
20. The method according to claim 14, wherein the first portion of
the conductive plug is disposed on the gate electrode and contacts
the gate electrode.
Description
BACKGROUND
[0001] 1. Technical Field
[0002] The disclosure relates in general to a semiconductor
structure and a method for manufacturing the same, and more
particularly to a semiconductor structure having conductive plug
with at least two fingers penetrating into the isolation, which
decreases the on-resistance (Ron) and increases the breakdown
voltage of the semiconductor structure simultaneously, thereby
improving the ratio of Ron to breakdown voltage (Ron/BVD).
[0003] 2. Description of the Related Art
[0004] Reduction of feature size, improvements of the rate, the
efficiency, the density and the cost per integrated circuit unit
are the important goals in the semiconductor technology. With the
development of semiconductor technology, high power devices have
been applied to a variety of electronic products in different
fields. Laterally diffused metal oxide semiconductor (LDMOS) or
extended drain metal oxide semiconductor (EDMOS) is widely used in
high voltage or high power PMIC (power management integrated
circuit) application as the driving device.
[0005] On-resistance (Ron) is one of key factors of the
semiconductor device. The lower the on-resistance or the specific
on-resistance (Ron-sp), the lower the power consumption of the
semiconductor device. Ron is a very important characteristic for
the PMIC products, especially for the portable IC devices. Many
improvements have been disclosed by modifying the structures of
LDMOS or EDMOS devices; for example, changing the shape of STI or
wells. However, Ron improvement is still limited on current LDMOS
or EDMOS devices. No more than about 5% of improvement on the ratio
of Ron to breakdown voltage (Ron/BVD) has been achieved by using
well scheme or implant optimization.
SUMMARY
[0006] The disclosure is directed to a semiconductor structure and
a method for manufacturing the same, particularly directed to a
semiconductor structure having a conductive plug with at least two
fingers penetrating into the isolation, which decreases the
on-resistance (Ron) and increases the breakdown voltage of the
semiconductor structure simultaneously, thereby improving the ratio
of the Ron to the breakdown voltage (Ron/BVD). The characteristic
of the device applied with the semiconductor structure of the
disclosure is enhanced consequently.
[0007] According to the embodiment, a semiconductor structure
comprises a substrate having a first conductive type; a deep well
having a second conductive type formed in the substrate and
extending down from a surface of the substrate; a first well having
the first conductive type formed in the deep well and extending
down from the surface of the substrate; and a second well having
the second conductive type formed in the deep well and extending
down from the surface of the substrate, and the second well spaced
apart from the first well; a gate electrode formed on the substrate
and disposed between the first and second wells; an isolation
extending down from the surface of the substrate and disposed
between the gate electrode and the second well; a conductive plug
including a first portion and a second portion electrically
connected to each other, and the first portion electrically
connected to the gate electrode, and the second portion comprising
at least two fingers penetrating into the isolation, and the
fingers spaced apart and electrically connected to each other.
[0008] According to another aspect of the disclosure, a method of
manufacturing semiconductor structure is provided, comprising steps
of providing a substrate having a first conductive type; forming a
deep well having a second conductive type in the substrate and
extending down from a surface of the substrate; forming a first
well having the first conductive type in the deep well and
extending down from the surface of the substrate; forming a second
well having the second conductive type in the deep well, the second
well extending down from the surface of the substrate and spaced
apart from the first well; forming an isolation extending down from
the surface of the substrate and part of the isolation disposed in
the second well; forming a gate electrode on the substrate and
disposed between the first and second wells; and forming a
conductive plug comprising a first portion and a second portion
electrically connected to each other, the first portion connecting
the gate electrode, and the second portion comprising at least two
fingers penetrating into the isolation, and the fingers are spaced
apart and electrically connected to each other.
BRIEF DESCRIPTION OF THE DRAWINGS
[0009] FIG. 1 is a partial drawing of a LDMOS device according to
an embodiment of the disclosure.
[0010] FIG. 2 is a partial drawing of a LDMOS device according to
another embodiment of the disclosure.
[0011] FIG. 3A and FIG. 3B illustrate the current paths of a LDMOS
device without conductive plug and the LDMOS device of FIG. 1 of
the embodiments during operation, respectively.
[0012] FIG. 4A and FIG. 4B respectively illustrate the breakdown
occurrence of the typical LDMOS device and the LDMOS device of FIG.
1 of the embodiments during operation.
[0013] FIG. 5A, FIG. 5B and FIG. 5C simply illustrate the top views
of three different types of the configurations of the conductive
plug and gate electrode of the LDMOS devices according to the
embodiments of the disclosure.
[0014] FIG. 6A.about.FIG. 6I are the simulation drawings depicting
the exemplary devices STD and Split 1.about.Split 8 in the
experiments.
DETAILED DESCRIPTION
[0015] The embodiments as illustrated below provide semiconductor
structures having conductive plugs comprising at least two fingers
and methods of manufacturing the same. The semiconductor structures
of the embodiments not only decrease the On-resistance (Ron) but
also increase the breakdown voltage (BVD) of the devices, thereby
efficiently improving the electrical characteristics of the
devices.
[0016] The embodiments are described in details with reference to
the accompanying drawings. The identical elements of the
embodiments are designated with the same reference numerals. Also,
it is also important to point out that the illustrations may not be
necessarily be drawn to scale, and that there may be other
embodiments of the present disclosure which are not specifically
illustrated. Thus, the specification and the drawings are to be
regard as an illustrative sense rather than a restrictive
sense.
[0017] FIG. 1 is a partial drawing of a LDMOS device according to
an embodiment of the disclosure. The LDMOS device 1 of the
embodiment includes a substrate 20 having a first conductive type
(such as P-type); a deep well 21 having a second conductive type
(such as N-type) formed in the substrate 20 and extending down from
a surface of the substrate 20; a first well 23 having the first
conductive type (such as P-type) extending down from the surface of
the substrate 20; a second well 24 having the second conductive
type (such as N-type) formed in the deep well 21 by extending down
from the surface of the substrate 20, and the second well 24 spaced
apart from the first well 23; a gate electrode 25 formed on the
substrate 20 and disposed between the first well 23 and the second
well 24; an isolation 27, such as an oxide or STI, extending down
from the surface of the substrate 20 and substantially disposed
between the gate electrode 25 and the second well 24.
[0018] The LDMOS device 1 further includes a first doping electrode
region 28 having the second conductive type formed within the first
well 23 and extending down from the surface of the substrate 20;
and a second doping electrode region 29 having the second
conductive type formed within the second well 24 and extending down
from the surface of the substrate 20. The isolation 27 is disposed
between the gate electrode 25 and the second doping electrode
region 29. The first doping electrode region 28 and the second
doping electrode region 29 function as the source and the drain of
the device, respectively. Accordingly, the gate electrode 25 and
the drain (i.e. the second doping electrode region 29) are
separated by the isolation 27 (ex: STI). In the embodiment, a third
doping region 232 having the first conductive type (ex: P-doping
region) is also formed in the first well (ex: P-well) 23 and
adjacent to the source (i.e. the first doping electrode region 28)
18 as a bulk.
[0019] Also, the LDMOS device 1 might include a field with the
second conductive type such as a HVN field 242 around the second
well 24. In one embodiment, the second doping electrode region 29,
the second well 24, the HVN field 242 and the deep well 21 are
implanted in an order from high to low doping concentrations,
respectively.
[0020] The LDMOS device 1 of the embodiment further includes a
conductive plug 26 comprising a first portion 261 and a second
portion 262 electrically connected to each other. The first portion
261 is electrically connected to the gate electrode 25, and the
second portion 262 comprises at least two fingers 262a penetrating
into the isolation 27. In other words, the second portion 262 of
the conductive plug 26 comprises n of fingers, n is an integer, and
n.gtoreq.2. As shown in FIG. 1, the fingers 262a are spaced apart
and electrically connected to each other. The fingers 262a of the
conductive plug 26 could be spaced apart from each other at the
same distance, or at the different distances.
[0021] Also, the first portion 261 of the conductive plug 26 is
disposed on the gate electrode 25 to contact the gate electrode 25,
as shown in FIG. 1. The first portion 261 and the fingers 262a of
the second portion 262 could be formed as one integrated piece.
[0022] Practically, the conductive plug 26 could be a tungsten
plug, or a plug made of other conductive materials. No extra mask
and photolithography step are required to manufacture the
semiconductor structure of the embodiment. Configuration of the
conductive plug 26 connected to the gate electrode 25 could be
achieved at the contact formation process (by photo and etching
steps) simultaneously.
[0023] As shown in FIG. 1, one of the fingers 262a of the second
portion 262 closest to the first side wall 271 of the isolation 27
near the gate electrode 25 is spaced apart from the first side wall
271 of the isolation 27 at a first distance, which is denoted as
d1. A width of the isolation (ex: STI) 27 is denoted as W.
Practically, the width of the isolation 27 is tunable for different
BVD requirement (ex: 30, 40, 50V). In one embodiment, the first
distance d1 is in a range of about 300 .ANG. to about 800 .ANG..
Also, the fingers 262a of the second portion 262 is spaced apart
from a bottom surface of the isolation 27 at a second distance d2.
In one embodiment, the second distance d2 is in a range of about
0.05 .mu.m to about 0.15 .mu.m; the ratio of the depth of the
fingers 262a to the depth of the isolation 27 is in a range of
about 0.4 to about 0.9. Also, the finger 262a of the second portion
262 farthest from the gate electrode 25 is spaced apart from the
second doping electrode region 29 at a third distance d3. In one
embodiment, the third distance d3 is in a range of about 1 .mu.m to
about 4 .mu.m. However, the disclosure is not limited to those
numerical ranges. The actual sizes of components in the conductive
plug 26, such as the first distance d1, the second distance d2, the
third distance d3, etc., could be adjusted according to the size of
the device in practical applications, such as bottom width of the
isolation 27 and the insertion depth of the fingers 262a of the
conductive plug 26.
[0024] Moreover, the isolation 27 of the embodiment could be a
single layer or a combination of multi-layers including several
insulating layers. The combination of multi-layers of the isolation
27 could be selected from SiO.sub.2, SiON, Si.sub.3N.sub.4, and
materials with high dielectric constant. For example, the isolation
27 is a combination of the SiO.sub.2 layer and the Si.sub.3N.sub.4
layer, which the Si.sub.3N.sub.4 layer functions as an etch stop
layer and facilitates controlling the second distance d2 precisely.
Examples of materials with high dielectric constant include
rare-earth (RE) oxides and lanthanide series metal oxides.
[0025] Furthermore, the gate electrode 25 could be extended toward
the second well 24 and partially overlapped with the isolation 27,
as shown in FIG. 1. However, the disclosure is not limited thereto.
The gate electrode 25 could be substantially aligned with the first
side wall 271 of the isolation 27, as shown in FIG. 2.
[0026] FIG. 2 is a partial drawing of a LDMOS device according to
another embodiment of the disclosure. Structures of the LDMOS
device 2 of FIG. 2 and the LDMOS device 1 of FIG. 1 are identical
except for the position of the gate electrode 25 and the number of
the fingers 262a. As shown in the LDMOS device 2 of FIG. 2, the
second portion 262 of the conductive plug 26 of the LDMOS device 3
includes three fingers 262a, and a first side wall 271 of the
isolation 27 is disposed beneath the gate electrode 25, and part of
the isolation 27 is disposed in the second well 24. Other details
of the conductive plug 26 in FIG. 2 could be referred to the
descriptions above, and are not redundantly described.
[0027] FIG. 3A and FIG. 3B illustrate the current paths of a LDMOS
device without conductive plug and the LDMOS device of FIG. 1 of
the embodiments during operation, respectively. The elements of
FIG. 3B and FIG. 1 are designated with the same reference numerals.
A typical LDMOS device of FIG. 3A comprises a P-substrate 10, a
N-deep well (NDW)11, a P-well 13 and a N-well 14 formed in the
N-deep well 11 by a distance, a gate electrode 15 formed on the
P-substrate 10 and substantially between the P-well 13 and the
N-well 14, an isolation 17 (such as shallow trench isolation, STI)
substantially between the gate electrode 15 and the N-well 14, two
heavy N-doping regions respectively formed in the P-well 13 and the
N-well 14 for being the source 18 and the drain 19. Also, a
P-doping region 132 is formed in the P-well 13 and adjacent to the
source 18 as a bulk.
[0028] In FIG. 3A, the typical LDMOS device without conductive plug
includes a channel area 150 and a charge-accumulation area 152. If
a positive bias is applied to the gate electrode 15, the negative
charges accumulate in the charge-accumulation area 152. In FIG. 3B,
the LDMOS device of the embodiment includes a channel area 250 and
the charge-accumulation areas 252a, 252b and 252c. Compared to the
LDMOS device of FIG. 3A, the charge-accumulation areas 252a-252c of
the LDMOS device of the embodiment of FIG. 3B is longer due to the
existence of the conductive plug 26 (i.e. the first portion 261 and
the fingers 262a of the second portion 262). If a positive bias is
applied to the gate electrode 25 of the embodiment, the negative
charges are distributed in the longer charge-accumulation areas
252a-252c and more close to drain side area, thereby reducing the
resistance in the extended drain area. Accordingly, the
on-resistance of the LDMOS device of the embodiment (as shown in
FIG. 1) has been efficiently decreased, especially at the condition
of low drain bias operation.
[0029] FIG. 4A and FIG. 4B respectively illustrate the breakdown
occurrence of the typical LDMOS device and the LDMOS device of FIG.
1 of the embodiments during operation. The elements of FIG. 4A and
FIG. 3A are designated with the same reference numerals. The
elements of FIG. 4B and FIG. 1 are designated with the same
reference numerals. Breakdown will occur in lightly doped PN
junctions, such as the boundaries between the P-type second wells
13, 23 and the N-type deep wells 11, 21 (i.e., positions of star
symbols depicted in FIG. 4A and FIG. 4B). The critical value of the
voltage, at which the breakdown of a P-N junction diode occurs, is
called the breakdown voltage. Since the LDMOS device of FIG. 1 has
the conductive plug 26 with fingers 262a as shown in FIG. 4B, the
fingers 262a of the second portion 262 function as the shielding
plates, resulting in the re-distribution of the lines of electric
force between the drain (i.e. the second doping electrode region
29) and the second well 23. Compared to the typical LDMOS device of
FIG. 4A, the lines of electric force close to the PN junctions at
which the breakdown occurs in FIG. 4B are not as dense as that in
FIG. 4A, and the breakdown voltage of the device is decreased due
to the change of the electric field.
[0030] Additionally, configuration of the conductive plug 26 and
gate electrode 25 could be varied depending on the actual needs of
the applications. FIG. 5A, FIG. 5B and FIG. 5C simply illustrate
the top views of three different types of the configurations of the
conductive plug and gate electrode of the LDMOS devices according
to the embodiments of the disclosure. As shown in FIG. 5A, the
conductive plug could be configured as a pattern of dots 56 (ex:
square shaped, rectangular, circular or the likes) separately
formed on the gate electrode 55. As shown in FIG. 5B, the
conductive plug could be configured as a pattern of rectangular
blocks 57 separately formed on the gate electrode 55. As shown in
FIG. 5C, the conductive plug could be configured as a long strip 58
formed on the gate electrode 55. It is, of course, noted that the
configurations of FIG. 5A-FIG. 5C are depicted only for
demonstration, not for limitation. It is known by people skilled in
the art that the shapes of the top surface of the conductive plug
and the area ratio of the conductive plug to the gate electrode
could be adjusted according to the requirements and/or
manufacturing method in the practical application.
[Relative Experiments]
[0031] In the relative experiments, the characteristics of
semiconductor structure would be affected by the number of the
fingers of the second portion 262 inserting the isolation 27. Two,
three or more fingers 262a of the second portion 262 inserting the
isolation 27 would cause the significant effect on the Ron/BVD
improvement. Also, the first distance d1 between the finger 262a of
the second portion 262 and the first side wall 271 of the isolation
27 has effects on not only the on-resistance but also the breakdown
voltage of the device. The closer the finger 262a to the first side
wall 271 of the isolation 27, the better results of the Ron/BVD
ratio.
[0032] Exemplary devices Split 1.about.Split 8 are provided for
conducting related simulations, and the results of measurements are
listed in Table 1. Please also refer FIG. 1 and FIG. 2 for the
structures of exemplary devices having the conductive plugs. The
exemplary devices Split 5.about.Split 8 are constructed as the
device of the embodiment, and the exemplary devices Split
1.about.Split 4 are constructed for comparison. FIG. 6A.about.FIG.
6I are the simulation drawings depicting the exemplary devices STD
and Split 1.about.Split 8 in the experiments. The first distance d1
between the finger 262a of the second portion 262 and the first
side wall 271 of the isolation 27 is also labeled in FIG. 6B, FIG.
6D.about.FIG. 6I. In the simulation, the width of the STI (i.e.
isolation 27 of FIG. 1/FIG. 2) is 2.8 .mu.m. Other conditions of
the exemplary devices STD and Split 1.about.Split 8 are briefly
described below.
[0033] STD (FIG. 6A): a device without conductive plug, and the
gate electrode extends and partially overlapped the STI.
[0034] Split 1 (FIG. 6B): a device with a conductive plug
comprising one finger penetrating into the STI, and the gate
electrode extends and partially overlapped the STI. The first
distance d1 is 1.55 .mu.m.
[0035] Split 2 (FIG. 6C): a device without conductive plug, and the
gate electrode substantially aligned with the STI.
[0036] Split 3 (FIG. 6D): a device with a conductive plug
comprising one finger penetrating into the STI, and the gate
electrode substantially aligned with the STI. The finger is close
to the first sidewall 271 of the isolation 27. The first distance
d1 is 0.21 .mu.m.
[0037] Split 4 (FIG. 6E): a device with a conductive plug
comprising one finger penetrating into the STI, and the gate
electrode substantially aligned with the STI. The finger is
distanced from the first sidewall 271 of the isolation 27. The
first distance d1 is 1.51 .mu.m.
[0038] Split 5 (FIG. 6F): a device with a conductive plug
comprising two fingers penetrating into the STI according to the
embodiment, and the gate electrode substantially aligned with the
STI. The first distance d1 is 0.21 .mu.m.
[0039] Split 6 (FIG. 6G): a device with a conductive plug
comprising three fingers penetrating into the STI according to the
embodiment, and the gate electrode substantially aligned with the
STI. The first distance d1 is 0.21 .mu.m.
[0040] Split 7 (FIG. 6H): a device with a conductive plug
comprising four fingers penetrating into the STI according to the
embodiment, and the gate electrode substantially aligned with the
STI. The first distance d1 is 0.21 .mu.m.
[0041] Split 8 (FIG. 6I): a device with a conductive plug
comprising three fingers penetrating into the STI according to the
embodiment, and the gate electrode extends and slightly overlapped
the STI for 0.2 .mu.m. The first distance d1 is 0.27 .mu.m.
[0042] The measurement results of the Ron, the BVD, and the Ron/BVD
of the exemplary devices are listed in Table 1.
[0043] The results of the experiments have shown that the
semiconductor structure of the embodiment do decrease the
on-resistance (Ron) and increase the breakdown voltage
simultaneously, and the ratio of Ron to breakdown voltage (Ron/BVD)
is also improved greatly. The breakdown voltages of four exemplary
devices (Split 5-Split 8) are 56V, 57V, 58V and 59V, respectively.
The specific on-resistances (Ron-sp, mohm.times.mm.sup.2) of four
exemplary devices (Split 5-Split 8) are 52.31, 51.78, 52.70 and
52.88, respectively. The ratios of specific on-resistance to
breakdown voltage (Ron-sp/BVD) of four exemplary devices (Split
5-Split 8) are 0.93, 0.91, 0.91 and 0.89, respectively. Ratios of
Ron-sp/BVD of four exemplary devices (Split 5-Split 8) have been
increased up to 24%, 26%, 27% and 28%, respectively.
TABLE-US-00001 TABLE 1 Ron-sp Ron-sp/BVD BVD (mohm .times. Ron-sp/
Improvement Device Structure d1 (V) mm.sup.2) BVD (%) STD -- NA 46
56.84 1.24 NA Split 1 Gate 1.55 .mu.m 49 56.50 1.15 7% W-plug Split
2 Poly align NA 38 59.27 1.56 -26% STI Split 3 Poly align 0.21
.mu.m 48 53.53 1.12 10% STI- W-plug Split 4 Poly align 1.51 .mu.m
42 58.08 1.38 -12% STI- W-plug Split 5 Finger 0.21 .mu.m 56 52.31
0.93 24% W-plug 1 Split 6 Finger 0.21 .mu.m 57 51.78 0.91 26%
W-plug 2 Split 7 Finger 0.21 .mu.m 58 52.70 0.91 27% W-plug 3 Split
8 Poly over 0.27 .mu.m 59 52.88 0.89 28% STI- W-plug
[0044] Accordingly, the semiconductor structure of the embodiments
having conductive plug comprising at least two fingers penetrating
the isolation not only decreases the on-resistance but also
increase the breakdown voltage of the semiconductor structure. The
simulation results have shown that the ratio of Ron/BVD is
significantly decreased. For PMIC (power management integrated
circuit) application, especially for the portable IC devices, the
characteristic and performance of the products applied with the
structure of the embodiment have been greatly improved. Moreover,
the structure of the embodiment could be implemented without
changing the device pitch and the manufacturing method thereof is
compatible with current process. Therefore, the structure of the
embodiment is feasible for mass production. Also, the devices
applied with the structure of the embodiment possess high
competitiveness in the commercial market.
[0045] While the disclosure has been described by way of example
and in terms of the exemplary embodiment(s), it is to be understood
that the disclosure is not limited thereto. On the contrary, it is
intended to cover various modifications and similar arrangements
and procedures, and the scope of the appended claims therefore
should be accorded the broadest interpretation so as to encompass
all such modifications and similar arrangements and procedures.
* * * * *